MAS7848L MICRONAS | Alldatasheet
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° MICRONAS S6E D MM 6111560 0000194 Tit MENCRN “SS M| IC < ONAS _ En! MAS 7848L PRELIMINARY APPLICATIONS FM comparator The circuit also includes a seperate comparator with the @ RDS Receivers inverting input FCN and non-inverting input FCP. The out- @ MBS Pagers put of the comparator is available at pin FCO. — ae GENERAL DESCRIPTION Battery voltage and temperature indicators The device can be usedinmonitoring the battery volt- The IC contains all the necessary function blocks to age. The outputs BTH, BTM and BTL change their states demodulate and decode the incoming modulated 57 from 1 to 0 when the voltage at the UBAT input drops be- kHz subcarrier. On the output the binary data and bit syn- low the threshold’s (VDD + 0,10) / 2V, (VDD - 0.04) /2V chronous clock is available for further frame decoding. and (VDD - 0.17) / 2V correspondingly. The temperature The above mentioned signal processing is performed is monitored by an NTC resistor connected between the digitally. For MBS receivers the circuit also provides pins UTMP and VSS. When the voltage at UTMP drops some analog function blocks such as a FM-tuner volt- below (VDD - 0.04) / 2V the output TMP changes its state age generator, FM comparator, battery voltage and tem- from 1 to 0. perature indicators and a power savings function. The power-down circuitry and the 32,768 kHz — oscillator FUNCTIONAL DESCRIPTION semiato : The device is equipment with a power down feature to re- | duce power consumption in pager applications. When Manchester decoder the PWR input is high power is cut from all other blocks except for the 32,768 kHz oscillator. The circuit accepts an analog 57 kHz signal on its PSK input pin. The signal is amplified and converted to a digi- tal signal by an autozeroing comparator. This digital sig- nal is then fed to a 57 kHz PLL. The internally generated SL Ly synchronous 57 kHz clock is the used to demodulate the 7 Ea product modulated PSK input signal | The resultant baseband signal is the low pass filtered poe and fedto a 1187,5 Hz PLL. The internally generated syn- FOL Binary data chronous 1187,5 Hz clock is used to demodulate the Popo Eg tone phase modulated differential coded _ information. 1 ln ee Finally the binary information can be decoded. POU 1187.5 Hz clock Data and DCO are the end products of this process and MUU rer Uy corresponds to binary data and clock. A crystal of 3,648 Fob bb ere ' ' Mz is connected between X1 and X2. Una Differential rotten 14 4 coded data Tuner voltage generator - TN AA | A AL A |. Tonephase The generator contains a 9 bit D/A converter. The output PANT E A A modulated with voltage at UT is programmed by applying an appropriate oro. + ep 4 4 4 differential coded number of pulses on the FST input poe toro eorys ! data The AFC input allows automatic frequency control to take ERY RANA fan (INGEN NIN ; place, The AUD input is used to fine tune the output voit- Reneoenca sitar (¢ PSK-signal age. The DC level of the FM detector output in the tuner is normally used for this. P.O.Box 51, Kamreerintie 2, SF-02771 Espoo, Finland Tel. Int. + 358-0-80521, Fax +358-0-8053213, Telex 1000691, Teletex 244-1000691
i MICRONAS SbE D MM 6111560 0000195 952 MENCRN t 7 a EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEeee! SIGNAL DESCRIPTION i Pin Name 10/AD Functions 4 8 PSK VA Phase shift 57 kHz input signal I 12 FST VO Clock to turner voltage generator é if 5 POL >) Polarity of the S-curve POL = 1 raising voltage i POI = 0 falling voltage
9 AFC VD Automatic frequency control using AUD as fine tuning voltage
| in] AUD VA ADC voltage level from the tuner used to fine adjust the tuning j H 10 Ut O/A Tuning voltage to tuner i VDD 1 Positive power supply for digital i VDA Positive power supply for analog VSS | Negative power supply, OV for digital VSA Negative power supply, OV for analog
3 FCN VA Inverting input of FM comparator
2 FCP VA Non-inverting input of FM comparator
43 FCO O/A Output of FM comparator
21 UTMP VA DC voltage proportional to temperature (from an NTC resistor)
27 TMP. o/D When the voltage at UTMP drops below (VDD - 0.04) / 2V this pin changes its state from 1 to 0
20 UBAT VA Comparator input used for monitoring the battery voltage
31 BTH O/D Battery test high. BTH is high when the voltage at the UBAT input is over (VDD + 0.10) / 2V 30 BIM o/D Battery test medium. BTM is high when the voltage at the UBAT inputs is over (VDD ~ 0.04) / 2V 32 BIL o/D Battery test low. BTL is high when the voltage at the UBAT input is over (VDD - 0.17) / 2v
26 PWR VD Power down control
PWR = 0 normal function PWR = 1 reduced power consumption
24 STEP VD Actives the tuner voltage generator and sends an interrupt on IRQ to the
micro controller when STEP goes from 1 to 0 and PWR = 1
é > MICRONAS SbE D MM 6111560 0000156 459 MBNCRN 18 RUP /D Reset from micro controller. resets the 32,768 kHz counter and sets IRQ 25 IRQ o/0 Interrupt request to micro controller. Active low. Time delay from RUP low/high transition to IRQ high / low is approx 31,2 sec E t 14 Ls o/D Loud speaker alarm. freq = 2,048 kHz fT 3 13 ALC VD Alarm control. When ALC = 1 a 2,048 kHz square waww signal is q available at the LS output i 16 x3 1 X.-tal 32,768 kHz A 15 x4 Oo X-tal 32,768 kHz (type: 32,768 kHz CX-IV statek corp.) i 34 x1 1 X-tal 3,648 MHz
33 X2 fe) X-tal 3,648 MHz
a DCO o/D 1187,5 Hz clock from Manchester decoder
36 DATA o/D Binary data from Manchester decoder
4 CEXT VA External filter capacitor for the auto-zeroing comparator. 4,7 uF typically
19 Test o/D Test pad for 32,8 kHz oscillator
42 APSK o/D Sliced PSK signal
Pin numbering refers to 44 lead PLCC package 127, LPIN €) e| a IP 3 5 q 5 nol d 17.65 max
| . MCRN | MICRONAS 5SbE D MM 6121560 0000197 725 a a MAS 7848L IN POCKET PAGER MAS 7648. Low power microprocessor with power off feature 14) 3 rs ac ta rst [q2—_| m = mo" e ourper Pon : weur pont i EXT TMP e ATA | ss | i > Ly woo [2 j “ saresnz S| x2 H a ‘ d IH, Ro
3 VSA VDA vSO VOD voo vss
3 TZ 4 {—}
| iiS+—— i PLCC 4 PACKAGE MAS 7848L BLOCK DIAGRAM v coco = pS : Auo 3.9 MOHM . FCO o——. _ 440 KOHM: VOO/2 POL ——— a) > FoP _— FCN oO oOo
j ; MICRONAS SbE D MM 6111560 0000198 &bb1 MENCRN i ° \\ | ? ee eemmmmnnmmmeennmmemeneeameemeeemeeeen!
PACKAGE INFORMATION
115, 127, LPIN PLCC 1.15 x45" Ross - i Feslclclel-l-leiclelsising al d (Fh j ‘RBARRSERAaT a os x45: PARRA SooererperraTe | O.S TYPICAL [ | ' 2.65 TYPICAL 16.67 max___ ' 4.57 max 17.65max | f \\ ORDERING INFORMATION i Our product code: Product: Package: 7848PL44C MAS 7848L RDS MODEM / 44LD PLCC . MANCHESTER DECODER i Please, refer to our product code when ordering