MSP34X1G MICRONAS | Alldatasheet
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Edition Jan. 19, 2001 6251-511-2PD PRELIMINAR Y DATA SHEET MICR ONAS MICRONAS with Virtual Dolby Surround
Contents, continued Page Section Title PRELIMINARY DATA SHEET MSP 34x1G Micronas 3 19 3.2. Start-Up Sequence: Power-Up and I 2C-Controlling 19 3.3. MSP 34x1G Programming Interface 19 3.3.1. User Registers Overview 23 3.3.2. Description of User Registers 24 3.3.2.1. STANDARD SELECT Register 24 3.3.2.2. Refresh of STANDARD SELECT Register 24 3.3.2.3. STANDARD RESULT Register 26 3.3.2.4. Write Registers on I 2C Subaddress 10hex 28 3.3.2.5. Read Registers on I 2C Subaddress 11hex 29 3.3.2.6. Write Registers on I 2C Subaddress 12hex 44 3.3.2.7. Read Registers on I 2C Subaddress 13hex 45 3.4. Programming Tips 45 3.5. Examples of Minimum Initialization Codes 45 3.5.1. SCART1 Input to Loudspeaker in Stereo Sound 45 3.5.2. SCART1 Input to Loudspeaker in 3D-PANORAMA Sound 45 3.5.3. Noise Sequencer for 3D-PANORAMA Sound 46 3.5.4. B/G-FM (A2 or NICAM) 46 3.5.5. BTSC-Stereo 46 3.5.6. BTSC-SAP with SAP at Loudspeaker Channel 46 3.5.7. FM-Stereo Radio 46 3.5.8. Automatic Standard Detection 46 3.5.9. Software Flow for Interrupt driven STATUS Check 48 4. Specifications 48 4.1. Outline Dimensions 50 4.2. Pin Connections and Short Descriptions 53 4.3. Pin Descriptions 56 4.4. Pin Configurations 60 4.5. Pin Circuits 62 4.6. Electrical Characteristics 62 4.6.1. Absolute Maximum Ratings 63 4.6.2. Recommended Operating Conditions (T A = 0 to 70 °C) 63 4.6.2.1. General Recommended Operating Conditions 63 4.6.2.2. Analog Input and Output Recommendations 64 4.6.2.3. Recommendations for Analog Sound IF Input Signal 65 4.6.2.4. Crystal Recommendations 66 4.6.3. Characteristics 66 4.6.3.1. General Characteristics 67 4.6.3.2. Digital Inputs, Digital Outputs 68 4.6.3.3. Reset Input and Power-Up 69 4.6.3.4. I 2C-Bus Characteristics 70 4.6.3.5. I 2S-Bus Characteristics 72 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC 73 4.6.3.7. Sound IF Inputs 73 4.6.3.8. Power Supply Rejection 74 4.6.3.9. Analog Performance 77 4.6.3.10. Sound Standard Dependent Characteristics
MSP 34x1G PRELIMINARY DATA SHEET
4 Micronas
Contents, continued Page Section Title 81 5. Appendix A: Overview of TV-Sound Standards 81 5.1. NICAM 728 82 5.2. A2-Systems 83 5.3. BTSC-Sound System 83 5.4. Japanese FM Stereo System (EIA-J) 84 5.5. FM Satellite Sound 84 5.6. FM-Stereo Radio 85 6. Appendix B: Manual/Compatibility Mode 85 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode 86 6.2. DSP Write and Read Registers for Manual/Compatibility Mode 87 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers 87 6.3.1. Automatic Switching between NICAM and Analog Sound 87 6.3.1.1. Function in Automatic Sound Select Mode 87 6.3.1.2. Function in Manual Mode 89 6.3.2. A2 Threshold 89 6.3.3. Carrier-Mute Threshold 90 6.3.4. Register AD_CV 91 6.3.5. Register MODE_REG 93 6.3.6. FIR-Parameter, Registers FIR1 and FIR2 93 6.3.7. DCO-Registers 95 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers 95 6.4.1. NICAM Mode Control/Additional Data Bits Register 95 6.4.2. Additional Data Bits Register 95 6.4.3. CIB Bits Register 96 6.4.4. NICAM Error Rate Register 96 6.4.5. PLL_CAPS Readback Register 96 6.4.6. AGC_GAIN Readback Register 96 6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode 97 6.5. Manual/Compatibility Mode: Description of DSP Write Registers 97 6.5.1. Additional Channel Matrix Modes 97 6.5.2. Volume Modes of SCART1/2 Outputs 97 6.5.3. FM Fixed Deemphasis 97 6.5.4. FM Adaptive Deemphasis 98 6.5.5. NICAM Deemphasis 98 6.5.6. Identification Mode for A2 Stereo Systems 98 6.5.7. FM DC Notch 98 6.6. Manual/Compatibility Mode: Description of DSP Read Registers 98 6.6.1. Stereo Detection Register for A2 Stereo Systems 98 6.6.2. DC Level Register 99 6.7. Demodulator Source Channels in Manual Mode 99 6.7.1. Terrestric Sound Standards 99 6.7.2. SAT Sound Standards 101 6.8. Exclusions of Audio Baseband Features 101 6.9. Phase Relationship of Analog Outputs 101 6.10. Compatibility Restrictions to MSP 34xxD
Contents, continued Page Section Title PRELIMINARY DATA SHEET MSP 34x1G Micronas 5 102 7. Appendix D: MSP 34x1G Version History 103 8. Appendix E: Application Circuit 104 9. Data Sheet History License Notice: 1) "Dolby", “Virtual Dolby Surround” and the double-D symbol are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec- tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
MSP 34x1G PRELIMINARY DATA SHEET
6 Micronas
Multistandard Sound Processor Family with Virtual Dolby Surround Release Note: Revision bars indicate significant changes to the previous edition.The hardware and software description in this document is valid for the MSP 34x1G version B8 and following versions. 1. Introduction The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to pro- cessed analog AF-out, is performed on a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x1G. The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature. Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the Micronas virtualizer algorithm “3D-PANORAMA ” which has been approved by the Dolby 1) Laboratories for compliance with the "Virtual Dolby Surround" technol- ogy. In addition, the MSP 34x1G includes the “PAN- ORAMA ” algorithm. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo perfor- mance without any adjustments. All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x1G further simplifies con- trolling software. Standard selection requires a single I 2C transmission only. The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automat- ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I 2C interaction is necessary (Auto- matic Sound Selection). The ICs are produced in submicron CMOS technology. The MSP 34x1G is available in the following packages: PLCC68 (not intended for new designs), PSDIP64, PSDIP52, PQFP80, and PLQFP64. Fig. 1–1:Simplified functional block diagram of the MSP 34x1G Source Select Loud- SCART1 SCART2 SCART1 SCART2 SCART4 SCART3 MONO De- modulator Headphone Headphone I2S Sound Processing speaker Sound Processing DAC DAC ADC Loud- DAC DAC ADC Subwoofer SCART DSP Input Select Pre- processing SCART Output Select Prescale Prescale I2S1 I2S2 Sound IF1 Sound IF2 speaker
PRELIMINARY DATA SHEET MSP 34x1G Micronas 7 1.1. Features of the MSP 34x1G Family and Differences to MSP 34xxD 1.2. MSP 34x1G Version List Feature (New features not available for MSP 34xxD are shaded gray.) 3401 3411 3421 3441 3451 3461 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generatorX X X X X X PANORAMA virtualizer algorithm X X X X X X Standard Selection with single I2C transmission X X X X X X Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function X X X X X X Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS X X X X X X Two selectable sound IF (SIF) inputs X X X X X X Interrupt output programmable (indicating status change) X X X X X X Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness X X X X X X Loudspeaker channel with MDB (Micronas Dynamic Bass) X X X X X X AVC: Automatic Volume Correction X X X X X X Subwoofer output with programmable low-pass and complementary high-pass filter X X X X X X 5-band graphic equalizer for loudspeaker channel X X X X X X Spatial effect for loudspeaker channel; processing of all deemphasis filtering X X X X X X Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs X X X X X X Complete SCART in/out switching matrix X X X X X X Two I 2S inputs; one I2S o u t p u t XXXXXX All analog FM-Stereo A2 and satellite standards X X X All analog Mono sound carriers including AM-SECAM L X X X X X X Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM X X Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) X X X X ASTRA Digital Radio (ADR) together with DRP 3510A X X X X All NICAM standards XX Demodulation of the BTSC multiplex signal and the SAP channel X X X Alignment free digital DBX noise reduction for BTSC Stereo and SAP X X Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP X BTSC stereo separation (MSP 3421/41G also EIA-J) significantly better than spec. X X X SAP and stereo detection for BTSC system X X X Korean FM-Stereo A2 standard X X X X X Alignment-free Japanese standard EIA-J X X X Demodulation of the FM-Radio multiplex signal X X X Version Status Description MSP 3401G available FM Stereo (A2) Version MSP 3411G available NICAM and FM Stereo (A2) Version MSP 3421G available NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) MSP 3441G not confirmed NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) MSP 3451G available Global Version (all sound standards) MSP 3461G not confirmed Global Mono Version (all sound Standards)
MSP 34x1G PRELIMINARY DATA SHEET
8 Micronas
1.3. MSP 34x1G Versions and their Application Fields Table 1–1 provides an overview of TV sound standards that can be processed by the MSP 34x1G family. In addition, the MSP 34x1G is able to handle the FM- Radio standard. With the MSP 34x1G, a complete multimedia receiver covering all TV sound standards together with terrestrial/cable and satellite radio sound can be built; even ASTRA Digital Radio can be pro- cessed (with a DRP 3510A coprocessor). Fig. 1–2:Typical MSP 34x1G application Table 1–1:TV Stereo Sound Standards covered by the MSP 34x1G IC Family (details see Appendix A) MSP Version TV- System Position of Sound Carrier /MHz Sound Modulation Color System Broadcast e.g. in: 3401 3411 3451 B/G 5.5/5.7421875 FM-Stereo (A2) PAL Germany 5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain L 6.5/5.85 AM-Mono/NICAM SECAM-L France I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong
3401 D/K
6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep. 6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast 6.5/5.7421875 FM-Stereo (A2, D/K3) SECAM-East Poland 6.5/5.85 FM-Mono/NICAM (D/K, NICAM) PAL China, Hungary 3401 Satellite 6.5 7.02/7.2 7.38/7.56 etc. FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A PA L Europe Sat. ASTRA 3421, 3441 M/N 4.5/4.724212 FM-Stereo (A2) NTSC Korea
4.5 FM-FM (EIA-J) NTSC Japan
4.5 BTSC-Stereo + SAP NTSC, PAL USA, Argentina
FM-Radio 10.7 FM-Stereo Radio USA, Europe 3461 all Standards, but Mono demodulation only 33 34 39 MHz 4.5 9 MHz Loudspeaker Subwoofer Headphone SCART Outputs2 SCART2 SCART1 MSP 34x1G I2S2ADRI2S1 ADR Decoder DRP 3510A Dolby Pro Logic Processor DPL 351xA SCART1 SCART2 SCART3 SCART4 Mono SAW Filter Sound IF Mixer Vision Demo- dulator Tuner SCART Inputs Composite Video
PRELIMINARY DATA SHEET MSP 34x1G Micronas 9 2. Functional Description ANA_IN1+ AGC ANA_IN2+ ADR-Bus Interface MDB I2S_DA_IN2 I2S_DA_IN1 D A SCART DSP Input Select A D D A D A A D SCART Output Select Fig. 2–1:Signal flow block diagram of the MSP 34x1G (input and output names correspond to pin names) Source Select DACM_L DACM_R DACM_SUB DACA_L DACA_R VolumeBalance Balance Level Adjust Spatial Effects Comple- mentary Highpass Lowpass Σ Σ I2S_DA_OUT Beeper SCART1_L/R Bass/ Treble or Equalize Bass/ Treble AVC Loud- Channel Matrix speaker I2S Interface I2S Channel Matrix I2C Read Register Quasi-Peak Detector Volume I2S1 I2S Interface I2C Stereo or B Stereo or A FM/AMFM/AM Prescale Prescale NICAM Read Register Deemphasis: 50/75 µs, J17 DBX/MNR Panda1 Standard DEMODULATOR (incl. Carrier Mute) Decoded − NICAM − A2 − AM − BTSC − EIA-J − SAT − FM-Radio and Sound Detection SC1_IN_R SC1_IN_L SC3_IN_R SC2_IN_L SC2_IN_R SC3_IN_L MONO_IN SC4_IN_L SC4_IN_R SCART2_L/R SC1_OUT_L SC1_OUT_R SC2_OUT_L SC2_OUT_R SCART1 Standards: Deemphasis J17 Stereo or A/B Prescale Headphone Channel Matrix Quasi-Peak Channel Loud- Loudness ness Matrix Automatic Sound Select (08hex) (0Ahex) (07hex) (00hex) (29hex) (14hex) (13hex) (13hex) (02hex) (03hex) (04hex)( 0 5 hex)( 0 1 hex) (16hex) Standard Selection (0Ehex) (10hex) (0Bhex) Channel Matrix D A VolumeSCART2 Channel Matrix (0Chex) (41hex)( 4 0 hex) I2S2 I2S Interface Prescale (12hex) SCART Prescale (0Dhex) 0.5 (2Dhex) (2Dhex)( 2 C hex) (30hex) (19hex) (09hex) (31/32hex)( 3 3 hex) (1Ahex) Volume (06hex) Noise Generator Virtualizer
MSP 34x1G PRELIMINARY DATA SHEET
10 Micronas
2.1. Architecture of the MSP 34x1G Family Fig. 2–1 on page 9 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3451G. Other members of the MSP 34x1G family do not have the complete set of features: The demodu- lator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3411G and MSP 3451G. 2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN− offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x1G. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The high- pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ see Section 8. “Appendix E: Application Circuit” on page 103 are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their out- puts. In this case, further filtering is recommended. 2.2.2. Demodulator: Standards and Features The MSP 34x1G is able to demodulate all TV-sound standards worldwide including the digital NICAM sys- tem. Depending on the MSP 34x1G version, the fol- lowing demodulation modes can be performed: A2 Systems: Detection and demodulation of two sep- arate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the ana- log (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum devi- ation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detec- tion and evaluation of the pilot carrier, AM demodula- tion of the (L−R)-carrier and detection of the SAP sub- carrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Process- ing of DBX noise reduction or Micronas Noise Reduc- tion (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L−R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodula- tion of the (L−R)-carrier. The demodulator blocks of all MSP 34x1G versions have identical user interfaces. Even completely differ- ent systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x1G demodulator blocks are Standard Selection: The controlling of the demodula- tor is minimized: All parameters, such as tuning fre- quencies or filter bandwidth, are adjusted automati- cally by transmitting one single value to the STANDARD SELECT register. For all standards, spe- cific MSP standard codes are defined. Automatic Standard Detection: If the TV sound stan- dard is unknown, the MSP 34x1G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x1G offers a configurable carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STAN- DARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corre- sponding demodulator output is muted. This is indi- cated in the STATUS register.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 11 2.2.3. Preprocessing of Demodulator Signals The NICAM signals must be processed by a deempha- sis filter and adjusted in level. The analog demodu- lated signals must be processed by a deemphasis fil- ter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound stan- dard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection. 2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identifi- cation information in the STATUS register. No I interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono-compatible standards (stan- dards that have the same FM-Mono carrier) automati- cally and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these stan- dards. The same action is performed for the stan- dards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x1G auto- matically falls back from digital NICAM sound to ana- log FM or AM mono. Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on. To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig. 2–2). By choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loud- speaker, headphone, etc.). This is done by means of the Source Select registers. The following source channels of demodulated sound are defined: – “FM/AM ” channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). – “Stereo or A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains both languages A (left) and B (right). – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains language A (on left and right). – “Stereo or B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains language B (on left and right). Fig. 2–2 and Table 2–2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of the MPX carrier, or the SAP signal. Fig. 2–2:Source channel assignment of demodulated signals in Automatic Sound Select Mode 2.2.5. Manual Mode Fig. 2–3 shows the source channel assignment of demodulated signals in case of manual mode. If man- ual mode is required, more information can be found in Section 6.7. “Demodulator Source Channels in Manual Mode ” on page 99. Fig. 2–3:Source channel assignment of demodulated signals in Manual Mode 2.3. Preprocessing for SCART and I 2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale regis- ters. Source Select FM/AM Stereo or A/B Stereo or A Stereo or B primary FM/AM Prescale NICAM Prescale Automatic Sound Select channel secondary channel NICAM A NICAM B LS Ch. Matrix Output-Ch. matrices must be set once to stereo. Source Select FM/AM (Stereo or A/B) primary FM/AM Prescale NICAM Prescale FM-Matrix channel secondary channel NICAM A NICAM B LS Ch. Matrix Output-Ch. matrices must be set according to the standard. NICAM
MSP 34x1G PRELIMINARY DATA SHEET
12 Micronas
Table 2–1:Performed actions of the Automatic Sound Selection Selected TV Sound Standard Performed Actions B/G-FM, D/K-FM, M-Korea, and M-Japan Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. B/G-NICAM, L-NICAM, I-NICAM, and D/K-NICAM Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM, and D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non- audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-Mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. BTSC-STEREO, FM Radio Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2–2. Detection of the SAP carrier. BTSC-SAP In the absence of SAP , the MSP switches to BTSC-Stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2–2). Table 2–2:Sound modes for the demodulator source channels with Automatic Sound Select Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) M-Korea B/G-FM D/K-FM M-Japan 03, 08 04, 05, 07, 0B1) MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo BILINGUAL: Languages A and B Left = A Right = B Left = A Right = B AB B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) 08, 032) 0B, 04 2), 052) 0C, 0D NICAM not available or error rate too high analog Mono analog Mono analog Mono analog Mono MONO analog Mono NICAM Mono NICAM Mono NICAM Mono STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo BILINGUAL: Languages A and B analog Mono Left = NICAM A Right = NICAM B NICAM A NICAM B BTSC 20, 21 MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo
20 MONO+SAP Mono Mono Mono Mono
STEREO+SAP Stereo Stereo Stereo Stereo
21 MONO+SAP Left = Mono
Right = SAP Left = Mono Right = SAP Mono SAP STEREO+SAP Left = Mono Right = SAP Left = Mono Right = SAP Mono SAP FM Radio 40 MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo 1) The Automatic Sound Select process will automatically switch to the mono compatible analog standard. 2) The Automatic Sound Select process will automatically switch to the mono compatible digital standard. 3) The MSP Standard Codes are defined in Table 3–7 on page 23.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 13 2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source chan- nels, SCART, or I2S input) to the desired output chan- nels (loudspeaker, headphone, etc.). All input and out- put signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. 2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 33). For input signals ranging from −24 dBr to 0 dBr, the AVC maintains a fixed output level of −18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is – SCART input/output 0 dBr = 2.0 V rms – Loudspeaker output 0 dBr = 1.4 Vrms Fig. 2–4:Simplified AVC characteristics 2.5.2. Loudspeaker and Headphone Outputs The following baseband features are implemented in the loudspeaker and headphone output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to the loudspeaker and headphone channel. The loudspeaker channel addi- tionally performs: equalizer (not simultaneously with bass/treble), spatial effects, and a subwoofer cross- over filter. 2.5.3. Subwoofer Output The subwoofer signal is created by combining the left and right channels directly behind the loudness block using the formula (L+R)/2. Due to the division by 2, the D/A converter will not be overloaded, even with full scale input signals. The subwoofer signal is filtered by a third-order low-pass with programmable corner fre- quency followed by a level adjustment. At the loud- speaker channels, a complementary high-pass filter can be switched on. Subwoofer and loudspeaker out- put use the same volume (Loudspeaker Volume Reg- ister). 2.5.4. Quasi-Peak Detector The quasi-peak readout register can be used to read out the quasi-peak level of any input source. The fea- ture is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms input level −18 −24 output level 0 [dBr] [dBr]
MSP 34x1G PRELIMINARY DATA SHEET
14 Micronas
2.5.5. Micronas Dynamic Bass (MDB) The M icronas D ynamic B ass system (MDB) extends the frequency range of loudspeakers or headphones. After the adaption of MDB to the loudspeakers and the cabinet, further customizing of MDB allows individual fine tuning of the sound. The MDB is placed in the subwoofer path. For applica- tions without a subwoofer, the enhanced bass signal can be added back onto the Left/Right channels (see Fig. 2–1 on page 9). Micronas Dynamic Bass com- bines two effects: dynamic amplification and adding harmonics. 2.5.5.1. Dynamic Amplification Low frequency signals can be boosted while the output signal amplitude is measured. If the amplitude comes close to a definable limit, the gain is reduced automati- cally in dynamic Volume mode. Therefore, the system adapts to the signal amplitude which is really present at the output of the MSP device. Clipping effects are avoided. Fig. 2–5:Dynamic amplification 2.5.5.2. Adding Harmonics MDB exploits the psychoacoustic phenomenon of the ‘missing fundamental’. Adding harmonics of the fre- quency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental. In other words: The listener has the impression that a loudspeaker system seems to repro- duce frequencies althoug physically not possible. Fig. 2–6:Adding harmonics 2.5.5.3. MDB Parameters Several parameters allow tuning the characteristics of MDB according to the TV loudspeaker, the cabinet, and personal preferences (see Table 3–11). For more detailed information on how to set up MDB, please refer to the corresponding application note on the Micronas homepage. 2.6. Virtual Surround System Application Tips 2.6.1. Sweet Spot Good results are only obtained in a rather close area along the middle axis between the two loudspeakers: the sweet spot. Moving away from this position degrades the effect. 2.6.2. Clipping For the test at Dolby Labs, it is very important to have no clipping effects even with worst case signals. That is, 2 Vrms input signal may not clip. The SCART Input Prescale register has to be set to values of 19 hex (25dec) or lower (see SCART Input Prescale on page 30). Test signals: sine sweep with 2 VRMS ; L only, R only, L&R equal phase, L&R anti phase. Listening tests: Dolby Trailers (train trailer, city trailer, canyon trailer...) Frequency MDB_LIMIT MDB_HP MDB_LP Signal Level Amplitude SUBW_FREQ (db) Frequency MDB_HP Amplitude (db)
PRELIMINARY DATA SHEET MSP 34x1G Micronas 15 2.6.3. Loudspeaker Requirements The loudspeakers used and their positioning inside the TV set will greatly influence the performance of the vir- tualizer. The algorithm works with the direct sound path. Reflected sound waves reduce the effect. So it’s most important to have as much direct sound as possi- ble, compared to indirect sound. To obtain the approval for a TV set, Dolby Laboratories require mounting the loudspeakers in front of the set. Loudspeakers radiating to the side of the TV set will not produce convincing effects. Good directionality of the loudspeakers towards the listener is optimal. The virtualizer was specially developed for implemen- tation in TV sets. Even for rather small stereo TV's, sufficient sound effects can be obtained. For small sets, the loudspeaker placement should be to the side of the CRT; for large screen sets (or 16:9 sets), mount- ing the loudspeakers below the CRT is acceptable (large separation is preferred, low frequency speakers should be outmost to avoid cancellation effects). Using external loudspeakers with a large stereo base will not create optimal effects. The loudspeakers should be able to reproduce a wide frequency range. The most important frequency range starts from 160 Hz and ranges up to 5 kHz. Great care has to be taken with systems that use one common subwoofer: A single loudspeaker cannot reproduce virtual sound locations. The crossover fre- quency must be lower than 120 Hz. 2.6.4. Cabinet Requirements During listening tests at Dolby Laboratories, no reso- nances in the cabinet should occur. Good material to check for resonances are the Dolby Trailers or other dynamic sound tracks. 2.7. SCART Signal Routing 2.7.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 41). 2.7.2. Stand-by Mode If the MSP 34x1G is switched off by first pulling STANDBYQ low and then (after >1µs delay) switching off DVSUP and AVSUP , but keeping AHVSUP (‘Stand-by’-mode ), the SCART switches maintain their position and function. This allows the copying from SCART -input to SCART -output in the TV set’s stand-by mode. In case of power on or starting from stand-by (switch- ing on the DVSUP and AVSUP , RESETQ going high 2 ms later), all internal registers except the ACB regis- ter (page 41) are reset to the default configuration (see Table 3–5 on page 20). The reset position of the ACB register becomes active after the first I 2C transmission into the Baseband Processing part. By transmitting the ACB register first, the reset state can be redefined.
MSP 34x1G PRELIMINARY DATA SHEET
16 Micronas
2.8. I2S Bus Interface The MSP 34x1G has a synchronous master/slave input/output interface running on 32 kHz. The interface accepts two formats: 1. I2S_WS changes at the word boundary 2. I2S_WS changes one I2S-clock period before the word boundaries. All I2S options are set by means of the MODUS and the I2S_CONFIGURATION registers. The I2S bus interface consists of five pins: – I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 : I2S serial data input: 16, 18....32 bits per sample – I 2S_ DA_O U T: I2S serial data output: 16, 18...32 bits per sample – I2S_CL: I2S serial clock – I2S_WS: I2S word strobe signal defines the left and right sample If the MSP 34x1G serves as the master on the I2S interface, the clock and word strobe lines are driven by the IC. In this mode, only 16 or 32 bits per sample can be selected. In slave mode, these lines are input to the IC and the MSP clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possi- ble in slave mode. An I 2S timing diagram is shown in Fig. 4–28 on page 71. 2.9. ADR Bus Interface For the ASTRA Digital Radio System (ADR), the MSP 3401G, MSP 3411G, and MSP 3451G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are trans- ferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the fol- lowing lines of MSP 34x1G should be provided on a feature connector: – AUD_CL_OUT – I2S_DA_IN1 or I2S_DA_IN2 – I2S_DA_OUT – I2S_WS – I2S_CL – ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet. 2.10. Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I 2C-bus by means of the ACB register (see page 41). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high imped- ance by means of the MODUS register (see page 26). In this mode, the pins can be used as input. The cur- rent state can be read out of the STATUS register (see page 28). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes poll- ing unnecessary, I 2C bus interactions are reduced to a minimum (see STATUS register on page 28 and MODUS register on page 26). 2.11. Clock PLL Oscillator and Crystal Specifications The MSP 34x1G derives all internal system clocks from the 18.432-MHz oscillator. In NICAM or in I2S- Slave mode, the clock is phase-locked to the corre- sponding source. Therefore, it is not possible to use NICAM and I 2S-Slave mode at the same time. For proper performance, the MSP clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (NICAM, I 2S-Slave), crystals with tighter tolerance are required.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 17 3. Control Interface 3.1. I2C Bus Interface The MSP 34x1G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 34x1G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x1G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3–1). Writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.3. for the I 2C bus protocol and to Section 3.4. “Programming Tips” on page 45 for pro- posals of MSP 34x1G I2C telegrams. See Table 3–2 for a list of available subaddresses. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CON- TROL register by the controller via I 2C bus. Due to the architecture of the MSP 34x1G, the IC can- not react immediately to an I2C request. The typical response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line I2C_CL low to force the transmitter into a wait state. The I 2C Bus Master must read back the clock line to detect when the MSP is ready to receive the next I2C transmission. The positions within a transmission where this may happen are indicated by ’Wait’ in Section 3.1.3. The maximum wait period of the MSP during normal opera- tion mode is less than 1 ms. 3.1.1. Internal Hardware Error Handling In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines. Indication and solving the error status: To indicate the error status, the remaining acknowl- edge bits of the actual I 2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I 2C bus by transmitting the RESET condition to CONTROL. Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4–27 on page 69. Table 3–1:I2C Bus Device Addresses ADR_SEL Low (connected to DVSS) High (connected to DVSUP) Left Open Mode Write Read Write Read Write Read MSP device address 80 hex 81hex 84hex 85hex 88hex 89hex Table 3–2:I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Read/Write Write: Software reset of MSP (see Table 3 –3) Read: Hardware error status of MSP WR_DEM 0001 0000 10 Write write address demodulator RD_DEM 0001 0001 11 Write read address demodulator WR_DSP 0001 0010 12 Write write address DSP RD_DSP 0001 0011 13 Write read address DSP
MSP 34x1G PRELIMINARY DATA SHEET
18 Micronas
3.1.2. Description of CONTROL Register 3.1.3. Protocol Description Write to DSP or Demodulator Read from DSP or Demodulator Write to Control Register Read from Control Register Note:S = I 2C-Bus Start Condition from master P = I 2C-Bus Stop Condition from master ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP , light gray) or master (= controller, dark gray) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MSP indicating internal error state Wait = I 2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms Table 3–3:CONTROL as a Write Register Name Subaddress Bit[15] (MSB) Bits[14:0] CONTROL 00 hex 1 : RESET 0 : normal Table 3–4:CONTROL as a Read Register Name Subaddress Bit[15] (MSB) Bit[14] Bits[13:0] CONTROL 00 hex RESET status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Internal hardware status: 0 : no error occured 1 : internal error occured not of interest Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset. Sw r i t e device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK data-byte high ACK data-byte low ACK P Sw r i t e device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S read device address Wait ACK data-byte- high ACK data-byte low NAK P Sw r i t e device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P Sw r i t e device address Wait ACK 00hex ACK S read device address Wait ACK data-byte- high ACK data-byte low NAK P
PRELIMINARY DATA SHEET MSP 34x1G Micronas 19 Fig. 3–1:I2C bus protocol (MSB first; data must be stable while clock is high) 3.1.4. Proposals for General MSP 34x1G I2C Telegrams 3.1.4.1. Symbols dawwrite device address (80hex, 84hex or 88hex) darread device address (81hex, 85hex or 89hex) < Start Condition > Stop Condition aa Address Byte dd Data Byte 3.1.4.2. Write Telegrams <daw 00 d0 00>write to CONTROL register <daw 10 aa aa dd dd>write data into demodulator <daw 12 aa aa dd dd>write data into DSP 3.1.4.3. Read Telegrams <daw 00 <dar dd dd>read data from CONTROL register <daw 11 aa aa <dar dd dd>read data from demodulator <daw 13 aa aa <dar dd dd>read data from DSP 3.1.4.4. Examples <80 00 80 00>RESET MSP statically <80 00 00 00>Clear RESET <80 10 00 20 00 03>Set demodulator to stand. 03hex <80 11 02 00 <81 dd dd>Read STATUS <80 12 00 08 01 20>Set loudspeaker channel source to NICAM and Matrix to STEREO More examples of typical application protocols are listed in Section 3.4. “Programming Tips” on page 45. 3.2. Start-Up Sequence: Power-Up and I2C-Controlling After POWER-ON or RESET (see Fig. 4–26), the IC is in an inactive state. All registers are in the Reset posi- tion (see Table 3–5 and Table 3–6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary. 3.3. MSP 34x1G Programming Interface 3.3.1. User Registers Overview The MSP 34x1G is controlled by means of user regis- ters. The complete list of all user registers is given in Table 3–5 and Table 3–6. The registers are partitioned into the Demodulator section (subaddress 10 hex for writing, 11hex for reading) and the Baseband Process- ing sections (subaddress 12hex for writing, 13hex for reading). Write and read registers are 16 bit wide, whereby the MSB is denoted bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write registers, except the demodulator write registers are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be accessed. For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility Mode is available. More read and write registers together with a detailed description can be found in “Appendix B: Manual/Com- patibility Mode” on page 85. S P I2C_DA I2C_CL
MSP 34x1G PRELIMINARY DATA SHEET
20 Micronas
Table 3–5:List of MSP 34x1G Write Registers Write Register Address (hex) Bits Description and Adjustable Range Reset See Page I2C Subaddress = 10hex ; Registers are not readable STANDARD SELECT 00 20 [15:0] Initial Programming of the Demodulator 00 00 24 MODUS 00 30 [15:0] Demodulator, Automatic and I 2S options 00 00 26 I2S CONFIGURATION 00 40 [15:0] Configuration of I 2S options 00 00 27 I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex Volume loudspeaker channel 00 00 [15:8] [ +12 dB ... −114 dB, MUTE] MUTE 32 Volume / Mode loudspeaker channel [7:0] 1/8 dB Steps, Reduce Volume / Tone Control / Compromise / Dynamic hex 100%/100% 33 Balance mode loudspeaker [7:0] [Linear / logarithmic mode] linear mode Bass loudspeaker channel 00 02 [15:8] [ +20 dB ... −12 dB] 0 dB 34 Treble loudspeaker channel 00 03 [15:8] [ +15 dB ... −12 dB] 0 dB 35 Loudness loudspeaker channel 00 04 [15:8] [0 dB ... +17 dB] 0 dB 36 Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL Spatial effect mode/customize [7:0] [SBE, SBE +PSE] SBE +PSE Volume headphone channel 00 06 [15:8] [ +12 dB ... −114 dB, MUTE] MUTE 32 Volume / Mode headphone channel [7:0] 1/8 dB Steps, Reduce Volume / Tone Control 00 hex Volume SCART1 output channel 00 07 [15:8] [ +12 dB ... −114 dB, MUTE] MUTE 40 Loudspeaker source select 00 08 [15:8] [FM/AM, NICAM, SCART, I 2S1, I2S2] FM/AM 31 Loudspeaker channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 Headphone source select 00 09 [15:8] [FM/AM, NICAM, SCART, I 2S1, I2S2] FM/AM 31 Headphone channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 SCART1 source select 00 0A [15:8] [FM/AM, NICAM, SCART, I 2S1, I2S2] FM/AM 31 SCART1 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 I 2S source select 00 0B [15:8] [FM/AM, NICAM, SCART, I 2S1, I2S2] FM/AM 31 I2S channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 Quasi-peak detector source select 00 0C [15:8] [FM/AM, NICAM, SCART, I 2S1, I2S2] FM/AM 31 Quasi-peak detector matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 Prescale SCART input 00 0D [15:8] [00 hex ... 7Fhex]0 0 hex 30 Prescale FM/AM 00 0E [15:8] [00 hex ... 7Fhex]0 0 hex 29 FM matrix [7:0] [NO_MAT , GSTEREO, KSTEREO] NO_MAT 30 Prescale NICAM 00 10 [15:8] [00 hex ... 7Fhex] (MSP 3411G, MSP 3451G only) 00 hex 30 Prescale I2S2 00 12 [15:8] [00 hex ... 7Fhex]1 0 hex 30 ACB : SCART Switches a. D_CTR_I/O 00 13 [15:0] Bits [15..0] 00 hex 41 Prescale I2S1 00 16 [15:8] [00 hex ... 7Fhex]1 0 hex 30
PRELIMINARY DATA SHEET MSP 34x1G Micronas 21 Mode tone control 00 20 [15:8] [BASS/TREBLE, EQUALIZER] BASS/TREB 34 Equalizer loudspeaker ch. band 1 00 21 [15:8] [ +12 dB ... −12 dB] 0 dB 35 Equalizer loudspeaker ch. band 2 00 22 [15:8] [ +12 dB ... −12 dB] 0 dB 35 Equalizer loudspeaker ch. band 3 00 23 [15:8] [ +12 dB ... −12 dB] 0 dB 35 Equalizer loudspeaker ch. band 4 00 24 [15:8] [ +12 dB ... −12 dB] 0 dB 35 Equalizer loudspeaker ch. band 5 00 25 [15:8] [ +12 dB ... −12 dB] 0 dB 35 Automatic Volume Correction 00 29 [15:8] [off, on, decay time] off 33 Subwoofer level adjust 00 2C [15:8] [+12 dB ... −30 dB, mute] 0 dB 38 Subwoofer corner frequency 00 2D [15:8] [50 Hz ... 400 Hz] 00 hex 38 Subwoofer complementary high-pass [7:0] [off, on, MDB to Main] off 38 100%/100% 33 Balance mode headphone [7:0] [Linear mode / logarithmic mode] linear mode Bass headphone channel 00 31 [15:8] [ +20 dB ... −12 dB] 0 dB 34 Treble headphone channel 00 32 [15:8] [ +15 dB ... −12 dB] 0 dB 35 Loudness headphone channel 00 33 [15:8] [0 dB ... +17 dB] 0 dB 36 Loudness filter characteristic [7:0] [NORMAL, SUPER_BASS] NORMAL Volume SCART2 output channel 00 40 [15:8] [ +12 dB ... −114 dB, MUTE] 00 hex 40 SCART2 source select 00 41 [15:8] [FM, NICAM, SCART, I 2S1, I2S2] FM 31 SCART2 channel matrix [7:0] [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA 31 Virtual Surround OFF/ON switch 00 48 [15:8] [OFF/ON] 00 hex 42 Virtual Surround spatial effect strength 00 49 [15:8] [0% - 100%] 00 hex 42 Virtual Surround 3D effect strength 00 4A [15:8] [0% - 100%] 00 hex 42 Virtual Surround mode 00 4B [15:0] [PANORAMA/3D-PANORAMA] 00 hex 42 Noise generator 00 4D [15:0] [OFF/ON, Noise_L, Noise_C, Noise_R, Noise_S] 00 hex 43 MDB Effect Strength 00 68 [15:8] [0 dB ... 127 dB, off] off 38 MDB Amplitude Limit 00 69 [15:8] [0 dBFS... -32 dBFS] 0 dBFS 38 MDB Harmonic Content 00 6A [15:8] [0% ... 100%] 0% 39 MDB Low Pass Corner Frequency 00 6B [15:8] [50 Hz ... 300 Hz] 0 Hz 39 MDB High Pass Corner Frequency 00 6C [15:8] [20 Hz ... 300 Hz] 0 Hz 39 Table 3–5:List of MSP 34x1G Write Registers, continued Write Register Address (hex) Bits Description and Adjustable Range Reset See Page
MSP 34x1G PRELIMINARY DATA SHEET
22 Micronas
Table 3–6:List of MSP 34x1G Read Registers Read Register Address (hex) Bits Description and Adjustable Range See Page I2C Subaddress = 11hex ; Registers are not writable STANDARD RESULT 00 7E [15:0] Result of Automatic Standard Detection (see Table 3 –8) 28 STATUS 02 00 [15:0] Monitoring of internal settings e.g. Stereo, Mono, Mute etc. . 28 I2C Subaddress = 13hex ; Registers are not writable Quasi peak readout left 00 19 [15:0] [00 hex ... 7FFFhex] 16 bit two’s complement 44 Quasi peak readout right 00 1A [15:0] [00 hex ... 7FFFhex] 16 bit two’s complement 44 MSP hardware version code 00 1E [15:8] [00 hex ... FFhex]4 4 MSP major revision code [7:0] [00 hex ... FFhex]4 4 MSP product code 00 1F [15:8] [00 hex ... FFhex]4 4 MSP ROM version code [7:0] [00 hex ... FFhex]4 4
PRELIMINARY DATA SHEET MSP 34x1G Micronas 23 3.3.2. Description of User Registers Table 3–7:Standard Codes for STANDARD SELECT register MSP Standard Code (Data in hex) TV Sound Standard Sound Carrier Frequencies in MHz MSP 34x1G Version Automatic Standard Detection 00 01 Starts Automatic Standard Detection and sets detected standard all Standard Selection 00 02 M-Dual FM-Stereo 4.5/4.724212 3401, -11, -21, -41, -51 00 03 B/G -Dual FM-Stereo 1) 5.5/5.7421875 3401, -11, -51 00 04 D/K1-Dual FM-Stereo 2) 6.5/6.2578125 00 05 D/K2-Dual FM-Stereo 2) 6.5/6.7421875 00 06 D/K -FM-Mono with HDEV3 3), not detectable by Automatic Standard Detection, HDEV3 3) SAT -Mono (i.e. Eutelsat, s. Table 6–18) 6.5 00 07 D/K3-Dual FM-Stereo 6.5/5.7421875 00 08 B/G -NICAM-FM 1) 5.5/5.85 3411, -51 00 09 L -NICAM-AM 6.5/5.85 00 0A I -NICAM-FM 6.0/6.552 00 0B D/K -NICAM-FM 2) 6.5/5.85 00 0C D/K -NICAM-FM with HDEV2 4), not detectable by Automatic Standard Detection, for China 6.5/5.85 00 0D D/K -NICAM-FM with HDEV3 3), not detectable by Automatic Standard Detection, for China 6.5/5.85 00 20 BTSC-Stereo 4.5 3421, -41, -51 00 21 BTSC-Mono + SAP 00 30 M-EIA-J Japan Stereo 4.5 3421, -41, -51 00 40 FM-Stereo Radio with 75 µs Deemphasis 10.7 3421, -41, -51 00 50 SAT -Mono (s. Table 6 –18) 6.5 3401, -11, -51 00 51 SAT -Stereo (s. Table 6 –18) 7.02/7.20 00 60 SAT ADR (Astra Digital Radio) 6.12 1) In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent. 2) In case of Automatic Sound Select, the D/K-codes 4hex, 5hex, 7hexand Bhex are equivalent. 3) HDEV3: Max. FM deviation must not exceed 540 kHz 4) HDEV2: Max. FM deviation must not exceed 360 kHz
MSP 34x1G PRELIMINARY DATA SHEET
24 Micronas
3.3.2.1. STANDARD SELECT Register The TV sound standard of the MSP 34x1G demodula- tor is determined by the STANDARD SELECT register. There are two ways to use the STANDARD SELECT register: – Setting up the demodulator for a TV sound standard by sending the corresponding standard code with a single I 2C bus transmission. – Starting the Automatic Standard Detection for ter- restrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and setup of the actual TV sound standard is performed. The detected standard can be read out of the STANDARD RESULT register by the con- trol processor. This feature is recommended for the primary setup of a TV set. Outputs should be muted during Automatic Standard Detection. The Standard Codes are listed in Table 3–7. Selecting a TV sound standard via the STANDARD SELECT register initializes the demodulator. This includes: AGC-settings and carrier mute, tuning fre- quencies, FIR-filter settings, demodulation mode (FM, AM, NICAM), deemphasis and identification mode. TV stereo sound standards that are unavailable for a specific MSP version are processed in analog mono sound of the standard. In that case, stereo or bilingual processing will not be possible. For a complete setup of the TV sound processing from analog IF input to the source selection, the transmis- sions as shown in Section 3.5. are necessary. For reasons of software compatibility to the MSP 34xxD, a Manual/Compatibility mode is available. A detailed description of this mode can be found on page 85. 3.3.2.2. Refresh of STANDARD SELECT Register A general refresh of the STANDARD SELECT register is not allowed. However, the following method enables watching the MSP 34x1G “alive” status and detection of accidental resets (only versions B6 and later): – After Power-on, bit[15] of CONTROL will be set; it must be read once to enable the reset-detection feature. – Reading of the CONTROL register and checking the reset indicator bit[15] . – If bit[15] is “0”, any refresh of the STANDARD SELECT register is not allowed. – If bit[15] is “1”, indicating a reset, a refresh of the STANDARD SELECT register and all other MSPG registers is required. 3.3.2.3. STANDARD RESULT Register If Automatic Standard Detection is selected in the STANDARD SELECT register, status and result of the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3–8. In cases where no sound standard has been detected (no standard present, too much noise, strong interfer- ers, etc.) the STANDARD RESULT register contains 00 00 hex. In that case, the controller has to start further actions (for example set the standard according to a preference list or by manual input). As long as the STANDARD RESULT register contains a value greater than 07 FF hex, the Automatic Standard Detection is still active. During this period, the MODUS and STANDARD SELECT register must not be written. The STATUS register will be updated when the Auto- matic Standard Detection has finished. If a present sound standard is unavailable for a spe- cific MSP-version, it detects and switches to the ana- log mono sound of this standard. Example: The MSPs 3421G and 3441G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FM- Mono sound.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 25 Table 3–8:Results of the Automatic Standard Detection Broadcasted Sound Standard STANDARD RESULT Register Read 007E hex Automatic Standard Detection could not find a sound standard 0000 hex B/G-FM 0003 hex B/G-NICAM 0008 hex I0 0 0 A hex FM-Radio 0040 hex M-Korea M-Japan M-BTSC 0002hex (if MODUS[14,13]=00) 0020hex (if MODUS[14,13]=01) 0030hex (if MODUS[14,13]=10) L-AM D/K1 D/K2 D/K3 0009hex (if MODUS[12]=0) 0004hex (if MODUS[12]=1) L-NICAM D/K-NICAM 0009hex (if MODUS[12]=0) 000Bhex (if MODUS[12]=1) Automatic Standard Detection still active >07FF hex
MSP 34x1G PRELIMINARY DATA SHEET
26 Micronas
3.3.2.4. Write Registers on I2C Subaddress 10hex Table 3–9:Write Registers on I2C Subaddress 10hex Register Address Function Name 00 20hex STANDARD SELECTION Register Defines TV Sound or FM-Radio Standard bit[15:0] 00 01hex start Automatic Standard Detection 00 02hex Standard Codes (see Table 3–7)... 00 60hex STANDARD_SEL 00 30hex MODUS Register Preference in Automatic Standard Detection: bit[15] 0 undefined, must be 0 bit[14:13] detected 4.5 MHz carrier is interpreted as: 0 standard M (Korea) 1 standard M (BTSC) 2 standard M (Japan) 3 chroma carrier (M/N standards are ignored) bit[12] detected 6.5 MHz carrier is interpreted as: 0 standard L (SECAM) 1 standard D/K1, D/K2, D/K3, or D/K NICAM General MSP 34x1G Options bit[11:9] 0 undefined, must be 0 bit[8] 0/1 ANA_IN1+/ANA_IN2+; select analog sound IF input pin bit[7] 0/1 active/tristate state of audio clock output pin AUD_CL_OUT bit[6] I 2S word strobe alignment
0 WS changes at data word boundary
1 WS changes one clock cycle in advance
bit[5] 0/1 master/slave mode of I 2S interface (must be set to 0 (= Master) in case of NICAM mode) bit[4] 0/1 active/tristate state of I2S output pins bit[3] state of digital output pins D_CTR_I/O_0 and _1 0 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register. see also: MODUS[1]) 1 tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) bit[2] 0 undefined, must be 0 bit[1] 0/1 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[3] = 0 (active) bit[0] 0/1 off/on: Automatic Sound Select MODUS 1) Valid at the next start of Automatic Standard Detection.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 27 00 40hex I2S CONFIGURATION Register bit[15:1] 0 not used, must be set to “0” bit[0] I2S_CL frequency and I 2S data sample length for master mode 0 2 x 16 bit (1.024 MHz) 1 2 x 32 bit (2.048 MHz) I2S_CONFIG Table 3–9:Write Registers on I 2C Subaddress 10hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
28 Micronas
3.3.2.5. Read Registers on I2C Subaddress 11hex Table 3–10:Read Registers on I2C Subaddress 11hex Register Address Function Name 00 7Ehex STANDARD RESULT Register Readback of the detected TV Sound or FM-Radio Standard bit[15:0] 00 00hex Automatic Standard Detection could not find a sound standard 00 02hex MSP Standard Codes (see Table 3–8) ... 00 40hex >07 FFhex Automatic Standard Detection still active STANDARD_RES 02 00hex STATUS Register Contains all user relevant internal information about the status of the MSP bit[15:10] undefined bit[8] 0/1 “1” indicates bilingual sound mode or SAP present (internally evaluated from received analog or digital iden- tification signals) bit[7] 0/1 “1” indicates independent mono sound (only for NICAM) bit[6] 0/1 mono/stereo indication (internally evaluated from received analog or digital iden- tification signals) bit[5,9] 00 analog sound standard (FM or AM) active 01 this pattern will not occur 10 digital sound (NICAM) available 11 bad reception condition of digital sound (NICAM) due to: a. high error rate b. unimplemented sound code c. data transmission only bit[4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1 bit[3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0 bit[2] 0 detected secondary carrier (2nd A2 or SAP sub-carrier) 1 no secondary carrier detected bit[1] 0 detected primary carrier (Mono or MPX carrier) 1 no primary carrier detected bit[0] undefined If STATUS change indication is activated by means of MODUS[1]: Each change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1. STA TUS
PRELIMINARY DATA SHEET MSP 34x1G Micronas 29 3.3.2.6. Write Registers on I2C Subaddress 12hex Table 3–11:Write Registers on I2C Subaddress 12hex Register Address Function Name PREPROCESSING 00 0Ehex FM/AM Prescale bit[15:8] 00hex Defines the input prescale gain for the demodulated ... FM or AM signal hex 00hex off (RESET condition) For all FM modes except satellite FM and AM-mode, the combinations of pres- cale value and FM deviation listed below lead to internal full scale. FM mode bit[15:8] 7Fhex 28 kHz FM deviation 48hex 50 kHz FM deviation 30hex 75 kHz FM deviation 24hex 100 kHz FM deviation 18hex 150 kHz FM deviation 13hex 180 kHz FM deviation (limit) FM high deviation mode (HDEV2, MSP Standard Code = Chex) bit[15:8] 30hex 150 kHz FM deviation 14hex 360 kHz FM deviation (limit) FM very high deviation mode (HDEV3, MSP Standard Code = 6 and Dhex) bit[15:8] 20hex 450 kHz FM deviation 1Ahex 540 kHz FM deviation (limit) Satellite FM with adaptive deemphasis bit[15:8] 10hex recommendation AM mode (MSP Standard Code = 9) bit[15:8] 7Chex recommendation for SIF input levels from 0.1 Vpp to 0.8 Vpp (Due to the AGC being switched on, the AM-output level remains stable and independent of the actual SIF-level in the mentioned input range) PRE_FM
MSP 34x1G PRELIMINARY DATA SHEET
30 Micronas
(continued) 00 0Ehex FM Matrix Modes Defines the dematrix function for the demodulated FM signal bit[7:0] 00hex no matrix (used for bilingual and unmatrixed stereo sound) 01hex German stereo (Standard B/G) 02hex Korean stereo (also used for BTSC, EIA-J and FM Radio) 03hex sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier) 04hex sound B mono In case of Automatic Sound Select = on, the FM Matrix Mode is set automati- cally. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed. In order not to disturb the automatic process, the low part of any I2C transmis- sion to this register is ignored. Therefore, any FM-Matrix readback values may differ from data written previously. In case of Automatic Sound Select = off, the FM Matrix Mode must be set as shown in Table 6–17 of Appendix B. To enable a Forced Mono Mode set A2 THRESHOLD as described in Section 6.3.2.on page 89 FM_MATRIX 00 10hex NICAM Prescale Defines the input prescale value for the digital NICAM signal bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 20hex 0d B g a i n 5Ahex 9 dB gain (recommendation) 7Fhex +12 dB gain (maximum gain) PRE_NICAM 00 16hex 00 12hex I2S1 Prescale I2S2 Prescale Defines the input prescale value for digital I2S input signals bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 10hex 0 dB gain (recommendation) 7Fhex +18 dB gain (maximum gain) PRE_I2S1 PRE_I2S2 00 0Dhex SCART Input Prescale Defines the input prescale value for the analog SCART input signal bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 19hex 0d B g a i n ( 2 VRMS input leads to digital full scale) Due to the Dolby requirements, this is the maximum value allowed to prohibit clipping of a 2 VRMS input signal. 7Fhex +14 dB gain (400 mVRMS input leads to digital full scale) PRE_SCART Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 31 SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Source for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I 2S Output Quasi-Peak Detector bit[15:8] 0 “FM/AM ”: demodulated FM or AM mono signal 1 “Stereo or A/B”: demodulator Stereo or A/B signal (in manual mode, this source is identical to the NICAM source in the MSP 3410D) 3 “Stereo or A”: demodulator Stereo Sound or Language A (only defined for Automatic Sound Select) 4 “Stereo or B”: demodulator Stereo Sound or Language B (only defined for Automatic Sound Select) 2S C A R T i n p u t 2S1 input 6I 2S2 input For demodulator sources, see Table 2–2. SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK 00 08 hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex Matrix Mode for: Loudspeaker Output Headphone Output SCART1 DA Output SCART2 DA Output I 2S Output Quasi-Peak Detector bit[7:0] 00hex Sound A Mono (or Left Mono) 10hex Sound B Mono (or Right Mono) 20hex Stereo (transparent mode) 30hex Mono (sum of left and right inputs divided by 2) special modes are available (see Section 6.5.1. on page 97) In Automatic Sound Select mode, the demodulator source channels are set according to Table 2–2. Therefore, the matrix modes of the corresponding out- put channels should be set to “Stereo” (transparent). MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
32 Micronas
LOUDSPEAKER AND HEADPHONE PROCESSING 00 00hex 00 06hex Volume Loudspeaker Volume Headphone bit[15:8] volume table with 1 dB step size 7Fhex +12 dB (maximum volume) 7Ehex +11 dB ... 74hex +1d B 73hex 0d B 72hex −1d B ... hex −113 dB 01hex −114 dB 00hex Mute (reset condition) FFhex Fast Mute (needs about 75 ms until the signal is com- pletely ramped down) bit[7:5] higher resolution volume table 0 +0d B 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit[4] 0 must be set to 0 bit[3:0] clipping mode 0 reduce volume 1 reduce tone control 2 compromise 3d y n a m i c With large scale input signals, positive volume settings may lead to signal clipping. The MSP 34x1G loudspeaker and headphone volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute posi- tion by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted. If the clipping mode is set to “reduce volume”, the following rule is used: To pre- vent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is “reduce tone control”, the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is “compromise ”, the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB. If the clipping mode is “dynamic ”, volume is reduced automatically if the signal amplitudes would exceed −2 dBFS within the IC. For operation of MDB, dyna- mic mode must be switched on. VOL_MAIN VOL_AUX Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 33 00 29hex Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] 00hex AVC off (and reset internal variables) 08hex AVC on bit[11:8] 08hex 8 sec decay time 04hex 4 sec decay time 02hex 2 sec decay time 01hex 20 ms decay time (should be used for approx. 100 ms after channel change) AVC 00 01 hex 00 30hex Balance Loudspeaker Channel Balance Headphone Channel bit[15:8] Linear Mode 7Fhex Left muted, Right 100% 7Ehex Left 0.8%, Right 100% ... 01hex Left 99.2%, Right 100% 00hex Left 100%, Right 100% FFhex Left 100%, Right 99.2% ... hex Left 100%, Right 0.8% 81hex Left 100%, Right muted bit[15:8] Logarithmic Mode 7Fhex Left −127 dB, Right 0 dB 7Ehex Left −126 dB, Right 0 dB ... hex Left −1 dB, Right 0 dB 00hex Left 0 dB, Right 0 dB FFhex Left 0 dB, Right −1d B ... hex Left 0 dB, Right −127 dB 80hex Left 0 dB, Right −128 dB bit[7:0] Balance Mode 00hex linear 01hex logarithmic Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. BAL_MAIN BAL_AUX Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
34 Micronas
00 20hex Tone Control Mode Loudspeaker Channel bit[15:8] 00hex bass and treble is active FFhex equalizer is active Defines whether Bass/Treble or Equalizer is activated for the loudspeaker chan- nel. Bass and Equalizer cannot work simultaneously. If Equalizer is used, Bass, and Treble coefficients must be set to zero and vice versa. TONE_MODE 00 02hex 00 31hex Bass Loudspeaker Channel Bass Headphone Channel bit[15:8] extended range 7Fhex +20 dB 78hex +18 dB 70hex +16 dB 68hex +14 dB normal range 60hex +12 dB 58hex +11 dB ... 08hex +1d B 00hex 0d B F8hex −1d B ... hex −11 dB A0hex −12 dB Higher resolution is possible: an LSB step in the normal range results in a gain step of about 1/8 dB, in the extended range about 1/4 dB. With positive bass settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not rec- ommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. BASS_MAIN BASS_AUX Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 35 00 03hex 00 32hex Treble Loudspeaker Channel Treble Headphone Channel bit[15:8] 78hex +15 dB 70hex +14 dB ... 08hex +1d B 00hex 0d B F8hex −1d B ... hex −11 dB A0hex −12 dB Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive treble settings, internal clipping may occur even with overall vol- ume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. TREB_MAIN TREB_AUX 00 21 hex 00 22hex 00 23hex 00 24hex 00 25hex Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Equalizer Loudspeaker Channel Band 2 (center: 500 Hz) Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz) Equalizer Loudspeaker Channel Band 4 (center: 5 kHz) Equalizer Loudspeaker Channel Band 5 (above: 10 kHz) bit[15:8] 60 hex +12 dB 58hex +11 dB ... hex +1d B 00hex 0d B F8hex −1d B ... A8hex −11 dB A0hex −12 dB Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB. With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with vol- ume, would result in an overall positive gain. EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5 Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
36 Micronas
Loudness Loudspeaker Channel Loudness Headphone Channel bit[15:8] Loudness Gain 44hex +17 dB 40hex +16 dB ... 04hex +1d B 03hex +0.75 dB 02hex +0.5 dB 01hex +0.25 dB 00hex 0d B bit[7:0] Loudness Mode 00hex normal (constant volume at 1 kHz) 04hex Super Bass (constant volume at 2 kHz) Higher resolution of Loudness Gain is possible: An LSB step results in a gain step of about 1/4 dB. Loudness increases the volume of low- and high-frequency signals, while keep- ing the amplitude of the reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness intro- duces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. The corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant vol- ume is shifted from 1 kHz to 2 kHz. LOUD_MAIN LOUD_AUX Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 37 00 05hex Spatial Effects Loudspeaker Channel bit[15:8] Effect Strength 7Fhex Enlargement 100% 3Fhex Enlargement 50% ... 01hex Enlargement 1.5% 00hex Effect off FFhex reduction 1.5% ... hex reduction 50% 80hex reduction 100% bit[7:4] Spatial Effect Mode 0hex Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) 2hex Stereo Basewidth Enlargement (SBE) only. (Mode B) bit[3:0] Spatial Effect High-Pass Gain 0hex max. high-pass gain 2hex 2/3 high-pass gain 4hex 1/3 high-pass gain 6hex min. high-pass gain 8hex automatic Spatial effects should not be used together with 3D-PANORAMA or PANORAMA. There are several spatial effect modes available: In mode A (low byte = 00hex), the spatial effect depends on the source mode. If the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode B, only Stereo Basewidth Enlargement is effective. For mono input sig- nals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0 hex yields a flat response for center signals (L = R), but a high-pass function for L or R only signals. A value of 6hex has a flat response for L or R only signals, but a low-pass function for center signals. By using 8hex, the fre- quency response is automatically adapted to the sound material by choosing an optimal high-pass gain. SPAT_MAIN Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
38 Micronas
00 2Chex Subwoofer Level Adjustment bit[15:8] 0Chex +12 dB ... hex +1 dB 00hex 0 dB (default) FFhex −1d B ... E3hex −29 dB E2hex −30 dB ... hex Mute bit[7:0] 00hex must be zero If MDB is added onto the main channel, this register should be set to 00hex SUBW_LEVEL 00 2Dhex Subwoofer Corner Frequency bit[15:8] 5...40 corner frequency in 10 Hz steps (range: 50...400 Hz) If MDB is active, SUBW_FREQ must be set to a value higher than the MDB Lowpass Frequency (MDB_LP). Choosing the corner frequency of the subwoofer closer to MDB_LP results in a narrower MDB frequency range. Recommended value: 1.5×MDB_LP Subwoofer Complementary High-Pass Filter bit[7:0] 00hex loudspeaker channel unfiltered 01hex a complementary high-pass is processed in the loud- speaker output channel hex MDB added onto main channel SUBW_FREQ SUBW_HP MDB CONTROL REGISTERS 00 68hex MDB Effect Strength bit[15:8] 00hex MDB OFF (default) 7Fhex maximum MDB bit[7:0] 00hex must be zero The MDB effect strength can be adjusted in 1 dB steps. A value of 44hex will yield a medium MDB effect. MDB_STR 00 69hex MDB Amplitude Limit bit[15:8] 00hex 0 dBFS (default limitation) FFhex −1d B F S ... hex −32 dBFS bit[7:0] 00hex must be zero The MDB Amplitude Limit defines the maximum allowed amplitude at the output of the MDB relative to 0 dbFS. If the amplitude exceeds MDB_LIM, the gain of the MDB is automatically reduced. Note that the Volume Clipping Mode must be set to “dynamic” (see page 32). MDB_LIM Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 39 00 6Ahex MDB Harmonic Content bit[15:8] 00hex no harmonics are added (default) 64hex 50% fundamentals + 50% harmonics 7Fhex 100% harmonics bit[7:0] 00hex must be zero MDB creates harmonics of the frequencies below the MDB highpass frequency (MDB_HP). The variable MDB_HMC describes the ratio of the harmonics towards the original signal. MDB_HMC 00 6B hex MDB Low Pass Corner Frequency bit[15:8] 5 50 Hz 66 0 H z ... 30 300 Hz bit[7:0] 00 hex must be zero The MDB lowpass corner frequency (range 50...300 Hz) defines the upper cor- ner frequency of the MDB bandpass filter. Recommended values are the same as for the MDB highpass corner frequency (MDB_HP). MDB_LP 00 6C hex MDB High Pass Corner Frequency bit[15:8] 2 20 Hz 33 0 H z ... 30 300 Hz bit[7:0] 00 hex must be zero The MDB highpass corner frequency defines the lower corner frequency of the MDB bandpass filter. The highpass filter avoids loading the loudspeakers with low frequency components that are below the speakers’ cut off frequency. Rec- ommended values for subwoofer systems are around 5 (=50 Hz), for regular TV sets around 10 (=100 Hz). MDB_HP Table 3–11:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
40 Micronas
Volume SCART1 Output Channel Volume SCART2 Output Channel bit[15:8] volume table with 1 dB step size 7Fhex +12 dB (maximum volume) 7Ehex +11 dB ... 74hex +1d B 73hex 0d B 72hex −1d B ... hex −113 dB 01hex −114 dB 00hex Mute (reset condition) bit[7:5] higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit[4:0] 01 hex this must be 01hex VOL_SCART1 VOL_SCART2 Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 41 SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB Register Defines the level of the digital output pins and the position of the SCART switches bit[15] 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) bit[14] 0/1 low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) bit[13:5] SCART DSP Input Select xxxx00xx0 SCART1 to DSP input (RESET position) xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10xx0 SCART2 to DSP input xxxx11xx0 SCART3 to DSP input xxxx00xx1 SCART4 to DSP input xxxx11xx1 mute DSP input bit[13:5] SCART1 Output Select xx00xxx0x SCART3 input to SCART1 output (RESET position) xx01xxx0x SCART2 input to SCART1 output xx10xxx0x MONO input to SCART1 output xx11xxx0x SCART1 DA to SCART1 output xx00xxx1x SCART2 DA to SCART1 output xx01xxx1x SCART1 input to SCART1 output xx10xxx1x SCART4 input to SCART1 output xx11xxx1x mute SCART1 output bit[13:5] SCART2 Output Select 00xxxx0xx SCART1 DA to SCART2 output (RESET position) 01xxxx0xx SCART1 input to SCART2 output 10xxxx0xx MONO input to SCART2 output 00xxxx1xx SCART2 DA to SCART2 output 01xxxx1xx SCART2 input to SCART2 output 10xxxx1xx SCART3 input to SCART2 output 11xxxx1xx SCART4 input to SCART2 output 11xxxx0xx mute SCART2 output The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined. ACB_REG BEEPER 00 14hex Beeper Volume and Frequency bit[15:8] Beeper Volume 00hex off 7Fhex maximum volume bit[7:0] Beeper Frequency 01hex 16 Hz (lowest) 40hex 1k H z FFhex 4k H z BEEPER Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
42 Micronas
VIRTUAL SURROUND PROCESSING 00 48hex Virtual Surround OFF/ON Switch bit[15:8] 00hex virtual surround sound off (normal baseband processing) 01hex virtual surround processing bit[7:0] 00hex must be 0 Be sure to switch off Spatial Effects Loudspeaker Channel (register 0005hex) if 3D-PANORAMA is in use. VIRT_ON 00 49hex Virtual Surround Spatial Effects bit[15:8] Spatial Effect Strength 7Fhex Enlargement 100% 3Fhex Enlargement 50% ... 01hex Enlargement 1.5% 00hex Effect off bit[7:0] 00hex must be 0 Increases the perceived basewidth of the reproduced left and right front chan- nels. Recommended value: 50% = 40hex. In contrast to the Spatial Effects Loudspeaker Channel, the Surround Spatial Effects is optimized for virtual sur- round. VIRT_SPAT 00 4A hex Virtual Surround 3D Effect Strength bit[15:8] Virtual Surround Effect Strength 7Fhex Effect 100% 3Fhex Effect 50% ... hex Effect 1.5% 00hex Effect off bit[7:0] 00hex must be 0 Strength of the surround effect in PANORAMA or 3D-PANORAMA mode. Recommended value: 66% = 54hex. VIRT_3DEFF 00 4Bhex Virtual Surround Mode bit[15:8] 00hex must be 0 bit[7:0] 50hex PANORAMA virtualizer 60hex 3D-PANORAMA virtualizer VIRT_MODE Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 34x1G Micronas 43 NOISE GENERATOR 00 4Dhex Noise Generator bit[15:8] 00hex Noise generator off 80hex Noise generator on bit[7:0] A0hex Noise on left channel B0hex Noise on center channel C0 hex Noise on right channel D0 hex Noise on surround channel Determines the active channel for the noise generator. NOISE_CHAN Table 3–11:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
MSP 34x1G PRELIMINARY DATA SHEET
44 Micronas
3.3.2.7. Read Registers on I2C Subaddress 13hex Table 3–12:Read Registers on I2C Subaddress 13hex Register Address Function Name QUASI-PEAK DETECTOR READOUT 00 19hex 00 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right bit[15:0] 0hex... 7FFFhex values are 16 bit two’s complement (only positive) QPEAK_L QPEAK_R MSP 34x1G VERSION READOUT REGISTERS 00 1Ehex MSP Hardware Version Code bit[15:8] 02hex MSP 34x1G - B8 A change in the hardware version code defines hardware optimizations that may have influence on the chip’s behavior. The readout of this register is iden- tical to the hardware version code in the chip’s imprint. MSP Major Revision Code bit[7:0] 07 hex MSP 34x1G - B8 The major revision code of the MSP 34x1G is 7. MSP_HARD MSP_REVISION 00 1Fhex MSP Product Code bit[15:8] 01hex MSP 3401 G - B8 0Bhex MSP 3411 G - B8 15hex MSP 3421 G - B8 29hex MSP 3441 G - B8 33hex MSP 3451 G - B8 3D hex MSP 3461 G - B8 By means of the MSP-Product Code, the control processor is able to decide which TV sound standards have to be considered. MSP ROM Version Code bit[7:0] 41hex MSP 34x1G - A1 42hex MSP 34x1G - A2 48hex MSP 34x1G - B8 A change in the ROM version code defines internal software optimizations, that may have influence on the chip’s behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 34x1G versions according to this number. To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of hex is added to the ROM version code of the chip’s imprint. MSP_PRODUCT MSP_ROM
PRELIMINARY DATA SHEET MSP 34x1G Micronas 45 3.4. Programming Tips This section describes the preferred method for initial- izing the MSP 34x1G. The initialization is grouped into four sections: – SCART Signal Path (analog signal path) – Demodulator – SCART and I2S Inputs – Output Channels See Fig. 2–1 on page 9 for a complete signal flow. SCART Signal Path 1. Select analog input for the SCART baseband pro- cessing (SCART DSP Input Select) by means of the ACB register. 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB regis- ter. Demodulator For a complete setup of the TV sound processing from analog IF input to the source selection, the following steps must be performed: 1. Set MODUS register to the preferred mode and Sound IF input. 2. Choose preferred prescale (FM and NICAM) values. 3. Write STANDARD SELECT register. 4. If Automatic Sound Select is not active: Choose FM matrix repeatedly according to the sound mode indicated in the STATUS register. SCART and I 2S Inputs 1. Select preferred prescale for SCART. 2. Select preferred prescale for I 2S inputs (set to 0 dB after RESET). Output Channels 1. Select the source channel and matrix for each out- put channel. 2. Set audio baseband processing. 3. Select volume for each output channel. 3.5. Examples of Minimum Initialization Codes Initialization of the MSP 34x1G according to these list- ings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I 2C controlled reset of the IC. 2. Write MODUS register (with Automatic Sound Select). 3. Set Source Selection for loudspeaker channel (with matrix set to STEREO). 4. Set Prescale (FM and/or NICAM and dummy FM matrix). 5. Write STANDARD SELECT register. 6. Set Volume loudspeaker channel to 0 dB. 3.5.1. SCART1 Input to Loudspeaker in Stereo Sound <80 00 80 00> // reset <80 00 00 00> <80 12 00 08 02 20> // source loudspeaker = scart, stereo <80 12 00 0d 19 00> // prescale scart <80 12 00 00 73 00> // volume main = 0dB 3.5.2. SCART1 Input to Loudspeaker in 3D-PANORAMA Sound <80 00 80 00> // reset <80 00 00 00> <80 12 00 08 02 20> // source loudspeaker = scart, stereo <80 12 00 0d 19 00> // prescale scart <80 12 00 00 73 00> // volume main = 0dB <80 12 00 48 01 00> // virtual surround sound: on <80 12 00 49 40 00> // Surround spatial effect = 50% <80 12 00 4a 54 00> // panorama sound effect = 66% <80 12 00 4b 00 60> // Surround mode = 3d_panorama <80 12 00 4d 00 00> // Noise Sequencer = off 3.5.3. Noise Sequencer for 3D-PANORAMA Sound // switch into 3D-PANORAMA sound (s.a.). Then: <80 12 00 4d 80 a0> // noise L [wait for 2 seconds] <80 12 00 4d 80 b0> // noise C [wait for 2 seconds] <80 12 00 4d 80 c0> // noise R [wait for 2 seconds] <80 12 00 4d 80 d0> // noise S [wait for 2 seconds] // switch back to normal operation <80 12 00 4d 00 00> // Noise Sequencer = off
MSP 34x1G PRELIMINARY DATA SHEET
46 Micronas
3.5.4. B/G-FM (A2 or NICAM) < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = MONO/SOUNDA < 8 01 20 0 1 05 A 0 0 >// NICAM-Prescale = 5Ahex < 8 01 00 0 2 00 0 0 3 >// Standard Select: A2 B/G or NICAM B/G or < 8 01 00 0 2 00 0 0 8 > < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.5. BTSC-Stereo < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 00 0 2 00 0 2 0 >// Standard Select: BTSC-STEREO < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.6. BTSC-SAP with SAP at Loudspeaker Channel < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 20 0 0 80 4 2 0 >// Source Sel. = (St or B) & Ch. Matr. = St < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 00 0 2 00 0 2 1 >// Standard Select: BTSC-SAP < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.7. FM-Stereo Radio < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 00 0 2 00 0 4 0 >// Standard Select: FM-STEREO-RADIO < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.8. Automatic Standard Detection A detailed software flow diagram is shown in Fig. 3–2 on page 47. < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 20 0 1 05 A 0 0 >// NICAM-Prescale = 5Ahex < 8 01 00 0 2 00 0 0 1 >// Standard Select: Automatic Standard Detection // Wait till ST ANDARD RESULT contains a value ≤ 07FF // IF STANDARD RESULT contains 0000 // do some error handling // ELSE < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.9. Software Flow for Interrupt driven STATUS Check A detailed software flow diagram is shown in Fig. 3–2 on page 47. If the D_CTR_I/O_1 pin of the MSP 34x1G is con- nected to an interrupt input pin of the controller, the fol- lowing interrupt handler can be applied to be automati- cally called with each status change of the MSP 34x1G. The interrupt handler may adjust the TV display according to the new status information. Interrupt Handler: <80 11 02 00 <81 dd dd>// Read STATUS // adjust TV display with given status information // Return from Interrupt
PRELIMINARY DATA SHEET MSP 34x1G Micronas 47 Fig. 3–2:Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the Automatic Sound Select feature Write SOURCE SELECT Settings Example: set loudspeaker Source Select to "Stereo or A" set headphone Source Select to "Stereo or B" set SCART_Out Source Select to "Stereo or A/B" set Channel Matrix mode for all outputs to "Stereo" Write 01 into STANDARD SELECT Register (Start Automatic Standard Detection) Write MODUS Register: Example for the essential bits: [0] = 1 Automatic Sound Select = on [1] = 1 Enable interrupt if STATUS changes [8] = 0 ANA_IN1+ is selected Define Preference for Automatic Standard Detection: [12] = 0 If 6.5 MHz, set SECAM-L [14:13] = 3 Ignore 4.5 MHz carrier Write FM/AM-Prescale Write NICAM-Prescale In case of MSPG- Interrupt to Controller: Read STATUS Adjust TV-Display If Bilingual, adjust Source Select setting if required Result = 0 set previous standard or set standard manually according picture information yes no expecting MSPG-interrupt
MSP 34x1G PRELIMINARY DATA SHEET
48 Micronas
- Specifications 4.1. Outline Dimensions Fig. 4–1: 68-Pin Plastic Leaded Chip Carrier Package (not intended for new designs) (PLCC68) Weight approximately 4.8 g Dimensions in mm Fig. 4–2: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm Fig. 4–3: 52-Pin Plastic Shrink Dual-Inline Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm 24.2 0.1± 4.75±0.15 25.14 0.12± 25.14 0.12± 23.3 0.3± 0.23 0.04± 0.9 0.2± x 45°1.1 1.2 x 45° 4327 619 0.1 1.27 1.27 SPGS704000-1(P68)/1E 9 2 7.5 7.5 0.71 0.05± 0.48 0.06± 4.05±0.1 1.9±0.05 24.2 0.1± 16 x 1.27 = 20.320.1± 16 x 1.27 = 20.320.1± 13 2 3364 57.7±0.1 0.8±0.2 3.8±0.13.2±0.2 1.778 1±0.05 31 x 1.778 = 55.1±0.1 0.48±0.06 20.3±0.5 0.28±0.06 18±0.05 19.3±0.1 SPGS703000-1(P64)/1E 12 6 2752 47.0±0.1 0.6±0.2 4.0±0.12.8±0.2 1.778 1±0.05 25 x 1.778 = 44.4±0.1 0.48±0.06 SPGS703000-1(P52)/1E 16.3±1 0.28±0.06 14±0.1 15.6±0.1
PRELIMINARY DATA SHEET MSP 34x1G Micronas 49 Fig. 4–4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm Fig. 4–5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 3.5 g Dimensions in mm 0.8 0.8 4164 241 0.13 ±0.2 SPGS705000-3(P80)/1E 23.2 0.15± 17.2 0.15± 20 0.1± 14 0.1± 0.17 0.04± 0.37 0.04± 1.3 0.05± 2.7 0.1± 10 0.1± 1.75 1.75 11 6 3348 D0025/3E 0.5 0.5 0.112 0.2± 1.5 0.1± 1.4 0.05± 12 0.2± 10 0.1± 0.145 0.055± 0.22 0.05± 15 x 0.5 = 7.50.1± 15 x 0.5 = 7.50.1±
MSP 34x1G PRELIMINARY DATA SHEET
50 Micronas
4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS Pin No. Pin Name Type Connection (if not used) Short Description PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin 1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 −−−− NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR data output 41 4 1 2 76I 2 S _ D A _ I N 1 I N L V I 2S1 data input 51 3 1 1 65I 2 S _ D A _ O U T O U T L V I 2S data output 61 2 1 0 54I 2 S _ W S I N / O U T L V I 2S word strobe 71 1 943I 2 S _ C L I N / O U T L V I 2S clock 81 0 832I 2 C _ D A I N / O U T X I 2C data 99721I 2 C _ C L I N / O U T X I 2C clock 10 8 − 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN X Stand-by (low-active) 1 26 5 7 96 2A D R _ S E L I N X I 2C Bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 − 76 59 NC LV Not connected 16 2 − 75 58 NC LV Not connected 17 −−−− NC LV Not connected 18 1 2 74 57 AUD_CL_OUT OUT LV Audio clock output (18.432 MHz) 19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT X Crystal oscillator 21 62 51 71 54 XTAL_IN IN X Crystal oscillator 22 61 50 70 53 TESTEN IN X Test pin 23 60 49 69 52 ANA_IN2 + IN AVSS via 56 pF / LV IF input 2 (can be left vacant, only if IF input 1 is also not in use) 24 59 48 68 51 ANA_IN − IN AVSS via 56 pF / LV IF common (can be left vacant, only if IF input 1 is also not in use)
PRELIMINARY DATA SHEET MSP 34x1G Micronas 51 25 58 47 67 50 ANA_IN1 + IN LV IF input 1 26 57 46 66 49 AVSUP X Analog power supply 5 V −−− 65 − AVSUP X Analog power supply 5 V −−− 64 − NC LV Not connected −−− 63 − NC LV Not connected 27 56 45 62 48 AVSS X Analog ground −−− 61 − AVSS X Analog ground 28 55 44 60 47 MONO_IN IN LV Mono input −−− 59 − NC LV Not connected 29 54 43 58 46 VREFTOP X Reference voltage IF A/D converter 30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 − 55 43 ASG AHVSS Analog Shield Ground 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 − 52 40 ASG AHVSS Analog Shield Ground 36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 − 49 37 ASG AHVSS Analog Shield Ground 39 44 − 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 − 47 35 SC4_IN_L IN LV SCART 4 input, left 41 −− 46 − NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC X Analog reference voltage 43 41 35 44 33 AHVSS X Analog ground −−− 43 − AHVSS X Analog ground −−− 42 − NC LV Not connected −−− 41 − NC LV Not connected 44 40 34 40 32 CAPL_M X Volume capacitor MAIN 45 39 33 39 31 AHVSUP X Analog power supply 8 V 46 38 32 38 30 CAPL_A X Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left Pin No. Pin Name Type Connection (if not used) Short Description PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
MSP 34x1G PRELIMINARY DATA SHEET
52 Micronas
48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 X Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 −− 32 − NC LV Not connected 53 32 − 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 − 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 X Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right −−− 23 − NC LV Not connected −−− 22 − NC LV Not connected 61 24 20 21 16 RESETQ IN X Power-on-reset 62 23 − 20 15 NC LV Not connected 63 22 − 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I 2S2-data input 66 19 17 16 11 DVSS X Digital ground −−− 15 − DVSS X Digital ground −−− 14 − DVSS X Digital ground 67 18 16 13 10 DVSUP X Digital power supply 5 V −−− 12 − DVSUP X Digital power supply 5 V −−− 11 − DVSUP X Digital power supply 5 V 68 17 15 10 9 ADR_CL OUT LV ADR clock Pin No. Pin Name Type Connection (if not used) Short Description PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
PRELIMINARY DATA SHEET MSP 34x1G Micronas 53 4.3. Pin Descriptions Pin numbers refer to the 80-pin PQFP package. Pin 1, NC – Pin not connected. Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–18) Via this pin, the I2C-bus clock signal has to be sup- plied. The signal can be pulled down by the MSP in case of wait conditions. Pin 3, I2C_DA – I 2C Data Input/Output (Fig. 4–18) Via this pin, the I2C-bus data is written to or read from the MSP . Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–19) Clock line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS – I2S Word Strobe Input/Output (Fig. 4–19) Word strobe line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S word strobe has to be supplied. Pin 6, I2S_DA_OUT – I2S Data Output (Fig. 4–23) Output of digital serial sound data of the MSP on the I 2S bus. Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–15) First input of digital serial sound data to the MSP via the I 2S bus. Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–23) Output of digital serial data to the DRP 3510A via the ADR bus. Pin 9, ADR_WS – ADR Bus Word Strobe Output (Fig. 4–23) Word strobe output for the ADR bus. Pin 10, ADR_CL – ADR Bus Clock Output (Fig. 4–23) Clock line for the ADR bus. Pins 11, 12, 13, DVSUP* – Digital Supply Voltage Power supply for the digital circuitry of the MSP . Must be connected to a +5 V power supply. Pins 14, 15, 16, DVSS* – Digital Ground Ground connection for the digital circuitry of the MSP . Pin 17, I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–15) Second input of digital serial sound data to the MSP via the I2S bus. Pins 18, 19, 20, NC – Pins not connected. Pin 21, RESETQ – Reset Input (Fig. 4–11) In the steady state, high level is required. A low level resets the MSP 34x1G. Pins 22, 23, NC – Pins not connected. Pins 24, 25, DACA_R/L – Headphone Outputs (Fig. 4–21) Output of the headphone signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC off- set on these pins depends on the selected headphone volume. Pin 26, VREF2 – Reference Ground 2 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the loudspeaker and head- phone outputs. Pins 27, 28, DACM_R/L – Loudspeaker Outputs (Fig. 4–21) Output of the loudspeaker signal. A 1-nF capacitor to AHVSS must be connected to these pins. The DC off- set on these pins depends on the selected loud- speaker volume. Pin 29, NC – Pin not connected. Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–21) Output of the subwoofer signal. A 1-nF capacitor to AHVSS must be connected to this pin. Due to the low frequency content of the subwoofer output, the value of the capacitor may be increased for better suppres- sion of high-frequency noise. The DC offset on this pin depends on the selected loudspeaker volume. Pins 31, 32 NC – Pin not connected. Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs (Fig. 4–22) Output of the SCART2 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled. Pin 35, VREF1 – Reference Ground 1 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–22) Output of the SCART1 signal. Connections to these pins must use a 100-Ω series resistor and are intended to be AC-coupled.
MSP 34x1G PRELIMINARY DATA SHEET
54 Micronas
Pin 38, CAPL_A – Volume Capacitor Headphone (Fig. 4–24) A 10-µF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for headphone volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-µF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induc- tion. Pin 39, AHVSUP* – Analog Power Supply High Volt- age Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8V s u p p l y . Pin 40, CAPL_M – Volume Capacitor Loudspeaker (Fig. 4–24) A 10-µF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for loudspeaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1µF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induc- tion. Pins 41, 42, NC – Pins not connected. Pins 43, 44, AHVSS* – Ground for Analog Power Sup- ply High Voltage Ground connection for the analog circuitry of the MSP (except IF input). Pin 45, AGNDC – Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be con- nected to the VREF pins with a 3.3-µF and a 100-nF capacitor in parallel. This pins shows a DC level of typ- ically 3.73 V. Pin 46, NC – Pin not connected. Pins 47, 48, SC4_IN_L/R – SCART4 Inputs (Fig. 4–14) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pin 49, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R – SCART3 Inputs (Fig. 4–14) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pin 52, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–14) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled. Pin 55, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–14) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, VREFTOP – Reference Voltage IF A/D Con- verter (Fig. 4–16) Via this pin, the reference voltage for the IF A/D con- verter is decoupled. It must be connected to AVSS pins with a 10-µF and a 100-nF capacitor in parallel. Traces must be kept short. Pin 59, NC – Pin not connected. Pin 60 MONO_IN – Mono Input (Fig. 4–14) The analog mono input signal is fed to this pin. Analog input connection must be AC-coupled. Pins 61, 62, AVSS* – Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP . Pins 63, 64, NC – Pins not connected. Pins 65, 66, AVSUP* – Ground for Analog Power Sup- ply Voltage Power is supplied via this pin for the analog IF input cir- cuitry of the MSP . This pin must be connected to the +5 V supply. Pin 67, ANA_IN1 + – IF Input 1 (Fig. 4–16) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 68, ANA_IN − – IF Common (Fig. 4–16) This pins serves as a common reference for ANA_IN1/ 2+ inputs. Pin 69, ANA_IN2 + – IF Input 2 (Fig. 4–16) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symmetrical op amp, ANA_IN− to the other. Pin 70, TESTEN – Test Enable Pin (Fig. 4–12) This pin enables factory test modes. For normal opera- tion, it must be connected to ground.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 55 Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input and Output Pins (Fig. 4–20) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. An external clock can be fed into XTAL_IN. The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground con- nection point. Pin 73, TP – This pin enables factory test modes. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT – Audio Clock Output (Fig. 4–20) This is the 18.432 MHz main clock output. Pins 75, 76, NC – Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/ Output Pins (Fig. 4–19) General purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the control- ler. Pin 79, ADR_SEL – I 2C Bus Address Select (Fig. 4–17) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be connected to ground (I 2C device addresses 80/81hex), to +5 V sup- ply (84/85hex), or left open (88/89hex). Pin 80, STANDBYQ – Stand-by In normal operation, this pin must be high. If the MSP 34x1G is switched off by first pulling STANDBYQ low and then (after >1µs delay) switching off DVSUP and AVSUP , but keeping AHVSUP (‘Standby’-mode ), the SCART switches maintain their position and func- tion. * Application Note: All ground pins should be connected to one low-resis- tive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF , 470 pF , 1.5 nF , and 10µF. T h e capacitor with the lowest value should be placed near- est to the DVSUP and DVSS pins. The ASG pins should be connected as closely as pos- sible to the MSP ground. If they are lead with the SCART -inputs as shielding lines, they should not be connected to ground at the SCART connector.
MSP 34x1G PRELIMINARY DATA SHEET
56 Micronas
4.4. Pin Configurations Fig. 4–6:68-pin PLCC package (not intended for new designs) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 987654321 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 26 44 MSP 34x1G NC STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN − ANA_IN1+ DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA NC ADR_WS I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L AVSS SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS ASG AVSUP CAPL_M
PRELIMINARY DATA SHEET MSP 34x1G Micronas 57 Fig. 4–7:64-pin PSDIP package Fig. 4–8:52-pin PSDIP package 1AUD_CL_OUT 2NC 3NC 4D_CTR_I/O_1 5D_CTR_I/O_0 6ADR_SEL 7STANDBYQ 8NC 9I2C_CL 10I2C_DA 11I2S_CL 12I2S_WS 13I2S_DA_OUT 14I2S_DA_IN1 15ADR_DA 16ADR_WS TP64 XTAL_OUT63 XTAL_IN62 TESTEN61 ANA_IN2+60 ANA_IN −59 ANA_IN+58 AVSUP57 AVSS56 MONO_IN55 VREFTOP54 SC1_IN_R53 SC1_IN_L52 ASG51 SC2_IN_R50 SC2_IN_L49 17ADR_CL 18DVSUP 19DVSS 20I2S_DA_IN2 21NC 22NC 23NC 24RESETQ 25DACA_R 26DACA_L ASG48 SC3_IN_R47 SC3_IN_L46 ASG45 SC4_IN_R44 SC4_IN_L43 AGNDC42 AHVSS41 CAPL_M40 AHVSUP39 MSP 34x1G VREF2 DACM_R DACM_L NC DACM_SUB NC CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R TP AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN − ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L DVSS I2S_DA_IN2 NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R MSP 34x1G
MSP 34x1G PRELIMINARY DATA SHEET
58 Micronas
Fig. 4–9:80-pin PQFP package 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSUP AVSUP ANA_IN1+ ANA_IN − ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG NC SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL NC DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2 NC NC NC RESETQ NC NC DACA_R MSP 34x1G
PRELIMINARY DATA SHEET MSP 34x1G Micronas 59 Fig. 4–10:64-pin PLQFP package AVSUP ANA_IN1+ ANA_IN − ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/OUT1 D_CTR_I/OUT0 ADR_SEL STANDBYQ NC CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L AVSS ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ MSP 34x1G 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MSP 34x1G PRELIMINARY DATA SHEET
60 Micronas
4.5. Pin Circuits Fig. 4–11:Input Pin: RESETQ Fig. 4–12:Input Pin TESTEN Fig. 4–13:Input Pin: MONO_IN Fig. 4–14:Input Pins: SC4-1_IN_L/R Fig. 4–15:Input Pins: I2S_DA_IN1, I2S_DA_IN2, STANDBYQ Fig. 4–16:Input Pins: VREFTOP, ANA_IN1 +, ANA_IN-, ANA_IN2+ Fig. 4–17:Input Pin: ADR_SEL DVSS >300 k AVSUP 200 k ≈ 3.75 V 24 kΩ ≈ 3.75 V 40 kΩ D A ANA_IN1+ VREFTOP ANA_IN − ANA_IN2+ ADR_SEL GND DVSUP 23 kΩ 23 kΩ
PRELIMINARY DATA SHEET MSP 34x1G Micronas 61 Fig. 4–18:Input/Output Pins: I2C_CL, I2C_DA Fig. 4–19:Input/Output Pins: I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0 Fig. 4–20:Input/Output Pins: XTAL_IN, XTAL_OUT, AUD_CL_OUT Fig. 4–21:Output Pins: DACA_R/L, DACM_R/L, DACM_SUB Fig. 4–22:Output Pins: Fig. 4–23:Output Pins: I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL Fig. 4–24:Capacitor Pins: CAPL_A, CAPL_M Fig. 4–25:Pin 45: AGNDC N GND DVSUP P N GND 3−30 pF 2.5 V 500 kΩ 3−30 pF P N AHVSUP 0...1.2 mA 3.3 kΩ 26 pF 120 kΩ 300 Ω ≈ 3.75 V DVSUP P N GND 0...2 V ≈ 3.75 V 125 kΩ
MSP 34x1G PRELIMINARY DATA SHEET
62 Micronas
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Symbol Parameter Pin Name Min. Max. Unit TA Ambient Operating Temperature − 07 0 °C TS Storage Temperature −− 40 125 °C VSUP1 First Supply Voltage AHVSUP −0.3 9.0 V VSUP2 Second Supply Voltage DVSUP −0.3 6.0 V VSUP3 Third Supply Voltage AVSUP −0.3 6.0 V dVSUP23 Voltage between AVSUP and DVSUP AVSUP, DVSUP −0.5 0.5 V PTOT Power Dissipation PSDIP64 PSDIP52 PQFP80 PLQFP64 AHVSUP , DVSUP, AVSUP 1300 1200 1000 960 mW mW mW mW V Idig Input Voltage, all Digital Inputs −0.3 V SUP2 +0.3 V IIdig Input Current, all Digital Pins−− 20 +20 mA 1) VIana Input Voltage, all Analog Inputs SCn_IN_s,2) MONO_IN −0.3 V SUP1 +0.3 V IIana Input Current, all Analog Inputs SCn_IN_s,2) MONO_IN −5 +5m A 1) IOana Output Current, all SCART Outputs SCn_OUT_s2) 3) , 4) 3) , 4) IOana Output Current, all Analog Outputs except SCART Outputs DACp_s 2) 3) 3) ICana Output Current, other pins connected to capacitors CAPL_p,2) AGNDC 3) 3) 1) positive value means current flowing into the circuit 3) The analog outputs are short-circuit proof with respect to First Supply Voltage and ground. 4) Total chip power dissipation must not exceed absolute maximum rating.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 63 4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C) 4.6.2.1. General Recommended Operating Conditions 4.6.2.2. Analog Input and Output Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit VSUP1 First Supply Voltage (AHVSUP = 8 V) AHVSUP 7.6 8.0 8.7 V First Supply Voltage (AHVSUP = 5V) 4.75 5.0 5.25 V VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V tSTBYQ1 STANDBYQ Setup Time before Turn-off of Second Supply Voltage ST ANDBYQ, DVSUP 1 µs Symbol Parameter Pin Name Min. Typ. Max. Unit C AGNDC AGNDC-Filter-Capacitor AGNDC −20% 3.3 µF Ceramic Capacitor in Parallel −20% 100 nF C inSC DC-Decoupling Capacitor in front of SCART Inputs SCn_IN_s1) −20% 330 nF VinSC SCART Input Level 2.0 V RMS VinMONO Input Level, Mono Input MONO_IN 2.0 V RMS R LSC SCART Load Resistance SCn_OUT_s 1) 10 k Ω C LSC SCART Load Capacitance 6.0 nF C VMA Main/AUX Volume Capacitor CAPL_M, CAPL_A 10 µF C FMA Main/AUX Filter Capacitor DACM_s, DACA_s 1) −10% 1 +10% nF
MSP 34x1G PRELIMINARY DATA SHEET
64 Micronas
4.6.2.3. Recommendations for Analog Sound IF Input Signal Symbol Parameter Pin Name Min. Typ. Max. Unit C VREFTOP VREFTOP-Filter-Capacitor VREFTOP −20 % 10 µF Ceramic Capacitor in Parallel −20 % 100 nF FIF_FMTV Analog Input Frequency Range for TV Applications ANA_IN1 +, ANA_IN2 +, ANA_IN −
09 M H z
FIF_FMRADIO Analog Input Frequency for FM-Radio Applications
10.7 MHz
VIF_FM Analog Input Range FM/NICAM 0.1 0.8 3 V pp VIF_AM Analog Input Range AM/NICAM 0.1 0.45 0.8 V pp R FMNI Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: −20 −23 −10 dB dB R AMNI Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) −25 −11 0 dB R FM Ratio: FM-Main/FM-Sub Satellite 7 dB R FM1/FM2 Ratio: FM1/FM2 German FM-System 7d B R FC Ratio: Main FM Carrier/ Color Carrier 15 −− dB R FV Ratio: Main FM Carrier/ Luma Components 15 −− dB PR IF Passband Ripple −−± 2d B SUP HF Suppression of Spectrum above 9.0 MHz (not for FM Radio) 15 − dB FM MAX Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode ±180 ±360 ±540 kHz kHz kHz
PRELIMINARY DATA SHEET MSP 34x1G Micronas 65 4.6.2.4. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations f P Crystal Parallel Resonance Fre- quency at 12 pF Load Capacitance
18.432 MHz
R R Crystal Series Resistance 8 25 Ω C 0 Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF C L External Load Capacitance1) XTAL_IN, XTAL_OUT PSDIP approx. 1.5 P(L)QFP approx. 3.3 pF pF Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock) fTOL Accuracy of Adjustment −20 +20 ppm D TEM Frequency Variation versus Temperature −20 +20 ppm C 1 Motional (Dynamic) Capacitance 19 24 fF fCL Required Open Loop Clock Frequency (Tamb = 25°C) AUD_CL_OUT 18.431 18.433 MHz Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment −30 +30 ppm D TEM Frequency Variation versus Temperature −30 +30 ppm C 1 Motional (Dynamic) Capacitance 15 fF fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.4305 18.4335 MHz Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment −100 +100 ppm D TEM Frequency Variation versus Temperature −50 +50 ppm fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.429 18.435 MHz Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 V pp 1)External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre- quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB . The sug- To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the fre- quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
MSP 34x1G PRELIMINARY DATA SHEET
66 Micronas
4.6.3. Characteristics at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel 4.6.3.1. General Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Supply ISUP1A First Supply Current (active) (AHVSUP = 8 V) AHVSUP 17 mA mA Vol. Main and Aux = 0 dB Vol. Main and Aux = -30dB First Supply Current (active) (AHVSUP = 5 V) mA mA Vol. Main and Aux = 0 dB Vol. Main and Aux = -30 dB ISUP2A Second Supply Current (active) DVSUP 55 70 mA ISUP3A Third Supply Current (active) AVSUP 30 38 mA ISUP1S First Supply Current (AHVSUP = 8 V) AHVSUP 5.6 7.7 mA ST ANDBYQ = low First Supply Current (AHVSUP = 5 V) 3.7 5.1 mA Clock fCLOCK Clock Input Frequency XTAL_IN 18.432 MHz D CLOCK Clock High to Low Ratio 45 55 % tJITTER Clock Jitter (Verification not provided in Production Test) 50 ps VxtalDC DC-Voltage Oscillator 2.5 V tStartup Oscillator Startup Time at VDD Slew-rate of 1 V/1 µs XTAL_IN, XTAL_OUT 0.4 2 ms VACLKAC Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 V pp load = 40 pF VACLKDC Audio Clock Output DC Voltage 0.4 0.6 V SUP3 Imax = 0.2 mA routHF_ACL HF Output Resistance 140 Ω
PRELIMINARY DATA SHEET MSP 34x1G Micronas 67 4.6.3.2. Digital Inputs, Digital Outputs Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Digital Input Levels V DIGIL Digital Input Low Voltage STANDBYQ D_CTR_I/O_0/1
0.2 V SUP2
VDIGIH Digital Input High Voltage 0.5 V SUP2 ZDIGI Input Impedance 5 pF IDLEAK Digital Input Leakage Current −11 µA0 V < U INPUT < DVSUP D_CTR_I/O_0/1: tri-state VDIGIL Digital Input Low Voltage ADR_SEL 0.2 V SUP2 VDIGIH Digital Input High Voltage 0.8 V SUP2 IADRSEL Input Current Address Select Pin −500 −220 µAU ADR_SEL = DVSS 220 500 µAU ADR_SEL = DVSUP Digital Output Levels V DCTROL Digital Output Low Voltage D_CTR_I/O_0 D_CTR_I/O_1
0.4 V IDDCTR = 1 mA
VDCTROH Digital Output High Voltage V SUP2 −0.3 V IDDCTR = −1 mA
MSP 34x1G PRELIMINARY DATA SHEET
68 Micronas
4.6.3.3. Reset Input and Power-Up Fig. 4–26:Power-up sequence Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RESETQ Input Levels V RHL Reset High-Low Transition Voltage RESETQ 0.3 0.4 V SUP2 VRLH Reset Low-High Transition Voltage 0.45 0.55 V SUP2 ZRES Input Capacitance 5 pF IRES Input High Current 20 µAU RESETQ = DVSUP 4.5 V Internal Reset t/ms RESETQ AVSUP DVSUP High Low t/ms t/ms Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 0.45 x DVSUP means
2.25 Volt with
DVSUP = 5.0 V 0.45× DVSUP High-to-Low Threshold Low-to-High Threshold Reset Delay >2 ms
PRELIMINARY DATA SHEET MSP 34x1G Micronas 69 4.6.3.4. I2C-Bus Characteristics Fig. 4–27:I2C bus timing diagram Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VI2CIL I2C-Bus Input Low Voltage I2C_CL, I2C_DA
0.3 V SUP2
VI2CIH I2C-Bus Input High Voltage 0.6 V SUP2 tI2C1 I2C Start Condition Setup Time 120 ns tI2C2 I2C Stop Condition Setup Time 120 ns tI2C5 I2C-Data Setup Time before Rising Edge of Clock 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns tI2C3 I2C-Clock Low Pulse Time I2C_CL 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns fI2C I2C-BUS Frequency 1.0 MHz VI2COL I2C-Data Output Low Voltage I2C_CL, I2C_DA
0.4 V I I2COL = 3 mA
1.0 µAV I2COH = 5 V tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns f I2C = 1 MHz I2C_CL I2C_DA as input I2C_DA as output TI2C1 TI2C5 TI2C6 TI2C2 TI2C4 TI2C3 1/FI2C TI2COL2 TI2COL1
MSP 34x1G PRELIMINARY DATA SHEET
70 Micronas
4.6.3.5. I2S-Bus Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VI2SIL Input Low Voltage I2S_CL I2S_WS I2S_DA_IN1/2 0.2 V SUP2 VI2SIH Input High Voltage 0.5 V SUP2 ZI2SI Input Impedance 5 pF ILEAKI2S Input Leakage Current −11 µA0 V < U INPUT < DVSUP VI2SOL I2S Output Low Voltage I2S_CL I2S_WS I2S_DA_OUT
0.4 V I
I2SOL = 1 mA VI2SOH I2S Output High Voltage V SUP2 − 0.3 VI I2SOH = −1 mA fI2SOWS I2S-Word Strobe Output Frequency I2S_WS 32.0 kHz fI2SOCL I2S-Clock Output Frequency I2S_CL 1.024 2.048 MHz MHz I2S_CONFIG[0] = 0 I2S_CONFIG[0] = 1 R I2S10/I2S20 I2S-Clock Output High/Low-Ratio 0.9 1.0 1.1 ts_I2S I2S Input Setup Time before Rising Edge of Clock I2S_CL I2S_DA_IN1/2 12 ns for details see Fig. 4 –28 “I2S bus timing diagram” th_I2S I2S Input Hold Time after Rising Edge of Clock 40 ns td_I2S I2S Output Delay Time after Falling Edge of Clock I2S_CL I2S_WS I2S_DA_OUT 28 ns C L =3 0p F fI2SWS I2S-Word Strobe Input Frequency I2S_WS 32.0 kHz fI2SCL I2S-Clock Input Frequency I2S_CL 1.024 MHz R I2SCL I2S-Clock Input High/Low Ratio 0.9 1.1
PRELIMINARY DATA SHEET MSP 34x1G Micronas 71 Fig. 4–28:I2S bus timing diagram Data: MSB first, I2S master R LSB L LSB R LSB L LSB 16/32 bit right channel L LSB L LSB R MSB R MSB Detail C I2S_WS I2S_CL I2S_DA_IN Detail A MODUS[6] = 1 MODUS[6] = 0 Detail B R LSB R LSB L MSB L MSBI2S_DA_OUT 16/32 bit right channel16/32 bit left channel 16/32 bit left channel 1/FI2SWS I2S_CL Detail C I2S_WS as INPUT I2S_WS as OUTPUT 1/FI2SCL Ts_I2S Td_I2S Detail A,B I2S_CL I2S_DA_OUT Td_I2S Data: MSB first, I2S slave R LSB L LSB R LSB L LSB 16, 18...32 bit right channel L LSB L LSB R MSB R MSB Detail C I2S_WS I2S_CL I2S_DA_IN Detail A MODUS[6] = 1 MODUS[6] = 0 Detail B R LSB R LSB L MSB L MSBI2S_DA_OUT 16, 18...32 bit right channel 16, 18...32 bit left channel 16,18...32 bit left channel 1/FI2SWS Th_I2STs_I2S I2S_DA_IN1/2
MSP 34x1G PRELIMINARY DATA SHEET
72 Micronas
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Ground V AGNDC0 AGNDC Open Circuit Voltage (AHVSUP = 8 V) AGNDC 3.77 V R load ≥ 10 MΩ AGNDC Open Circuit Voltage (AHVSUP = 5 V) 2.51 V R outAGN AGNDC Output Resistance (AHVSUP = 8 V) 70 125 180 k Ω 3 V ≤ VAGNDC ≤ 4 V AGNDC Output Resistance (AHVSUP = 5 V) 47 83 120 k Ω Analog Input Resistance R inSC SCART Input Resistance from TA = 0 to 70 °C SCn_IN_s 1) 25 40 58 k Ω fsignal = 1 kHz, I = 0.05 mA R inMONO MONO Input Resistance from TA = 0 to 70 °C M O N O _ I N 1 52 43 5k Ω fsignal = 1 kHz, I = 0.1 mA Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for Analog-to-Digital- Conversion (AHVSUP = 8 V) SCn_IN_s, MONO_IN 2.00 2.25 V RMS fsignal = 1 kHz Analog Input Clipping Level for Analog-to-Digital- Conversion (AHVSUP = 5 V) 1.13 1.51 V RMS SCART Outputs R outSC SCART Output Resistance SCn_OUT_s 1) 200 200 330 460 500 Ω Ω fsignal = 1 kHz, I = 0.1 mA Tj = 27 °C TA = 0 to 70 °C dVOUTSC Deviation of DC-Level at SCART Output from AGNDC Voltage −70 +70 mV ASCtoSC Gain from Analog Input to SCART Output SCn_IN_s,1) MONO_IN SCn_OUT_s 1) −1.0 +0.5 dB f signal = 1 kHz frSCtoSC Frequency Response from Analog Input to SCART Output −0.5 +0.5 dB with resp. to 1 kHz Bandwidth: 0 to 20000 Hz VoutSC Signal Level at SCART Output (AHVSUP = 8 V) SCn_OUT_s 1) 1.8 1.9 2.0 V RMS fsignal = 1 kHz Volume 0 dB Full Scale input from I Signal Level at SCART Output (AHVSUP = 5V) 1.17 1.27 1.37 V RMS
PRELIMINARY DATA SHEET MSP 34x1G Micronas 73 4.6.3.7. Sound IF Inputs 4.6.3.8. Power Supply Rejection Main and AUX Outputs R outMA Main/AUX Output Resistance DACp_s 1) 2.1 2.1 3.3 4.6 5.0 kΩ kΩ fsignal = 1 kHz, I = 0.1 mA Tj = 27 °C TA = 0 to 70 °C VoutDCMA DC-Level at Main/AUX-Output (AHVSUP = 8 V) 1.80 2.04 2.28 V mV Volume 0 dB Volume −30 dB DC-Level at Main/AUX-Output (AHVSUP = 5 V) 1.12 1.36 1.60 V mV Volume 0 dB Volume −30 dB VoutMA Signal Level at Main/AUX-Output (AHVSUP = 8 V) 1.23 1.37 1.51 V RMS fsignal = 1 kHz Volume 0 dB Full scale input from I Signal Level at Main/AUX-Output (AHVSUP = 5 V) 0.76 0.90 1.04 V RMS Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions R IFIN Input Impedance ANA_IN1 +, ANA_IN2 +, ANA_IN − 1.5 6.8 9.1 2.5 11.4 kΩ kΩ Gain AGC = 20 dB Gain AGC = 3 dB DC VREFTOP DC Voltage at VREFTOP VREFTOP 2.45 2.65 2.75 V DC ANA_IN DC Voltage on IF Inputs ANA_IN1 +, ANA_IN2 +, ANA_IN − 1.3 1.5 1.7 V XT ALKIF Crosstalk Attenuation ANA_IN1 +, ANA_IN2 +, ANA_IN − 40 dB f signal = 1 MHz Input Level = −2 dBr BW IF 3 dB Bandwidth 10 MHz AGC AGC Step Width 0.85 dB Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC AGNDC 80 dB From Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 70 dB From Analog Input to SCART Output MONO_IN, SCn_IN_s 1) SCn_OUT_s 1) 70 dB From I2S Input to SCART Output SCn_OUT_s 1) 60 dB From I2S Input to MAIN or AUX Output DACp_s 1) 80 dB Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
MSP 34x1G PRELIMINARY DATA SHEET
74 Micronas
4.6.3.9. Analog Performance Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Specifications for AHVSUP = 8 V SNR Signal-to-Noise Ratio from Analog Input to I 2S Output MONO_IN, SCn_IN_s 1) 85 88 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s SCn_OUT_s 1) 93 96 dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 85 88 dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...16 kHz from I 2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB DACp_s dB dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...16 kHz THD Total Harmonic Distortion from Analog Input to I 2S Output MONO_IN, SCn_IN_s 1) 0.01 0.03 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s SCn_OUT_s 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz from I 2S Input to Main or AUX Out- put DACA_s, DACM_s 1) 0.01 0.03 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz
PRELIMINARY DATA SHEET MSP 34x1G Micronas 75 Specifications for AHVSUP = 5 V SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 82 85 dB Input Level = −20 dB with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s SCn_OUT_s 1) 90 93 dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 82 85 dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...16 kHz from I 2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at −30 dB DACp_s dB dB Input Level = −20 dB, fsig = 1 kHz, unweighted 20 Hz...16 kHz THD Total Harmonic Distortion from Analog Input to I 2S Output MONO_IN, SCn_IN_s 1) 0.03 0.1 % Input Level = −3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s SCn_OUT_s 0.1 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 0.1 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz from I 2S Input to Main or AUX Out- put DACA_s, DACM_s 1) 0.1 % Input Level = −3 dBr, fsig = 1 kHz, unweighted 20 Hz...16 kHz Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
MSP 34x1G PRELIMINARY DATA SHEET
76 Micronas
CROSSTALK Specifications for AHVSUP = 8 V and 5 V XTALK Crosstalk Attenuation − PLCC68 − PSDIP64 Input Level = −3 dB, fsig = 1 kHz, unused ana- log inputs connected to ground by Z < 1 kΩ between left and right channel within SCART Input/Output pair (L→ R, R→ L) SCn_IN → SCn_OUT 1) PLCC68 PSDIP64 SC1_IN or SC2_IN → I2S Output PLCC68 PSDIP64 SC3_IN → I2S Output PLCC68 PSDIP64 I2S Input → SCn_OUT 1) PLCC68 PSDIP64 dB dB dB dB dB dB dB dB unweighted 20 Hz...20 kHz between left and right channel within Main or AUX Output pair I2S Input → DACp1) PLCC68 PSDIP64 dB dB unweighted 20 Hz...16 kHz between SCART Input/Output pairs D = disturbing program O = observed program D: MONO/SCn_IN → SCn_OUT PLCC68 O: MONO/SCn_IN → SCn_OUT 1) PSDIP64 D: MONO/SCn_IN → SCn_OUT or unsel. PLCC68 O: MONO/SCn_IN → I2S Output PSDIP64 D: MONO/SCn_IN → SCn_OUT PLCC68 O: I2S Input → SCn_OUT 1) PSDIP64 D: MONO/SCn_IN → unselected PLCC68 O: I2S Input → SC1_OUT 1) PSDIP64 100 100 100 100 100 100 100 dB dB dB dB dB dB dB dB unweighted 20 Hz...20 kHz same signal source on left and right disturbing chan- nel, effect on each observed output channel Crosstalk between Main and AUX Output pairs I 2S Input → DACp1) PLCC68 PSDIP64 dB dB unweighted 20 Hz...16 kHz same signal source on left and right disturbing chan- nel, effect on each observed output channel XTALK Crosstalk from Main or AUX Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP → SCn_OUT PLCC68 O: I 2S Input → DACp 1) PSDIP64 D: MONO/SCn_IN/DSP → SCn_OUT PLCC68 O: I2S Input → DACp1) PSDIP64 D: I2S Input → DACp PLCC68 O: MONO/SCn_IN → SCn_OUT 1) PSDIP64 D: I2S Input → DACM PLCC68 O: I2S Input → SCn_OUT 1) PSDIP64 100 100 dB dB dB dB dB dB dB dB unweighted 20 Hz...20 kHz same signal source on left and right disturbing chan- nel, effect on each observed output channel SCART output load resis- tance 10 kΩ SCART output load resis- tance 30 kΩ Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 34x1G Micronas 77 4.6.3.10. Sound Standard Dependent Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions NICAM Characteristics (MSP Standard Code = 8) dV NICAMOUT Tolerance of Output Voltage of NICAM Baseband Signal DACp_s, SCn_OUT_s 1) −1.5 +1.5 dB 2.12 kHz, Modulator input level = 0 dBref S/NNICAM S/N of NICAM Baseband Signal 72 dB NICAM: −6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7F hex Output level 1 VRMS at DACp_s THD NICAM Total Harmonic Distortion + Noise of NICAM Baseband Signal 0.1 % 2.12 kHz, Modulator input level = 0 dBref BER NICAM NICAM: Bit Error Rate 1 10 −7 FM +NICAM, norm conditions fRNICAM NICAM Frequency Response , 20...15000 Hz −1.0 +1.0 dB Modulator input level = −12 dB dBref; RMS XT ALKNICAM NICAM Crosstalk Attenuation (Dual) 80 dB SEP NICAM NICAM Channel Separation (Stereo) 80 dB FM Characteristics (MSP Standard Code = 3) dVFMOUT Tolerance of Output Voltage of FM Demodulated Signal DACp_s, SCn_OUT_s 1) −1.5 +1.5 dB 1 FM-carrier, 50 µs, 1 kHz, 40 kHz deviation; RMS S/NFM S/N of FM Demodulated Signal 73 dB 1 FM-carrier 5.5 MHz, 50 µs, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Pres- cale = 46 hex, Vol = 0 dB → Output Level 1 VRMS at DACp_s THD FM Total Harmonic Distortion + Noise of FM Demodulated Signal 0.1 % fRFM FM Frequency Response 20...15000 Hz −1.0 +1.0 dB 1 FM-carrier 5.5 MHz, 50 µs, Modulator input level = −14.6 dBref; RMS XT ALKFM FM Crosstalk Attenuation (Dual) 80 dB 2 FM-carriers 5.5/5.74 MHz, 50 µs, 1 kHz, 40 kHz devia- tion; Bandpass 1 kHz SEP FM FM Channel Separation (Stereo) 50 dB 2 FM-carriers 5.5/5.74 MHz, 50 µs, 1 kHz, 40 kHz devia- tion; RMS AM Characteristics (MSP Standard Code = 9) S/NAM(1) S/N of AM Demodulated Signal measurement condition: RMS/Flat DACp_s, SCn_OUT_s 1) 55 dB SIF level: 0.1 −0.8 Vpp AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM prescaler set for output = 0.5 V RMS at Loudspeaker out; Standard Code = 09 hex no video/chroma components S/N AM(2) S/N of AM Demodulated Signal measurement condition: QP/CCIR 45 dB THD AM Total Harmonic Distortion + Noise of AM Demodulated Signal 0.6 % fRAM AM Frequency Response 50...12000 Hz −2.5 +1.0 dB
MSP 34x1G PRELIMINARY DATA SHEET
78 Micronas
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R or SAP , 100% modulation, 75µs deempha- sis, RMS unweighted 0 to 15 kHz THD BTSC THD +N of BTSC Stereo Signal THD +N of BTSC SAP Signal 0.1 0.5 1 kHz L or R or SAP , 100% 75 µs EIM2), DBX NR or MNR, RMS unweighted 0 to 15 kHz fR DBX Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP , 50 Hz...9 kHz −1.0 −1.0 1.0 1.0 dB dB L or R or SAP , 1%...66% EIM2), DBX NR fRMNR Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP , 50 Hz...9 kHz −2.0 2.0 dB SAP , white noise, 10% Modu- lation, MNR XTALK BTSC Stereo → SAP SAP → Stereo dB dB 1 kHz L or R or SAP , 100% modulation, 75µs deempha- sis, Bandpass 1 kHz SEP DBX Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz dB dB L or R 1%...66% EIM 2), DBX NR SEP MNR Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz 14% Modulation, MNR FM pil Pilot deviation threshold Stereo off → on Stereo on → off ANA_IN1+, ANA_IN2+ 3.2 1.2 3.5 1.5 kHz kHz
4.5 MHz carrier modulated
with fh = 15.734 kHz SIF level = 100 mVpp indication: STATUS Bit[6] fPilot Pilot Frequency Range 15.563 15.843 kHz standard BTSC stereo signal, sound carrier only 2) EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-µs preemphasis network. Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 34x1G Micronas 79 BTSC Characteristics (MSP Standard Code = 20hex, 21hex) with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R or SAP , 100% modulation, 75µs deempha- sis, RMS unweighted 0 to 15 kHz THD BTSC THD +N of BTSC Stereo Signal THD +N of BTSC SAP Signal 0.15 0.8 1 kHz L or R or SAP , 100% 75 µs EIM2), DBX NR or MNR, RMS unweighted 0 to 15 kHz fR DBX Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP , 50 Hz...9 kHz −1.0 −1.0 1.0 1.0 dB dB L or R or SAP , 1%...66% EIM2), DBX NR fRMNR Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP , 50 Hz...9 kHz −2.0 2.0 dB SAP , white noise, 10% Modu- lation, MNR XT ALKBTSC Stereo → SAP SAP → Stereo dB dB 1 kHz L or R or SAP , 100% modulation, 75µs deempha- sis, Bandpass 1 kHz SEP DBX Stereo Separation DBX NR 50 Hz...10 kHz 50 Hz...12 kHz dB dB L or R 1%...66% EIM 2), DBX NR SEP MNR Stereo Separation MNR 30 dB L = 300 Hz, R = 3.1 kHz 14% Modulation, MNR 2) EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-µs preemphasis network. Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
MSP 34x1G PRELIMINARY DATA SHEET
80 Micronas
EIA-J Characteristics (MSP Standard Code = 30hex) S/NEIAJ S/N of EIA-J Stereo Signal S/N of EIA-J Sub-Channel DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R, 100% modulation, 75 µs deemphasis, RMS unweighted 0 to 15 kHzTHD EIAJ THD +N of EIA-J Stereo Signal THD +N of EIA-J Sub-Channel 0.2 0.3 fREIAJ Frequency Response of EIA-J Stereo, 50 Hz...12 kHz Frequency Response of EIA-J Sub-Channel, 50 Hz...12 kHz −0.5 −1.0 0.5 0.5 dB dB 100% modulation, 75 µs deemphasis XTALK EIAJ Main → SUB Sub → MAIN dB dB 1 kHz L or R, 100% modula- tion, 75µs deemphasis, Bandpass 1 kHz SEP EIAJ Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz dB dB EIA-J Stereo Signal, L or R 100% modulation FM-Radio Characteristics (MSP Standard Code = 40 hex) S/NUKW S/N of FM-Radio Stereo Signal DACp_s, SCn_OUT_s 1) 68 dB 1 kHz L or R, 100% modula- tion, 75µs deemphasis, RMS unweighted 0 to 15 kHz THD UKW THD +N of FM-Radio Stereo Signal 0.1 % fRUKW Frequency Response of FM-Radio Stereo L or R, 1%...100% modula- tion, 75µs deemphasis SEP UKW Stereo Separation 50 Hz...15 kHz 45 dB fPilot Pilot Frequency Range ANA_IN1+ ANA_IN2+ 18.844 19.125 kHz standard FM radio stereo signal Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 34x1G Micronas 81 5. Appendix A: Overview of TV-Sound Standards 5.1. NICAM 728 Table 5–1:Summary of NICAM 728 sound modulation parameters Specification I B/G L D/K Carrier frequency of digital sound 6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz Transmission rate 728 kbit/s Type of modulation Differentially encoded quadrature phase shift keying (DQPSK) Spectrum shaping Roll-off factor by means of Roll-off filters 1.0 0.4 0.4 0.4 Carrier frequency of analog sound component
6.0 MHz
5.5 MHz
6.5 MHz AM mono 6.5 MHz FM mono terrestrial cable Power ratio between vision carrier and analog sound carrier 10 dB 13 dB 10 dB 16 dB 13 dB Power ratio between analog and modulated digital sound carrier 10 dB 7 dB 17 dB 11 dB China/ Hungary Poland 12 dB 7 dB Table 5–2:Summary of NICAM 728 sound coding characteristics Characteristics Values Audio sampling frequency 32 kHz Number of channels 2 Initial resolution 14 bit/sample Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks Coding for compressed samples 2 ’s complement Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
MSP 34x1G PRELIMINARY DATA SHEET
82 Micronas
5.2. A2-Systems Table 5–3:Key parameters for A2 Systems of Standards B/G, D/K, and M Characteristics Sound Carrier FM1 Sound Carrier FM2 TV-Sound Standard B/G D/K M B/G D/K M 6.7421875 5.7421875 4.724212 Vision/sound power difference 13 dB 20 dB Sound bandwidth 40 Hz to 15 kHz Preemphasis 50 µs7 5 µs5 0 µs7 5 µs Frequency deviation (nom/max) ±27/±50 kHz ±17/±25 kHz ±27/±50 kHz ±15/±25 kHz Transmission Modes Mono transmission mono mono Stereo transmission (L +R)/2 (L +R)/2 R (L −R)/2 Dual sound transmission language A language B Identification of Transmission Mode Pilot carrier frequency 54.6875 kHz 55.0699 kHz Max. deviation portion ±2.5 kHz Type of modulation / modulation depth AM / 50% Modulation frequency mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz
PRELIMINARY DATA SHEET MSP 34x1G Micronas 83 5.3. BTSC-Sound System 5.4. Japanese FM Stereo System (EIA-J) Table 5–4:Key parameters for BTSC-Sound Systems Aural Carrier BTSC-MPX-Components (L+R) Pilot (L−R) SAP Prof. Ch. Carrier frequency (fhNTSC = 15.734 kHz) (fhPAL = 15.625 kHz) 4.5 MHz Baseband f h 2 fh 5 fh 6.5 fh Preemphasis 75 µs DBX DBX 150 µs Max. deviation to Aural Carrier 73 kHz (total) 25 kHz1) 5k H z 5 0k H z 1) 15 kHz 3 kHz Max. Freq. Deviation of Subcarrier Modulation Type AM 10 kHz FM 3k H z FM 1) Sum does not exceed 50 kHz due to interleaving effects Table 5–5:Key parameters for Japanese FM-Stereo Sound System EIA-J Aural Carrier FM EIA-J-MPX-Components (L+R) (L−R) Identification Carrier frequency (fh = 15.734 kHz) 4.5 MHz Baseband 2 f h 3.5 fh Sound bandwidth 0.05 - 15 kHz 0.05 - 15 kHz − Preemphasis 75 µs7 5 µs none Max. deviation portion to Aural Carrier 47 kHz 25 kHz 20 kHz 2 kHz Max. Freq. Deviation of Subcarrier Modulation Type 10 kHz FM 60% AM Transmitter-sided delay 20 µs0 µs0 µs Mono transmission L +R − unmodulated Stereo transmission L +RL −R 982.5 Hz Bilingual transmission Language A Language B 922.5 Hz
MSP 34x1G PRELIMINARY DATA SHEET
84 Micronas
5.5. FM Satellite Sound 5.6. FM-Stereo Radio Table 5–6:Key parameters for FM Satellite Sound Carrier Frequency Maximum FM Deviation Sound Mode Bandwidth Deemphasis
6.5 MHz 85 kHz Mono 15 kHz 50 µs
7.02/7.20 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.38/7.56 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.74/7.92 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive Table 5–7:Key parameters for FM-Stereo Radio Systems Aural Carrier FM-Radio-MPX-Components (L+R) Pilot (L−R) RDS/ARI Carrier frequency (fp = 19 kHz) 10.7 MHz Baseband f p 2 fp 3 fh Sound bandwidth in kHz 0.05 - 15 0.05 - 15 Preemphasis: − USA − Europe 75 µs 50 µs 75 µs 50 µs Max. deviation to Aural Carrier 75 kHz (100%) 90% 10% 90% 5%
PRELIMINARY DATA SHEET MSP 34x1G Micronas 85 6. Appendix B: Manual/Compatibility Mode To adapt the modes of the STANDARD SELECT regis- ter to individual requirements and for reasons of com- patibility to the MSP 34x0D, the MSP 34x1G offers an Manual/Compatibility Mode, which provides sophis- ticated programming of the MSP 34x1G. Using the STANDARD SELECT register generally pro- vides a more economic way to program the MSP 34x1G and will result in optimal behavior. There- fore, it is not recommend to use the Manual/Com- patibility mode. In those cases, where the MSP 34xxD is to be substituted by the MSP 34x1G, the tips given in Section 6.10. on page 101 have to be obeyed by the controller software. 6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode Table 6–1:Demodulator Write Registers; Subaddress: 10 hex; these registers are not readable! Demodulator Write Registers Address (hex) MSP- Version Description Reset Mode Page AUTO_FM/AM 00 21 3411, 3451 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 00 00 87 A2_Threshold 00 22 all A2 Stereo Identification Threshold 00 19 hex 89 CM_Threshold 00 24 all Carrier-Mute Threshold 00 2A hex 89 AD_CV 00 BB all SIF-input selection, configuration of AGC, and Carrier-Mute Function 00 00 90 MODE_REG 00 83 3411, 3451 Controlling of MSP-Demodulator and Interface options. As soon as this register is applied, the MSP 34x1G works in the MSP 34x0D Compatibility Mode. Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x1G is reset to the normal mode by first programming the MODUS register followed by transmitting a valid standard code to the STANDARD SELECTION register. 00 00 91 FIR1 FIR2 00 01 00 05 FIR1-filter coefficients channel 1 (6 ⋅ 8 bit) FIR2-filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit) 00 00 93 DCO1_LO DCO1_HI DCO2_LO DCO2_HI 00 93 00 9B 00 A3 00 AB Increment channel 1 Low Part Increment channel 1 High Part Increment channel 2 Low Part Increment channel 2 High Part 00 00 93 PLL_CAPS 00 1F Not of interest for the customer Switchable PLL capacitors to tune open-loop frequency 00 56 96 Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
MSP 34x1G PRELIMINARY DATA SHEET
86 Micronas
6.2. DSP Write and Read Registers for Manual/Compatibility Mode Table 6–2:Demodulator Read Registers; Subaddress: 11hex; these registers are not writable! Demodulator Read Registers Address (hex) MSP- Version Description Page C_AD_BITS 00 23 3411, 3451 NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits 95 ADD_BITS 00 38 NICAM: bit[10:3] of additional data bits 95 CIB_BITS 00 3E NICAM: CIB1 and CIB2 control bits 95 ERROR_RATE 00 57 NICAM error rate, updated with 182 ms 96 PLL_CAPS 02 1F Not for customer use 96 AGC_GAIN 02 1E Not for customer use 96 Table 6–3:DSP-Write Registers; Subaddress: 12hex, all registers are readable as well Write Register Address (hex) Bits Operational Modes and Adjustable Range Reset Mode Page Volume SCART1 channel: Ctrl. mode 00 07 [7:0] [Linear mode / logarithmic mode] 00 hex 97 FM Fixed Deemphasis 00 0F [15:8] [50 µs, 75µs, J17, OFF] 50 µs9 7 FM Adaptive Deemphasis [7:0] [OFF , WP1] OFF 97 Identification Mode 00 15 [7:0] [B/G, M] B/G 98 FM DC Notch 00 17 [7:0] [ON, OFF] ON 98 Volume SCART2 channel: Ctrl. mode 00 40 [7:0] [Linear mode / logarithmic mode] 00 hex 97 Table 6–4:DSP Read Registers; Subaddress: 13hex, all registers are not writable Additional Read Registers Address (hex) Bits Output Range Page Stereo detection register for A2 Stereo Systems 00 18 [15:8] [80 hex ... 7Fhex] 8 bit two ’s complement 98 DC level readout FM1/Ch2-L 00 1B [15:0] [8000 hex ... 7FFFhex] 16 bit two ’s complement 98 DC level readout FM2/Ch1-R 00 1C [15:0] [8000 hex ... 7FFFhex] 16 bit two ’s complement 98
PRELIMINARY DATA SHEET MSP 34x1G Micronas 87 6.3. Manual/Compatibility Mode: Description of Demodulator Write Registers 6.3.1. Automatic Switching between NICAM and Analog Sound In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 34x1G offers an Automatic Switching (fall back) to the analog sound (FM/AM- mono), without the necessity for the controller of reading and evaluating any parameters. If a proper NICAM sig- nal returns, switching back to this source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM-source, to the analog source, and vice versa. An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11] (Addr: 0023 hex) provide information about the actual NICAM-FM/AM-status. Fig. 6–1:Hysteresis for Automatic Switching 6.3.1.1. Function in Automatic Sound Select Mode The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700 dec. i.e.: – NICAM → analog Sound if ERROR_RATE > 700 – analog Sound → NICAM if ERROR_RATE < 700/2 The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10-3 /s. Individual configuration of the threshold can be done using Table 6–5. However, the internal setting used by the standard selection is recommended. The optimum NICAM sound can be assigned to the MSP output channels by selecting one of the “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source chan- nels 6.3.1.2. Function in Manual Mode If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6–6. Note, that the channel matrix of the corresponding out- put-channels must be set according to the NICAM-mode and need not to be changed in the FM/ AM-fallback case. Example: Required threshold = 500: bits[10:1] = 00 1111 1010 ERROR_RA TE Selected Sound NICAM analog sound thresholdthreshold/2 Table 6–5:Coding of Automatic NICAM/Analog Sound Switching; Automatic Sound Select is on (MODUS[0] = 1) Mode Description AUTO_FM [11:0] Addr. = 00 21hex ERROR_RATE- Threshold/dec Source Select: Input at NICAM Path Default Automatic Switching with internal threshold bit[11:0] = 0 700 NICAM or FM/AM, depending on ERROR_RATE
2 Automatic Switching with
(Customizing of Automatic Sound Select) bit[11] = 0 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000
3 Forced Analog Mono bit[11] = 1
bit[10:1] = ignored bit[0] = 1 always FM/AM 1) The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels (see Table 2–2 on page 12).
MSP 34x1G PRELIMINARY DATA SHEET
88 Micronas
Table 6–6:Coding of Automatic NICAM/Analog Sound Switching; Automatic Sound Select is off (MODUS[0] = 0) Mode Description AUTO_FM [11:0] Addr. = 00 21hex ERROR_RATE- Threshold/dec Source Select: Input at NICAM Path reset status Forced NICAM (Automatic Switching disabled) bit[11] = 0 bit[10:1] = 0 bit[0] = 0 none always NICAM; Mute in case of no NICAM available
1 Automatic Switching with
(Default, if Automatic Sound Select is on) bit[11] = 0 bit[10:1] = 0 bit[0] = 1
700 NICAM or FM/AM,
ERROR_RA TE (Customizing of Automatic Sound Select) bit[11] = 0 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000
3 Forced Analog Mono
(Automatic Switching disabled) bit[11] = 1 bit[10:1] = 0 bit[0] = 1 none always FM/AM
PRELIMINARY DATA SHEET MSP 34x1G Micronas 89 6.3.2. A2 Threshold The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard has been made pro- grammable according to the user’s preferences. An internal hysteresis ensures robustness and stability. 6.3.3. Carrier-Mute Threshold The Carrier-Mute threshold has been made program- mable according to the user’s preferences. An internal hysteresis ensures stable behavior. Table 6–7:Write Register on I2C Subaddress 10hex : A2 Threshold Register Address Function Name THRESHOLDS 00 22hex (write) A2 THRESHOLD Register Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection bit[15:0] 07F0hex force Mono Identification ... 0190 hex default setting after reset ... 00A0 hex minimum Threshold for stable detection recommended range : 00A0hex...03C0hex A2_THRESH Table 6–8:Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold Register Address Function Name THRESHOLDS 00 24hex (write) Carrier-Mute THRESHOLD Register Defines threshold for the carrier mute feature bit[15:0] 0000hex Carrier-Mute always ON (both channels muted) ... 002A hex default setting after reset ... 07FF hex Carrier-Mute always OFF (both channels forced on) recommended range : 0014hex...0050hex CM_THRESH
MSP 34x1G PRELIMINARY DATA SHEET
90 Micronas
6.3.4. Register AD_CV The use of this register is no longer recommended. Use it only in cases where compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS regis- ter provides a more economic way to program the MSP 34x1G. Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on. Table 6–9:AD_CV Register; reset status: all bits are “0” AD_CV (00 BBhex) Automatic setting by STANDARD SELECT Register Bit Function Settings 2-8, 0A-60hex 9 [0] not used must be set to 0 0 0 [1:6] Reference level in case of Automatic Gain Control = on (see T able 6–10). Constant gain factor when Automatic Gain Control = off (see Table 6–11). 101000 100011 [7] Determination of Automatic Gain or Constant Gain 0 = constant gain 1 = automatic gain [8] Selection of Sound IF source (identical to MODUS[8]) 0 = ANA_IN1+ 1 = ANA_IN2+ XX [9] MSP-Carrier-Mute Feature 0 = off: no mute 1 = on: mute as de- scribed in section 2.2.2. [10:15] not used must be set to 0 0 0 X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register Table 6–10:Reference Values for Active AGC (AD_CV[7] = 1) Application Input Signal Contains AD_CV [6:1] Ref. Value AD_CV [6:1] in integer Range of Input Signal at pin ANA_IN1+ and ANA_IN2 + Terrestrial TV − FM Standards − NICAM/FM − NICAM/AM − NICAM only 1 or 2 FM Carriers
1 FM and 1 NICAM Carrier
1 AM and 1 NICAM Carrier
1 NICAM Carrier only
0.10 − 3 V pp 0.10 − 3 Vpp 0.10 − 1.4 Vpp (recommended: 0.10 − 0.8 Vpp) 0.05 − 1.0 Vpp SAT 1 or more FM Carriers 100011 35 0.10 − 3 Vpp ADR FM and ADR carriers see DRP 3510A data sheet 1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
PRELIMINARY DATA SHEET MSP 34x1G Micronas 91 6.3.5. Register MODE_REG Note: The use of this register is no longer recom- mended. It should be used only in cases where soft- ware compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. As soon as this register is applied, the MSP 34x1G works in the MSP 34x0D Manual/Compatibility Mode . In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only MSP 34x0D features are available; the use of MODUS and STATUS register is not allowed. The MSP 34x1G is reset to the normal mode by first programming the MODUS register, followed by trans- mitting a valid standard code to the STANDARD SELECTION register. The register ‘MODE_REG ’ contains the control bits determining the operation mode of the MSP 34x1G in the MSP 34x0D Manual/Compatibility Mode; Table 6– 12 explains all bit positions. Table 6–11: AD_CV parameters for Constant Input Gain (AD_CV[7]=0) Step AD_CV [6:1] Constant Gain Gain Input Level at pin ANA_IN1+ and ANA_IN2+ 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 3.00 dB 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB maximum input level: 3 V pp (FM) or 1 Vpp (NICAM)1) maximum input level: 0.14 Vpp 1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.
MSP 34x1G PRELIMINARY DATA SHEET
92 Micronas
Table 6–12: Control word ‘MODE_REG ’; reset status: all bits are “0” MODE_REG 00 83 hex Automatic setting by STANDARD SELECT Register Bit Function Comment Definition 2 - 5 8, A, B 9 [0] not used 0 : must be used 0 0 0 [1] DCTR_TRI Digital control out 0/1 tri-state 0 : active 1 : tri-state XXX [2] I2S_TRI I 2S outputs tri-state (I2S_CL, I2S_WS, I2S_DA_OUT) 0 : active 1 : tri-state XXX [3] I 2S Mode1) Master/Slave mode of the I2S bus 0 : Master 1 : Slave XXX [4] I2S_WS Mode WS due to the Sony or Philips-Format 0 : Sony 1 : Philips XXX [5] Audio_CL_OUT Switch Audio_Clock_Output to tri-state 0 : on 1 : tri-state XXX [6] NICAM 1) Mode of MSP-Ch1 0 : FM 1 : Nicam 011 [7] not used 0 : must be used 0 0 0 [8] FM AM Mode of MSP-Ch2 0 : FM 1 : AM 001 [9] HDEV High Deviation Mode (channel matrix must be sound A) 0 : normal 1 : high deviation mode 000 [11:10] not used 0 : must be used 0 0 0 [12] MSP-Ch1 Gain see also Table 6 –14 0 : Gain = 6 dB 1 : Gain = 0 dB 000 [13] FIR1-Filter Coeff. Set see also Table 6–14 0 : use FIR1 1 : use FIR2 100 [14] ADR Mode of MSP-Ch1/ ADR-Interface 0 : normal mode/tri-state 1 : ADR-mode/active 000 [15] AM-Gain Gain for AM Demodulation 0 : 0 dB (default. of MSPB) 1 :12 dB (recommended) 111 1) NICAM and I2S-Master mode are not allowed simultaneously X: not affected by STANDARD SELECT Register
PRELIMINARY DATA SHEET MSP 34x1G Micronas 93 6.3.6. FIR-Parameter, Registers FIR1 and FIR2 Note: The use of this register is no longer recom- mended. It should be used only in cases where soft- ware compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. Data-shaping and/or FM/AM bandwidth limitation is performed by a pair of linear phase Finite Impulse Response filters (FIR-filter). The filter coefficients are programmable and are either configured automatically by the STANDARD SELECT register or written manu- ally by the control processor via the control bus. Two not necessarily different sets of coefficients are required: one for MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In Table 6–14 several coefficient sets are proposed. To load the FIR-filters, the following data values are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word. The loading sequences must be obeyed. To change a coefficient set, the complete block FIR1 or FIR2 must be transmitted. Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04 hex, 40hex, and 00hex arise. 6.3.7. DCO-Registers Note: The use of this register is no longer recom- mended. It should be used only in cases where soft- ware-compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the MODUS register provides a more economic way to program the MSP 34x1G. When selecting a TV-sound standard by means of the STANDARD SELECT register, all frequency tuning is performed automatically. If manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequen- cies of the quadrature mixers can be written manually into the IC. In Table 6–15, some examples of DCO reg- isters are listed. It is necessary to divide them up into low part and high part. The formula for the calculation of the registers for any chosen IF frequency is as fol- lows: INCR dec = int(f/fs ⋅ 224) with: int = integer function f = IF frequency in MHz fS = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required regis- ter values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI or LO for MSP-Ch2). Table 6–13: Loading sequence for FIR-coefficients FIR1 00 01hex (MSP-Ch1: NICAM/FM2) No. Symbol Name Bits Value 1 NICAM/FM2_Coeff. (5) 8 see Table 6–14 2 NICAM/FM2_Coeff. (4) 8 3 NICAM/FM2_Coeff. (3) 8 4 NICAM/FM2_Coeff. (2) 8 5 NICAM/FM2_Coeff. (1) 8 6 NICAM/FM2_Coeff. (0) 8 FIR2 00 05hex (MSP-Ch2: FM1/AM) No. Symbol Name Bits Value 1I M R E G 1 8 0 4 hex 2I M R E G 1 / I M R E G 2 8 4 0 hex 3I M R E G 2 8 0 0 hex
4 FM/AM_Coef (5) 8
see Table 6–14
5 FM/AM_Coef (4) 8
6 FM/AM_Coef (3) 8
7 FM/AM_Coef (2) 8
8 FM/AM_Coef (1) 8
9 FM/AM_Coef (0) 8
MSP 34x1G PRELIMINARY DATA SHEET
94 Micronas
Table 6–14: 8-bit FIR-coefficients (decimal integer); reset status: all coefficients are “0” Coefficients for FIR1 00 01hex and FIR2 00 05hex Terrestrial TV Standards B/G-, D/K- NICAM-FM NICAM-FM NICAM-AM B/G-, D/K-, M-Dual FM 130 kHz 180 kHz 200 kHz 280 kHz 380 kHz 500 kHz Auto- search Coef(i) FIR1 FIR2 FIR1 FIR2 FIR1 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 1 −81 8 41 8 −8 −12 18 53 18 18 −8 −9 −1 −1 2 −10 27 −62 7 −10 −9 2 7 6 42 82 7 4 −16 −8 −8 3 10 48 −4 48 10 23 48 119 47 48 36 5 2 2 4 50 66 40 66 50 79 66 101 55 66 78 65 59 59 5 86 72 94 72 86 126 72 127 64 72 107 123 126 126 Mode- REG[12] 0 0 0 0 111111 0 Mode- REG[13] 0 0 0 1 111111 0 For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet. Table 6–15: DCO registers for the MSP 34x1G; reset status: DCO_HI/LO = “0000” DCO1_LO 00 93 hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex Freq. MHz DCO_HI/hex DCO_LO/hex Freq. MHz DCO_HI/hex DCO_LO/hex 4.5 03E8 000 5.04 5.5 5.58 5.7421875 0460 04C6 04D8 04FC 0000 038E 0000 00AA 5.76 5.85 5.94 0500 0514 0528 0000 0000 0000 6.0 6.2 6.5 6.552 0535 0561 05A4 05B0 0555 0C71 071C 0000 6.6 6.65 6.8 05BA 05C5 05E7 0AAA 0C71 01C7 7.02 0618 0000 7.2 0640 0000 7.38 0668 0000 7.56 0690 0000 B FM - Satellite FIR filter corresponds to a band-pass with a band- width of B = 130 to 500 kHz f c frequency
PRELIMINARY DATA SHEET MSP 34x1G Micronas 95 6.4. Manual/Compatibility Mode: Description of Demodulator Read Registers Note: The use of these register is no longer recom- mended. It should be used only in cases where soft- ware compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 34x1G and to retrieve infor- mation from the IC. All registers except C_AD_BITs are 8 bits wide. They can be read out of the RAM of the MSP 34x1G if the MSP 34x0D Compatibility Mode is required. All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word. If the Automatic Sound Select feature is not used, the NICAM or FM-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are described in section 6.6.1. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Addi- tional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS. 6.4.1. NICAM Mode Control/Additional Data Bits Register NICAM operation mode control bits and A[2:0] of the additional data bits. Format: Important: “S” = Bit[0] indicates correct NICAM-syn- chronization (S = 1). If S = 0, the MSP 3411/3451G has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP mutes the NICAM output automatically and tries to synchro- nize again as long as MODE_REG[6] is set. The operation mode is coded by C4-C1 as shown in Table 6–16. Note: It is no longer necessary to read out and evalu- ate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register. 6.4.2. Additional Data Bits Register Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format: 6.4.3. CIB Bits Register CIB bits 1 and 2 (see NICAM 728 specifications). Format: MSB C_AD_BITS 00 23hex LSB 1 1 . . .76543210 Auto _FM ... A[2] A[1] A[0] C4 C3 C2 C1 S Table 6–16: NICAM operation modes as defined by the EBU NICAM 728 specification C4 C3 C2 C1 Operation Mode 0 0 0 0 Stereo sound (NICAMA/B), independent mono sound (FM1) 0 0 0 1 Two independent mono signals (NICAMA, FM1) 0 0 1 0 Three independent mono channels (NICAMA, NICAMB, FM1) 0 0 1 1 Data transmission only; no audio 1 0 0 0 Stereo sound (NICAMA/B), FM1 carries same channel 1 0 0 1 One mono signal (NICAMA). FM1 carries same channel as NICAMA 1 0 1 0 Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA 1 0 1 1 Data transmission only; no audio x 1 x x Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification) AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM MSB ADD_BITS 00 38hex LSB 76543210 MSB CIB_BITS 00 3Ehex LSB 76543210 xxxxxx C I B 1 C I B 2
MSP 34x1G PRELIMINARY DATA SHEET
96 Micronas
6.4.4. NICAM Error Rate Register Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The ini- tial and maximum value of ERROR_RATE is 2047. This value is also active if the NICAM bit of MODE_REG is not set. Since the value is achieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700 int. Individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from NICAM to FM/ AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10 −6 /s 6.4.5. PLL_CAPS Readback Register It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer. 6.4.6. AGC_GAIN Readback Register It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the cus- tomer. 6.4.7. Automatic Search Function for FM-Carrier Detection in Satellite Mode The AM demodulation ability of the MSP 34x1G offers the possibility to calculate the “field strength” of the momentarily selected FM carrier, which can be read out by the controller. In SAT receivers, this feature can be used to make automatic FM carrier search possi- ble. For this, the MSP has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to hex = +127dec, and the FM DC notch (see section 6.5.7.) must be switched off. The sound-IF frequency range must now be “scanned” in the MSP-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the controller. This results in either continuing search or switching the MSP back to FM demodulation mode. During the search process, the FIR2 must be loaded with the coefficient set “AUTOSEARCH ”, which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of “quasi-peak detector output FM1 ”) also gives information on whether a main FM carrier or a subcarrier was detected; and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 µs or adaptive) can be switched accordingly. Due to the fact that a constant demodulation frequency offset of a few kHz leads to a DC level in the demodu- lated signal, further fine tuning of the found carrier can be achieved by evaluating the “DC Level Readout FM1 ”. Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode. For a detailed description of the automatic search function, please refer to the corresponding MSP Win- dows software. ERROR_RATE 00 57hex Error free 0000 hex maximum error rate 07FF hex PLL_CAPS 02 1Fhex L minimum frequency 1111 1111 FF hex nominal frequency 0101 0110 56 hex RESET maximum frequency 0000 0000 00 hex PLL_CAPS 02 1Fhex H PLL open xxxx xxx0 PLL closed xxxx xxx1 AGC_GAIN 02 1Ehex max. amplification (20 dB) 0001 0100 14 hex min. amplification (3 dB) 0000 0000 00 hex
PRELIMINARY DATA SHEET MSP 34x1G Micronas 97 6.5. Manual/Compatibility Mode: Description of DSP Write Registers 6.5.1. Additional Channel Matrix Modes This table shows additional modes for the channel matrix registers. The sum/difference mode can be used together with the quasi-peak detector to determine the sound mate- rial mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. 6.5.2. Volume Modes of SCART1/2 Outputs Note: SCART Volume linear mode will not be sup- ported in the future (documented for compatibility rea- sons only). 6.5.3. FM Fixed Deemphasis Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto- matic Sound Select (MODUS[0]=1) is on. 6.5.4. FM Adaptive Deemphasis Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto- matic Sound Select (MODUS[0]=1) is on. Loudspeaker Matrix 00 08hex L Headphone Matrix 00 09hex L SCART1 Matrix 00 0Ahex L SCART2 Matrix 00 41hex L I2S Matrix 00 0Bhex L Quasi-Peak Detector Matrix 00 0Chex L SUM/DIFF 0100 0000 40 hex AB_XCHANGE 0101 0000 50 hex PHASE_CHANGE_B 0110 0000 60 hex PHASE_CHANGE_A 0111 0000 70 hex A_ONL Y 1000 0000 80 hex B_ONL Y 1001 0000 90 hex Volume Mode SCART1 00 07hex [3:0] Volume Mode SCART2 00 40hex [3:0] linear 0000 0 hex RESET logarithmic 0001 1 hex Linear Mode Volume SCART1 00 07hex H Volume SCART2 00 40hex H OFF 0000 0000 00 hex RESET 0d B g a i n (digital full scale (FS) to 2 V RMS output) 0100 0000 40 hex +6 dB gain (−6 dBFS to 2 VRMS output) 0111 1111 7F hex FM Deemphasis 00 0Fhex H 50 µs 0000 0000 00 hex RESET 75 µs 0000 0001 01 hex J17 0000 0100 04 hex OFF 0011 1111 3F hex FM Adaptive Deemphasis WP1 00 0Fhex L OFF 0000 0000 00 hex RESET WP1 0011 1111 3F hex
MSP 34x1G PRELIMINARY DATA SHEET
98 Micronas
6.5.5. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable. 6.5.6. Identification Mode for A2 Stereo Systems To shorten the response time of the identification algo- rithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Set identification mode back to standard B/G or M 4. Wait approx. 500 ms 5. Read stereo detection register Note: This register is initialized during STANDARD SELECTION and is automatically updated when Auto- matic Sound Select (MODUS[0]=1) is on. 6.5.7. FM DC Notch The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see Section 6.4.7.). In nor- mal FM-mode, the FM DC Notch should be switched on. 6.6. Manual/Compatibility Mode: Description of DSP Read Registers All readable registers are 16-bit wide. Transmissions via I 2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable. 6.6.1. Stereo Detection Register for A2 Stereo Systems Note: It is no longer necessary to read out and evalu- ate the A2 identification level. All evaluation is per- formed in the MSP and indicated in the STATUS regis- ter. 6.6.2. DC Level Register The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant τ, defining the transition time of the DC Level Register, is approximately 28 ms. Identification Mode 00 15hex L Standard B/G (German Stereo) 0000 0000 00 hex RESET Standard M (Korean Stereo) 0000 0001 01 hex Reset of Ident-Filter 0011 1111 3F hex FM DC Notch 00 17hex L ON 0000 0000 00 hex Reset OFF 0011 1111 3F hex Stereo Detection Register 00 18hex H Stereo Mode Reading (two’s complement) MONO near zero STEREO positive value (ideal reception: 7F hex) BILINGUAL negative value (ideal reception: 80hex) DC Level Readout FM1 (MSP-Ch2) 00 1Bhex H +L DC Level Readout FM2 (MSP-Ch1) 00 1Chex H +L DC Level [8000 hex ... 7FFFhex] values are 16 bit two’s complement
PRELIMINARY DATA SHEET MSP 34x1G Micronas 99 6.7. Demodulator Source Channels in Manual Mode 6.7.1. Terrestric Sound Standards Table 6–17 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestric sound standards. See Table 2–2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestric sound standards, only two demodulator sources are defined. 6.7.2. SAT Sound Standards Table 6–18 shows the source channel assignment of the demodulated signals for SAT sound standards. Table 6–17:Manual Sound Select Mode for Terrestric Sound Standards Source Channels of Sound Select Block Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM Matrix FM/AM (use 0 for channel select) Stereo or A/B (use 1 for channel select) B/G-FM D/K-FM M-Korea M-Japan 04, 05 MONO Sound A Mono Mono Mono STEREO German Stereo Korean Stereo Stereo Stereo BILINGUAL, Languages A and B No Matrix Left = A Right = B Left = A Right = B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) NICAM not available or NICAM error rate too high Sound A Mono 1) analog Mono no sound with AUTO_FM: analog Mono MONO Sound A Mono 1) analog Mono NICAM Mono STEREO Sound A Mono 1) analog Mono NICAM Stereo BILINGUAL, Languages A and B Sound A Mono1) analog Mono Left = NICAM A Right = NICAM B BTSC MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo MONO + SAP Sound A Mono Mono Mono STEREO + SAP Korean Stereo Stereo Stereo MONO Sound A Mono Mono Mono STEREO MONO + SAP No Matrix Left = Mono Right = SAP Left = Mono Right = SAPSTEREO + SAP FM-Radio 40 MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo 1) Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!
MSP 34x1G PRELIMINARY DATA SHEET
100 Micronas
Table 6–18:Manual Sound Select Modes for SAT-Standards Source Channels of Sound Select Block for SAT-Modes Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM Matrix FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) FM SAT 6, 50hex MONO Sound A Mono Mono Mono Mono Mono 51hex STEREO No Matrix Stereo Stereo Stereo Stereo BILINGUAL No Matrix Left = A (FM1) Right = B (FM2) Left = A (FM1) Right = B (FM2) A (FM1) B (FM2)
PRELIMINARY DATA SHEET MSP 34x1G Micronas 101 6.8. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with the FM2 channel. 2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification. 6.9. Phase Relationship of Analog Outputs The analog output signals: Loudspeaker, headphone, and SCART2 all have the same phases. The user does not need to correct output phases when using these analog outputs directly. The SCART1 output has opposite phase. Using the I 2S-outputs for other DSPs or D/A convert- ers, care must be taken to adjust for the correct phase. If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship. 6.10. Compatibility Restrictions to MSP 34xxD The MSP 34x1G is fully hardware compatible to the MSP 34xxD. However, to substitute a MSP 34xxD by the corresponding MSP 34x1G, the controller software has to be adapted slightly: 1. The register FM-Matrix (00 0E hex low part) must be changed from “no matrix (00hex)” to “sound A mono (03hex)” during mono transmission of all TV-sound standards (see also Table 6–17). 2. With the MSP 34x1G, the STANDARD SELECTION initializes the FM-deemphasis, which is not the case for the MSP 34xxD. So, if STANDARD SELECTION is applied, this I 2C instruction can be omitted. Fig. 6–2:Phase diagram of the MSP 34x1G SCART2-Ch. SCART1 SCART1 SCART2 SCART4 SCART3 MONO Loudspeaker Audio SCART DSP Input Select SCART Output Select Baseband Processing Headphone SCART1-Ch. SCART2 I2S_OUT1/2I2S_IN1/2 MONO, SCART1...4
MSP 34x1G PRELIMINARY DATA SHEET
102 Micronas
- Appendix D: MSP 34x1G Version History MSP 3451G-A1 First release MSP 3451G-A2 – CONTROL register now readable for more status information – new D/K standard for Poland – improved I2C hardware problem handling – improved AM-performance MSP 34x1G-B8 – fine-tuning of A2-identification and carrier mute – EIA-J identification: faster transition time stereo/ bilingual to mono – J17 FM-deemphasis implemented – input specification for RESETQ and TESTEN changed – MDB implemented
PRELIMINARY DATA SHEET MSP 34x1G Micronas 103 8. Appendix E: Application Circuit SC1_OUT_L SC1_OUT_R SC2_OUT_L SC2_OUT_R AHVSUP AHVSS AVSUP DVSUP DVSS RESETQ AVSS VREF1 VREF2
5 V 5 V 8 V
CAPL_M CAPL_A VREFTOP AGNDC ANA_IN1+ ANA_IN2+ ANA_IN − XTAL_IN XTAL_OUT MSP 34x1G D_CTR_I/O_0 D_CTR_I/O_1 AUD_CL_OUT TESTEN 100 Ω 100 Ω 100 Ω 100 Ω 22 µF 22 µF 22 µF 22 µF DACA_R 1 nF 1 nF 1 nF 1 nF 1 nF DACA_L DACM_SUB DACM_R DACM_L 1 µF 1 µF 1 µF 1 µF 1 µF HEAD PHONE LOUD Tuner 1 Tuner 2 SIF 2 IN Signal GND SIF 1 IN 56 pF 56 pF 56 pF + 3.3 µF 100 nF 100 nF µF if ANA_IN2+ not used 8V ( 5V ) 18.432 MHz 10 µF1 0 µF MONO_IN SC1_IN_L SC1_IN_R ASG SC2_IN_L SC2_IN_R ASG SC3_IN_L SC3_IN_R ASG SC4_IN_L SC4_IN_R STANDBYQ ADR_SEL I2C_DA I2C_CL ADR_WS ADR_CL ADR_DA I2S_WS I2S_CL I2S_DA_IN1 I2S_DA_IN2 I2S_DA_OUT 220 pF Alternative circuit for SIF-inputs for more attenuation of video 100 pF 56 pF 1 kΩ ANA_IN1/2+ AHVSS AHVSS AHVSS 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF DVSS DVSS AHVSS components: C s. section 4.6.2. SPEAKER RESETQ nF 470 pF µF 1.5 nF 470 pF µF 1.5 nF 470 pF µF (5 V) AHVSS AHVSS AHVSS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. MSP 34x1G PRELIMINARY DATA SHEET
104 Micronas
D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-511-2PD 9. Data Sheet History 1. Preliminary data sheet: “MSP 34x1G Multistandard Sound Processor Family with Virtual Dolby Surround”, Edition Oct. 15, 1999, 6251-511-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: “MSP 34x1G Multistandard Sound Processor Family with Virtual Dolby Surround”, Jan. 19, 2001, 6251-511-2PD. Second release of the preliminary data sheet. Major changes: – specification for version B8 added (see Appendix D: Version History) – MSP 3461 added, MSP 3431 removed – description for MDB added – specification for MNR added – I2C-bus description changed – ACB register: documentation for bit allocation D_CTR_I/O changed