MS51BA2AE

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Feb. 25, 2021 1 of 81 Rev 1.02 MS51 SERIES DATASHEET 1T 8051 8-bit Microcontroller NuMicro® Family MS51 Series MS51EB0AE MS51FC0AE MS51XC0BE MS51EC0AE MS51TC0AE MS51PC0AE Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com

Feb. 25, 2021 2 of 81 Rev 1.02 MS51 SERIES DATASHEET TABLE OF CONTENTS

4.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /

4.2 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /

5.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /

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6.10 Inter-Integrated Circuit (I

8.3.2 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics

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Feb. 25, 2021 6 of 81 Rev 1.02 MS51 SERIES DATASHEET LIST OF TABLES

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1 GENERAL DESCRIPTION

The MS51 is an embedded Flash type, 8 -bit high performance 1T 8051 -based microcontroller. The instruction set is fully compatible with the standard 80C51 and performance enhanced. The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE contains a 32 Kbytes and MS51EB0AE contains a 16 Kbytes of main Flash called APROM, in which the contents of User Code resides. The MS51 Flash supports In -Application-Programming (IAP) function, which enables on-chip firmware updates. IAP also makes it possible to configure any block of User Code array to be used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction. There is an additional Flash called LDROM, in which the Boot Code normally resides for carrying out In-System-Programming (ISP). The LDROM size is configurable with a maximum of 4 Kbytes. To facilitate programming and verification, the Flash allows to be programmed and read electronically by parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for security. The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE provides rich peripherals including 256 bytes of SRAM, 2 Kbytes of auxiliary RAM (XRAM), Up to 29 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-bit auto-reload Timer3 for general purpose or baud rate generator, two UAR Ts with frame error detection and automatic address recognition, three ISO 7816 -3 interfaces, one SPI, one I 2C, six basic PWM output channels, six enhanced PWM output channels, eight-channel shared pin interrupt for all I/O, and one 12-bit ADC. The peripherals are equipped with 24 sources with 4-level-priority interrupts capability. The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE series is equipped with three clock sources and supports switching on -the-fly via software. The three clock sources include external clock input, 10 kHz internal oscillator, and one 16 MHz internal precise oscillator that is factory trimmed t o ±1% at room temperature. The MS51 provides additional power monitoring detection such as power -on reset and 4-level brown-out detection , which stabilizes the power-on/off sequence for a high reliability system design. The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE microcontroller operation consumes a very low power with two economic power modes to reduce power consumption － Idle and Power-down mode, which are software selectable. Idle mode turns off the CPU clock but allows continuing peripheral operation. Power -down mode stops the whole system clock for minimum power consumption. The system c lock of the MS51 can also be slowed down by software clock divider, which allows for a flexibility between execution performance and power consumption. With high performance CPU core and rich well-designed peripherals, the MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE benefits to meet a general purpose, home appliances, or motor control system accomplishment.

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2 FEATURES

 Fully static design 8 -bit high performance 1T 8051 -based CMOS microcontroller.  Instruction set fully compatible with MCS-51.  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs). Power on Reset (POR)  POR with 1.15V threshold voltage level Brown-out Detector (BOD)  4-level selection, with b rown-out interrupt and reset option . Low Voltage Reset (LVR)  LVR with 2.0V threshold voltage level Security  96-bit Unique ID (UID)  128-bit Unique Customer ID (UCID)  128-bytes security protection memory SPROM Memories Flash  Up to 32 KBytes of APROM for User Code.  4/3/2/1 Kbytes of Flash for loader (LDROM) c onfigure from APROM for In-System-Programmable (ISP)  Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-Programmable (IAP) means whole APROM can be use as Data Flash  An additional 128 bytes security protection memory SPROM  Code lock for security by CONFIG SRAM  256 Bytes on-chip RAM.  Additional 2 KBytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction. Clocks External Clock Source  4~24 MHz High -speed external crystal oscillator (HXT) for precise timing operation Internal Clock Source  Default 16 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.  Selectable 24 MHz high-speed internal oscillator (HIRC).

Feb. 25, 2021 9 of 81 Rev 1.02 MS51 SERIES DATASHEET  10 kHz low-speed internal oscillator (LIRC) calibrating to ±1% by software from high-speed internal oscillator Timers 16-bit Timer  Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer2 with three-channel input capture module and 9 input pin can be selected.  One 16-bit auto-reload Timer3, which can be the baud rate clock source of UART0 and UART1. Watchdog  6-bit free running up counter for WDT time-out interval.  Selectable time-out interval is 6.40 ms ~ 1.638s since WDT_CLK = 10 kHz (LIRC).  Able to wake up from Power-down or Idle mode  Interrupt or reset selectable on watchdog time-out Wake-up Timer  16-bit free running up counter for time-out interval.  Clock sources from LIRC  Able self Wake-up wake up from Power-down or Idle mode, and auto reload count value.  Supports Interrupt PWM  Up To 12 output pins can be selected  Supports maximum clock source frequency up to 24 MHz  Supports up to Three PWM modules, each module provides 6 output channels.  Supports independent mode for PWM output  Supports complementary mode for 3 complementary paired PWM output channels  Dead-time insertion with 8-bit resolution  Supports 16-bit resolution PWM counter  Supports mask function and tri-state enable for each PWM pin  Supports brake function  Supports trigger ADC on the following events Analog Interfaces Analog-to-Digital Converter (ADC)  Analog input voltage range: 0 ~ AVDD.  12-bit resolution and 10-bit accuracy is guaranteed.  Up to 8 single-end analog input channels  1 internal channels, they are band-gap voltage (VBG).  Maximum ADC peripheral clock frequency is 1 MHz.

Feb. 25, 2021 10 of 81 Rev 1.02 MS51 SERIES DATASHEET  Up to 500 KSPS sampling rate.  Software Write 1 to ADCS bit.  External pin (STADC) trigger  PWM trigger.  Support continues convert function auto store the A/D conversion result in XRAM. Communication Interfaces UART  Supports up to 2 UARTs: UART0, UART1,  Up to three sets ISO 7816-3 device configuration as UART  UART baud rate clock from HIRC or HXT.  Full-duplex asynchronous communications  Programmable 9th bit.  TXD and RXD pins of UART0 exchangeable via software. I2C  1 sets of I2C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  7-bit addressing mode  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  Supports hold time programmable SPI  1 sets of SPI devices  Supports Master or Slave mode operation  Supports MSB first or LSB first transfer sequence  slave mode up to 12 MHz ISO-7816  Up to three sets ISO 7816-3 device  Supports ISO 7816-3 compliant T=0, T=1  Supports full-duplex UART mode. GPIO  Four I/O modes:  Quasi-bidirectional mode  Push-Pull Output mode  Open-Drain Output mode  Input only with high impendence mode  Schmitt trigger input / TTL mode selectable.  Each I/O pin configured as interrupt source with edge/level trigger setting

Feb. 25, 2021 11 of 81 Rev 1.02 MS51 SERIES DATASHEET  Supports high drive and high sink current I/O  I/O pin internal pull-up or pull-down resistor enabled in input mode.  Maximum I/O Speed is 24 MHz  Enabling the pin interrupt function will also enable the wake- up function ESD & EFT ESD  HBM pass 8 kV EFT  > ± 4.4 kV Latch-up  150 mA pass

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3 PARTS INFORMATION

3.1 MS51 Series Package Type

MSOP10 TSSOP14 TSSOP20 QFN20 TSSOP28 LQFP32 QFN33 Part No. MS51BA9AE MS51DA9AE MS51FB9AE MS51FC0AE MS51XB9AE MS51XB9BE MS51XC0BE MS51EC0AE MS51EB0AE MS51PC0AE MS51TC0AE

3.2 MS51 Series Selection Gude

Flash (KB) SRAM (KB) LDROM (KB) [1] I/O Timer PWM Connectivity ADC(12-Bit) Package ISO 7816-3 [2] UART SPI I2C MS51BA9AE 8 1 4 8 4 5 - 2 - 1 5-ch MSOP10 MS51DA9AE 8 1 4 12 4 5 - 2 1 1 8-ch TSSOP14 MS51XB9AE 16 1 4 18 4 6 - 2 1 1 8-ch QFN20[3] MS51XB9BE 16 1 4 18 4 6 - 2 1 1 8-ch QFN20[3] MS51FB9AE 16 1 4 18 4 6 - 2 1 1 8-ch TSSOP20 MS51EB0AE 16 2 4 26 4 11 3 2 1 1 15-ch TSSOP28 MS51FC0AE 32 2 4 18 4 11 2 2 1 1 10-ch TSSOP20 MS51XC0BE 32 2 4 18 4 8 2 2 1 1 10-ch QFN20 MS51EC0AE 32 2 4 26 4 11 3 2 1 1 15-ch TSSOP28 MS51PC0AE 32 2 4 30 4 12 3 2 1 1 15-ch LQFP32 MS51TC0AE 32 2 4 30 4 12 3 2 1 1 15-ch QFN33 Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as UART function, GPIO defined as UART2 ~ UART4. 3. Detailed package information please refer to MS51FB9AE / MS51XB9AE / MS51XB9BE series document. 4. This document is only for MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE products.

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3.3 MS51 Series Selection Code

Core Line Package Flash SRAM Reserve Temperature 1T 8051 Industry 51: Base B: MSOP10 (3x3 mm) D: TSSOP14 (4.4x5.0 mm) E: TSSOP28 (4.4x9.7 mm) F: TSSOP20 (4.4x6.5 mm) I: SOP8 (4x5 mm) O: SOP20 (300 mil) P: LQFP32 (7x7 mm) T: QFN33 (4x4 mm) U: SOP28 (300 mil) X: QFN20 (3x3mm) A: 8 KB B: 16 KB C: 32 KB 0: 2 KB 1: 4 KB 2: 8/12 KB 3: 16 KB 6: 32 KB 8: 64 KB 9: 1 KB A: 96 KB E:-40 ~ 105°C

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4 PIN CONFIGURATION

Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool - PinConfigure contains all Nuvoton NuMicro ® Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. MS51PC0AE Multi Function Pin Diagram

4.1.1 QFN 33-pin Package Pin Diagram

Corresponding Part Number: MS51TC0AE QFN33

33 VSS

PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3 UART1_RXD / I2C0_SCL / ICE_CLK / P0.2 PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 UART0_TXD / ADC_CH3 / P0.6 UART0_RXD / ADC_CH2 / P0.7 UART3_RXD / PWM3_CH1 / P3.4 nRESET / P2.0 SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0 SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7 VSS UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 VDD PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5 P2.1 / ADC_CH9 / PWM2_CH0 P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD P2.4 / ADC_CH12 / T0 P1.3 / STADC / I2C0_SCL / ADC_CH13 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1 P3.6 / UART1_RXD P3.7 / UART1_TXD P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P3.2 / PWM3_CH0 P3.1 / PWM2_CH1 P3.5 / SPI0_SS Top transparent view Figure 4.1-1 Pin Assignment of LQFP-32 Package

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4.1.2 LQFP 32-pin Package Pin Diagram

Corresponding Part Number: MS51PC0AE LQFP32 nRESET / P2.0 SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0 SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7 VSS UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 VDD PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5 P2.1 / ADC_CH9 / PWM2_CH0 P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD P2.4 / ADC_CH12 / T0 P1.3 / STADC / I2C0_SCL / ADC_CH13 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1 P3.6 / UART1_RXD P3.7 / UART1_TXD P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P3.2 / PWM3_CH0 P3.1 / PWM2_CH1 P3.5 / SPI0_SS PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3 UART1_RXD / I2C0_SCL / ICE_CLK / P0.2 PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 UART0_TXD / ADC_CH3 / P0.6 UART0_RXD / ADC_CH2 / P0.7 UART3_RXD / PWM3_CH1 / P3.4 Figure 4.1-2 Pin Assignment of LQFP-32 Package

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4.1.3 TSSOP 28-pin Package Pin Diagram

Corresponding Part Number: MS51EC0AE TSSOP28 VSS UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 VDD PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5 PWM1_CH1 / ADC_CH14 / PWM0_BRAKE / I2C0_SDA / PWM0_CH1 / P1.4 ADC_CH13 / I2C0_SCL / STADC / P1.3 T0 / ADC_CH12 / P2.4 UART4_TXD / PWM1_CH0 / ADC_CH11 / P2.3 UART4_RXD / PWM1_CH1 / ADC_CH10 / P2.2 PWM2_CH0 / ADC_CH9 / P2.1 SPI0_SS / P3.5 PWM1_CH0 / UART3_TXD / IC0 / PWM0_CH0 / P1.2 PWM1_CH1 / UART3_RXD / PWM0_CH1 / IC1 / CLKO / ADC_CH7 / P1.1 P1.7 / ADC_CH0 / INT1 / UART2_RXD / SPI0_CLK P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI P2.0 / nRESET P3.4 / PWM3_CH1 / UART3_RXD P0.7 / ADC_CH2 / UART0_RXD P0.6 / ADC_CH3 / UART0_TXD P0.5 / ADC_CH4 / IC6 / PWM0_CH2 / T0 / UART3_TXD / PWM2_CH0 P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1 P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1 P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD P3.3 / PWM0_CH0 / CLKO / PWM0_BRAKE P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 Figure 4.1-3 Pin Assignment of TSSOP28 Package

4.1.4 TSSOP 20-pin Package Pin Diagram

Corresponding Part Number: MS51FC0AE TSSOP20 PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 UART0_TXD / ADC_CH3 / P0.6 UART0_RXD / ADC_CH2 / P0.7 nRESET / P2.0 SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0 SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7 VSS UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 VDD PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5 P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1 P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1 P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P1.3 / STADC / I2C0_SCL / ADC_CH13 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1 Figure 4.1-4 Pin Assignment of TSSOP20 Package

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4.1.5 QFN 20-pin Package Pin Diagram

Corresponding Part Number: MS51XC0BE QFN20 PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3 PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4 PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5 UART0_TXD / ADC_CH3 / P0.6 UART0_RXD / ADC_CH2 / P0.7 nRESET / P2.0 SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0 SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7 VSS UART1_TXD / I2C0_SDA / ICE_DAT / P1.6 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P1.3 / STADC / I2C0_SCL / ADC_CH13 P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1 P1.5 / PWM0_CH5 / SPI0_SS / IC7 / UART3_TXD / PWM3_CH1 VDD P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 Top transparent view Figure 4.1-5 Pin Assignment of QFN20 Package

Feb. 25, 2021 18 of 81 Rev 1.02 MS51 SERIES DATASHEET Symbol Multi-Function Description[1] MS51XC0BE QFN 20 MS51FC0AE TSSOP20 MS51EC0AE TSSOP28 MS51PC0AE LQFP 32 MS51TC0AE QFN 33 6 9 3 6 VDD Supply voltage VDD for operation. 4 7 1 4 VSS Ground potential. 13 16 16 23 P0.0 Port 0 bit 0. PWM0_CH3 PWM0 output channel 3. PWM2_CH1 PWM2 output channel 1. IC3 Input capture channel 3. SPI0_MOSI SPI master output/slave input. UART1_RXD UART1 receive input. XT1_IN External 4~24 MHz (high speed) crystal input pin. OSCIN If the EXTEN[1:0] = 10b, OSCIN is the external clock input pin. T1 External count input to Timer/Counter 1 or its toggle output. 14 17 17 24 P0.1 Port 0 bit 1. PWM0_CH4 PWM0 output channel 4. PWM3_CH0 PWM3 output channel 0. IC4 Input capture channel 4. SPI0_MISO SPI master input/slave output. XT1_OUT External 4~24 MHz (high speed) crystal output pin. 15 18 19 26 P0.2 Port 0 bit 2. I2C0_SCL I C clock. UART1_RXD UART1 receive input. ICE_CLK ICE / ICP clock input. 16 19 20 27 P0.3 Port 0 bit 3. ADC_CH6 ADC input channel 6. PWM0_CH5 PWM0 output channel5 PWM3_CH1 PWM3 output channel1 IC5 Input capture channel 5. UART2_TXD UART2 transmit data output. SC0_CLK Smart Card 0 clock pin 17 20 21 28 P0.4 Port 0 bit 4. ADC_CH5 ADC input channel 5. PWM0_CH3 PWM0 output channel 3. PWM2_CH1 PWM2 output channel 1. IC3 Input capture channel 3. UART2_RXD UART2 receive input. SC0_DAT Smart Card 0 data pin STADC External start ADC trigger 18 1 22 29 P0.5 Port 0 bit 5. ADC_CH4 ADC input channel 4. PWM0_CH2 PWM0 output channel 2. PWM2_CH0 PWM2 output channel 0. IC6 Input capture channel 6. UART3_TXD UART3 transmit data output. SC1_CLK Smart card clock pin. T0 External count input to Timer/Counter 0 or its toggle output. 19 2 23 30 P0.6 Port 0 bit 6.

Feb. 25, 2021 19 of 81 Rev 1.02 MS51 SERIES DATASHEET Pin Number Symbol Multi-Function Description[1] MS51XC0BE QFN 20 MS51FC0AE TSSOP20 MS51EC0AE TSSOP28 MS51PC0AE LQFP 32 MS51TC0AE QFN 33 ADC_CH3 ADC input channel 3. UART0_TXD UART0 transmit data output. 20 3 24 31 P0.7 Port 0 bit 7. ADC_CH2 ADC input channel 2. UART0_RXD UART0 transmit data output. 12 15 15 22 P1.0 Port 1 bit 0. PWM0_CH2 PWM0 output channel 2. PWM2_CH0 PWM2 output channel 0. IC2 Input capture channel 2. SPI0_CLK SPI0 clock. UART1_TXD UART1 receive input. 11 14 14 21 P1.1 Port 1 bit 1 ADC_CH7 ADC input channel 7. PWM0_CH1 PWM0 output channel 1. PWM1_CH1 PWM1 output channel 1. IC1 Input capture channel 1. UART3_RXD UART3 receive input. SC1_DAT Smart Card 1 data pin. CLKO System clock output. 10 13 13 20 P1.2 Port 1 bit 2. PWM0_CH0 PWM0 output channel 0. PWM1_CH0 PWM1 output channel 0. IC0 Input capture channel 0. UART3_TXD UART3 transmit data output. SC1_CLK Smart Card 1 clock pin. 9 12 7 12 P1.3 Port 1 bit 3. ADC_CH13 ADC input channel 13. I2C0_SCL I C0 clock. STADC External start ADC trigger 8 11 6 11 P1.4 Port 1 bit 4. ADC_CH14 ADC input channel 14. PWM0_CH1 PWM0 output channel 1. PWM1_CH1 PWM1 output channel 1. I2C0_SDA I C0 data. PWM0_BRAKE PWM0 Fault Brake input. 7 10 4 7 P1.5 Port 1 bit 5. PWM0_CH5 PWM0 output channel 5. PWM3_CH1 PWM3 output channel 1. IC7 Input capture channel 7. SPI0_SS SPI0 slave select input. UART3_TXD UART3 transmit data output. SC1_CLK Smart card 2 clock pin 5 8 2 5 P1.6 Port 1 bit 6. I2C0_SDA I C0 data. UART1_TXD UART1 transmit data output. ICE_DAT ICE data input or output. 3 6 28 3 P1.7 Port 1 bit 7. ADC_CH0 ADC input channel 0. PWM3_CH0 PWM3 output channel 0. SPI0_CLK SPI0 clock. UART2_RXD UART2 receive input. SC0_DAT Smart Card 0 data pin

Feb. 25, 2021 20 of 81 Rev 1.02 MS51 SERIES DATASHEET Pin Number Symbol Multi-Function Description[1] MS51XC0BE QFN 20 MS51FC0AE TSSOP20 MS51EC0AE TSSOP28 MS51PC0AE LQFP 32 MS51TC0AE QFN 33 INT1 External interrupt 1 input. 1 4 26 1 P2.0 Port 2 bit 0 input pin available when RPD (CONFIG0.2) is programmed as 0. nRESET It is a Schmitt trigger input pin for hardware device reset. A low on this pin resets the device. nRESET pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to VSS. - - 11 16 P2.1 Port 2 bit 1. ADC_CH9 ADC input channel 9. PWM2_CH0 PWM2 output channel 0. - - 10 15 P2.2 Port 2 bit 2. ADC_CH10 ADC input channel 10. PWM1_CH1 PWM1 output channel 1. UART4_RXD UART4 receive input. SC2_DAT6 Smart card 2 data pin - - 9 14 P2.3 Port 2 bit 3. ADC_CH11 ADC input channel 11. PWM1_CH0 PWM1 output channel 0. UART4_TXD UART4 transmit data output. SC2_CLK6 Smart card 2 clock pin - - 8 13 P2.4 Port 2 bit 4. ADC_CH12 ADC input channel 12. T0 External count input to Timer/Counter 0 or its toggle output. - - 5 8 P2.5 Port 2 bit 5. ADC_CH15 ADC input channel 15. SPI0_MISO SPI master input/slave output. UART3_RXD UART3 receive input. SC1_DAT6 Smart card 1 data pin 2 5 27 2 P3.0 Port 3 bit 0. ADC_CH1 ADC input channel 1. PWM2_CH1 PWM2 output channel 1. PI0_MOSI SPI master output/slave input. UART2_TXD UART2 transmit data output. SC0_CLK6 Smart card 0 clock pin INT0 External interrupt 0 input. OSCIN If the EXTEN[1:0] = 11b, OSCIN is the external clock input pin. - - - 18 P3.1 Port 3 bit 1. PWM2_CH1 PWM2 output channel 1. - - - 19 P3.2 Port 3 bit 2. PWM3_CH0 PWM3 output channel 0. - - 18 25 P3.3 Port 3 bit 3. PWM0_CH0 PWM3 output channel 0. CLK_OUT System clock output. PWM0_BRAKE PWM0 Fault Brake input. - - 25 32 P3.4 Port 3 bit 4. PWM3_CH1 PWM3 output channel 0. UART3_RXD UART3 receive input. SC1_DAT Smart card 0 data pin - - 12 17 P3.5 Port 3 bit 5. SPI0_SS SPI0 slave select input.

Feb. 25, 2021 21 of 81 Rev 1.02 MS51 SERIES DATASHEET Pin Number Symbol Multi-Function Description[1] MS51XC0BE QFN 20 MS51FC0AE TSSOP20 MS51EC0AE TSSOP28 MS51PC0AE LQFP 32 MS51TC0AE QFN 33 - - - 9 P3.6 Port 3 bit 6. UART1_TXD UART1 transmit data output. - - - 10 P3.7 Port 3 bit 7. UART1_RXD UART1 receive input. Note: 1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description. 2. UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX (AUXR1.2). 3. [I2C] alternate function remapping option. I2C pins is software switched by I2CPX (I2CON.0). 4. [STADC] alternate function remapping option. STADC pin is software switched by STADCPX(ADCCON1.6). 5. PIOx register decides which pins are PWM or GPIO. 6. UART2_TXD and UART2_RXD pin is defined by AUXR2 register. UART3_TXD, UART3_RXD, UART4_TXD and UART4_RXD pin defined by AUXR3 register.

Feb. 25, 2021 22 of 81 Rev 1.02 MS51 SERIES DATASHEET

5 BLOCK DIAGRAM

Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline of the device. User can find all the peripheral functions of the device in the diagram. 1T High Performance

8051 Core

(UART 0/1) Timer 0/1 POR / LVR / BOD I2C0 I2C0_SDA I2C0_SCL VDD VSS Timer 2 with Input Capture FB0 SPI0 12-bit ADC Self Wake-up Timer Timer 3 UART2/3/4 (ISO 7816-3 port) 8-bit Internal Bus AIN0~7, 9~15 STADC UART2/3/4_TX UART2/3/4_RX UART0/1_RX UART0/1_TX SPI0_MOSI SPI0_SS SPI0_SCK SPI0_MISO ICAP0~2

32 KB APROM

Max. 4KB LDROM Flash Max. Bytes Data Flash (page: 128B) Clock Divider 16/24 MHz Internal RC Oscillator (HIRC) System Clock 4-24 MHz Oscillator Circuit (HXT) XIN XOUT 256 bytes Internal RAM P1[7:0] 8 8P3[7:0] P0P0[7:0] 8 P2[5:0] 6 Any Port 8 GPIO Interrupt External InterruptINT0 INT1

2 Kbytes XRAM

(Auxiliary RAM) PWM0CH0~5 Memory Access GPIO Analog Peripheral System Clock Source Digital Peripheral Power Management

6 PWM1/2/3CH0~1

(LIRC) Figure 5.1-1 Functional Block Diagram

Feb. 25, 2021 23 of 81 Rev 1.02 MS51 SERIES DATASHEET

6 FUNCTIONAL DESCRIPTION

6.1 Memory Organization

6.1.1 Overview

A standard 80C51 based microcontroller divides the memory into two different sections, Program Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to store data or variations during the program execution. The Data Memory occupies a separate address space from Program Memory. In MS51, there are 256 bytes of internal scratch -pad RAM. For many applications those need more internal RAM, the MS51 provides another on-chip 2 Kbytes of RAM, which is called XRAM, accessed by MOVX instruction. The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG bytes for hardware initialization. Actually, APROM and LDROM funct ion in the same way but have different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O pins, In -Application-Programming (IAP), or In -System-Programming (ISP) can both perform these modes.

Feb. 25, 2021 24 of 81 Rev 1.02 MS51 SERIES DATASHEET

6.2 Flash Memory Control

6.2.1 Reset

The MS51 has several options to place device in reset condition. It also offers the software flags to indicate the source, which causes a reset. In g eneral, most SFR go to their Reset value irrespective of the reset condition, but there are several reset source indicating flags whose state depends on the source of reset. User can read back these flags to determine the cause of reset using software. The re are five ways of putting the device into reset state. They are power -on reset, brown-out reset, external reset, WDT reset, and software reset. Power-On Reset (POR) and Low Voltage Reset (LVR) The MS51 incorporates an internal power -on reset (POR) and a low voltage reset (LVR) . During a power-on process of rising power supply voltage VDD, the POR or LVR will hold the MCU in reset mode when VDD is lower than the voltage reference threshold s. This design makes CPU not access program Flash while the VDD is not adequate performing the Flash reading. If an undetermined operating code is read from the program Flash and executed, this will put CPU and even the whole system in to an erroneous state. After a while, V DD rises above the threshold where the system can work, the selected oscillator will start and then program code will execute from 0000H. At the same time, a power -on flag POF (PCON.4) will be set 1 to indicate a cold reset, a power-on process complete. Note that the contents of internal RAM will be undetermined after a power-on. It is recommended that user gives initial values for the RAM block. The POF is recommended to be cleared to 0 via software to check if a cold reset or warm reset performed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1 again. If the reset is a warm reset caused by other reset sources, POF will remain 0. User may take a different course to check other reset flags and deal with the warm reset event. For detailed electrical characteristics, refer to the table 35-7 and 35-8. PCON – Power Control Register SFR Address Reset Value PCON 87H, All pages POR: 0001_0000b Others: 000U _0000b 7 6 5 4 3 2 1 0 SMOD SMOD0 LPR POF GF1 GF0 PD IDL R/W R/W RW R/W R/W R/W R/W R/W Bit Name Description

4 POF Power-on reset flag

This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-on reset complete. This bit remains its value after any other resets. This flag is recommended to be cleared via software. Brown-Out Reset The brown-out detection circuit is used for monitoring the V DD level during execution. When V DD drops

Feb. 25, 2021 25 of 81 Rev 1.02 MS51 SERIES DATASHEET to the selected brown-out trigger level (VBOD), the brown-out detection logic will reset the MCU if BORST (BODCON0.2) setting 1. After a brown -out reset, BOR F (BODCON0.1) will be set as 1 via hardware. BORF will not be altered by any reset other than a power-on reset or brown-out reset itself. This bit can be set or cleared by software.

Feb. 25, 2021 26 of 81 Rev 1.02 MS51 SERIES DATASHEET BODCON0 – Brown-out Detection Control 0 Register SFR Address Reset Value BODCON0 A3H, Page 0, TA protected POR,CCCC XC0X b BOD, UUUU XU1X b Others,UUUU XUUX b 7 6 5 4 3 2 1 0 BODEN BOV[2:0] BOF BORST BORF BOS R/W R/W R/W R/W R/W R Bit Name Description

1 BORF Brown-out reset flag

When the MCU is reset by brown-out event, this bit will be set via hardware. This flag is recommended to be cleared via software. External Reset and Hard Fault Reset The external reset pin RST̅̅̅̅̅̅ is an input with a Schmitt trigger. An external reset is accomplished by holding the RST̅̅̅̅̅̅ pin low for at least 24 system clock cycles to ensure detection of a valid hardware reset signal. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a synchronous operation and requires the clock to be running to cause an external reset. Once the device is in reset condition, it will remain as long as RST̅̅̅̅̅̅ pin is low. After the RST̅̅̅̅̅̅ high is removed, the MCU will exit the reset state and begin code executing from address 0000H. If an external reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is slightly different. Since the Power-down mode stops system clock, the reset signal will asynchronously cause the system clock resuming. After the system clock is stable, MCU will enter the reset state. There is a RSTPINF (AUXR0.6) flag, which indicates an external reset took place. After the external reset, this bit will be set as 1 via hardware. RSTPINF will not change after any reset other than a power- on reset or the external reset itself. This bit can be cleared via software. Hard Fault reset will occur if CPU fetches instruction address over Flash size , HardF (AUXR0.5) flag will be set via hardware. HardF will not change after any reset other than a power-on reset or the external reset itself. This bit can be cleared via software. If MCU run in OCD debug mode and OCDEN = 0, hard fault reset will be disabled. Only HardF flag be asserted.

Feb. 25, 2021 27 of 81 Rev 1.02 MS51 SERIES DATASHEET AUXR1 – Auxiliary Register Register SFR Address Reset Value AUXR1 A2H , Page 0 POR: 0000 0000b, Software reset: 1U00 0000b, nRESET pin: U100 0000b, Others: UUU0 0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R/W R/W R/W R/W R/W R/W R R/W Bit Name Description

6 RSTPINF External reset flag

When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended that the flag be cleared via software.

5 HardF Hard Fault reset flag

Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset and this bit will be set via hardware. It is recommended that the flag be cleared via software. Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only HardF flag be asserted. Watchdog Timer Reset The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock source. User can clear the WDT at any time, causing it to restart the counter. When the selected time - out occurs but no software response taking place for a while, the WDT will reset the system directly and CPU will begin execution from 0000H. Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via software. WDCON – Watchdog Timer Control Register SFR Address Reset Value WDCON AAH, Page 0, TA protected POR 0000_0111 b WDT 0000_1UUU b Others 0000_UUUU b 7 6 5 4 3 2 1 0 WDTR WDCLR WDTF WIDPD WDTRF WDPS[2:0] R/W R/W R/W R/W R/W R/W

Feb. 25, 2021 28 of 81 Rev 1.02 MS51 SERIES DATASHEET Bit Name Description

3 WDTRF WDT reset flag

When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is recommended to be cleared via software after reset. Software Reset The MS51 provides a software reset, which allows the software to reset the whole system just similar to an external reset, initializing the MCU as it reset state. The software reset is quite useful in the end of an ISP progress. For example, if an ISP of Boot Code updating User Code finishes, a software reset can be asserted to re -boot CPU to execute new User Code immediately. Writing 1 to SWRST (CHPCON.7) will trigger a software reset. Note that this bit is writing TA protection. The instruction that sets the SWRST bit is the last instruction that will be executed before the device reset. See demo code below. If a software reset occurs, SWRF (AUXR0.7) will be automatically set by hardware. User can check it as the reset source indicator. SWRF keeps unchanged after any reset other than a power -on reset or software reset itself. SWRF can be cleared via software.

Feb. 25, 2021 29 of 81 Rev 1.02 MS51 SERIES DATASHEET CONFIG0 7 6 5 4 3 2 1 0 CBS - OCDPWM OCDEN - RPD LOCK - R/W - R/W R/W - R/W R/W - Factory default value: 1111 1111b Bit Name Description

7 CBS CONFIG boot select

This bit defines from which block that MCU re-boots after resets except software reset. 1 = MCU will re-boot from APROM after resets except software reset. 0 = MCU will re-boot from LDROM after resets except software reset.

5 OCDPWM PWM output state under OCD halt

This bit decides the output state of PWM when OCD halts CPU. 1 = Tri-state pins those are used as PWM outputs. 0 = PWM continues. Note that this bit is valid only when the corresponding PIO bit of PWM channel is set as 1.

4 OCDEN OCD enable

1 = OCD Disabled. 0 = OCD Enabled. Note: If MCU run in OCD debug mode and OCDEN = 0, hard fault reset will be disabled and only Hard F flag be asserted.

2 RPD Reset pin disable

1 = The reset function of P2.0/Nrst pin Enabled. P2.0/Nrst functions as the external reset pin.

1 LOCK Chip lock enable

1 = Chip is unlocked. Flash Memory is not locked. Their contents can be read out through a parallel Writer/ICP programmer. 0 = Chip is locked. Whole Flash Memory is locked. Their contents read through a parallel Writer or ICP programmer will be all blank (FFH). Programming to Flash Memory is invalid. Note that CONFIG bytes are always unlocked and can be read. Hence, once the chip is locked, the CONFIG bytes cannot be erased or programmed individually. The only way to disable chip lock is execute “whole chip erase”. However, all data within the Flash Memory and CONFIG bits will be erased when this procedure is executed. If the chip is locked, it does not alter the IAP function. CHPCON CONFIG0 CBS OCDPWM OCDEN RPD LOCK SWRST IAPFF BS IAPEN Software reset does not reload Figure 6.2-1 CONFIG0 Any Reset Reloading

Feb. 25, 2021 30 of 81 Rev 1.02 MS51 SERIES DATASHEET CONFIG1 7 6 5 4 3 2 1 0 - - - - - LDSIZE[2:0] - - - - - R/W Factory default value: 1111 1111b Bit Name Description 2:0 LDSIZE[2:0] LDROM size select This field selects the size of LDROM. 111 = No LDROM. APROM is 32 Kbytes. 110 = LDROM is 1 Kbytes. APROM is 31 Kbytes. 101 = LDROM is 2 Kbytes. APROM is 30 Kbytes. 100 = LDROM is 3 Kbytes. APROM is 29 Kbytes. 0xx = LDROM is 4 Kbytes. APROM is 28 Kbytes.

Feb. 25, 2021 31 of 81 Rev 1.02 MS51 SERIES DATASHEET CONFIG2 7 6 5 4 3 2 1 0 CBODEN CBOV[2:0] BOIAP CBORST - - R/W R/W R/W R/W - - Factory default value: 1111 1111b Bit Name Description

7 CBODEN CONFIG brown-out detect enable

1 = Brown-out detection circuit on. 0 = Brown-out detection circuit off. 5:4 CBOV[1:0] CONFIG brown-out voltage select 11 = VBOD is 2.2V. 10 = VBOD is 2.7V. 01 = VBOD is 3.7V. 00 = VBOD is 4.4V.

3 BOIAP Brown-out inhibiting IAP

This bit decides whether IAP erasing or programming is inhibited by brown-out status. This bit is valid only when brown-out detection is enabled. 1 = IAP erasing or programming is inhibited if VDD is lower than VBOD. 0 = IAP erasing or programming is allowed under any workable VDD.

2 CBORST CONFIG brown-out reset enable

This bit decides whether a brown-out reset is caused by a power drop below VBOD. 1 = Brown-out reset Enabled. 0 = Brown-out reset Disabled. BODCON0 CONFIG2 CBODEN CBOV[2:0] 6 5 4 BOIAP CBORST BODEN BOV[2:0] 6 5 4 BOF BORST BORF BOS Figure 6.2-2 CONFIG2 Power-On Reset Reloading

Feb. 25, 2021 32 of 81 Rev 1.02 MS51 SERIES DATASHEET CONFIG4 7 6 5 4 3 2 1 0 WDTEN[3:0] - - - - R/W - - - - Factory default value: 1111 1111b Bit Name Description 7:4 WDTEN[3:0] WDT enable This field configures the WDT behavior after MCU execution. 1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control. 0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power- down mode. Others = WDT is Enabled as a time-out reset timer and it keeps running during Idle or Power- down mode. 3:0 - Reserved

Feb. 25, 2021 33 of 81 Rev 1.02 MS51 SERIES DATASHEET

6.3 General Purpose I/O (GPIO)

The MS51 has a maximum of 30 general purpose I/O pins which 29 bit-addressable general I/O pins grouped as 4 ports, P0 to P 3, and 1 input only pin as P20. Each port has its port control register (Px register). The writing and reading of a port control register have different meanings. A write to port control register sets the port output latch logic value, whereas a read gets the port pin logic state. These four modes are quasi-bidirectional (standard 8051 port structure), push-pull, input-only, and open-drain modes. Each port spends two special function registers PxM1 and PxM2 to select the I/O mode of port Px. The list below illustrates how to select the I/O mode of Px.n. Note that the default configuration of is input-only (high-impedance) after any reset.

Feb. 25, 2021 34 of 81 Rev 1.02 MS51 SERIES DATASHEET

6.4 Timer

6.4.1 Timer/Counter 0 And 1

Timer/Counter 0 and 1 on MS51 are two 16 -bit Timers/Counters. Each of them has two 8 -bit registers those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and TL0, the lower 8-bit register. Similarly Timer/Counter 1 has two 8-bit registers, TH1 and TL1. TCON and TMOD can configure modes of Timer/Counter 0 and 1. The Timer or Counter function is selected b y the C/T̅ bit in TMOD. Each Timer/Counter has its own selection bit. TMOD.2 selects the function for Timer/Counter 0 and TMOD.6 selects the function for Timer/Counter 1 When configured as a “Timer”, the timer counts the system clock cycles. The timer clock is 1/12 of the system clock (FSYS) for standard 8051 capability or direct the system clock for enhancement, which is selected by T0M (CKCON.3) bit for Timer 0 and T1M (CKCON.4) bit for Timer 1. In the “Counter” mode, the countering register increases on the falling edge of the external input pin T0. If the sampled value is high in one clock cycle and low in the next, a valid 1-to-0 transition is recognized on T0 or T1 pin. The Timers 0 and 1 can be configured to automatically to toggle output whenever a ti mer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. This function is enabled by control bits T0OE and T1OE in the CKCON register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be logic 1 prior to the first timer overflow when this mode is turned on. In order for this mode to function, the C/T̅ bit should be cleared selecting the system clock as the clock source for the timer. Note that the TH0 (TH1) and TL0 (TL1) are accessed separately. It is strongly recommended that in mode 0 or 1, user should stop Timer temporally by clearing TR0 (TR1) bit before reading from or writing to TH0 (TH1) and TL0 (TL1). The free-running reading or writing may cause unpredictable result.

6.4.2 Timer2 And Input Capture

Timer 2 is a 16 -bit up counter cascaded with TH2, the upper 8 bits register, and TL2, the lower 8 bit register. Equipped with RCMP2H and RCMP2L, Timer 2 can operate under compare mode and auto - reload mode selected by CM/RL2̅̅̅̅̅̅ (T2CON.0). An 3-channel input capture module makes Timer 2 detect and measure the width or period of input pulses. The results of 3 input captures are stores in C0H and C0L, C1H and C1L, C2H and C2L individually. The clock source of Timer 2 is from the system clock pre-scaled by a clock divider with 8 different scales for wide field application. The clock is enabled when TR2 (T2CON.2) is 1, and disabled when TR2 is 0. The following registers are related to Timer 2 function.

Feb. 25, 2021 35 of 81 Rev 1.02 MS51 SERIES DATASHEET TF2 Timer 2 Interrupt Pre-scalarFSYS RCMP2H T2DIV[2:0] (T2MOD[6:4]) RCMP2L CAPF0 CAPF1 CAPF2 LDEN[1] (T2MOD.7)LDTS[1:0] (T2MOD[1:0]) TR2 (T2CON.2) Timer 2 Module C0HC0L Noise Filter ENF0 (CAPCON2.4) or [00] [01] [10] CAP0LS[1:0] (CAPCON1[1:0]) CAPEN0 (CAPCON0.4) Input Capture 0 Module Input Capture 1 Module Input Capture 2 Module Input Capture Flags (CAPF[2:0]) CAPCR[1] (T2MOD.3) CAPF0 CAPF1 CAPF2 Clear Timer 2 [1] Once CAPCR and LDEN are both set, an input capture event only clears TH2 and TL2 without reloading RCMP2H and RCMP2L contents. Input Capture Interrupt CAPF0 CAPF1 CAPF2 CMPCR (T2MOD.2) Clear Timer 2 CAP0 CAP1 CAP2 TH2TL2 Clear Counter CAPF0 0000 0001 0010 0011 0100 0101 0110 0111 P1.5/IC7 P0.5/IC6 P0.3/IC5 P0.1/IC4 P0.0/IC3 P1.0/IC2 P1.1/IC1 P1.2/IC0 1000 P0.4/IC3 Figure 6.4-1 Timer 2 Block Diagram

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6.4.3 Timer 3

Timer 3 is implemented simply as a 16 -bit auto-reload, up-counting timer. The user can select the pre - scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and RL3 registers to be reloaded into the int ernal 16-bit counter. If ET3 (EIE1.1) is set as 1, Timer 3 interrupt service routine will be served. TF3 is auto-cleared by hardware after entering its interrupt service routine. Timer 3 can also be the baud rate clock source of both UARTs.. RL3 TR3 (T3CON.3) FSYS Internal 16-bit Counter 0 7 RH3 0 7 Timer 3 OverflowPre-scalar (1/1~1/128) T3PS[2:0] (T3CON[2:0]) TF3 (T3CON.4) Timer 3 Interrupt Figure 6.4-2 Timer 3 Block Diagram

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6.5 Pulse Width Modulated (PWM)

6.5.1 Overview

The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit. The MS51 PWM 0 is especially designed for motor control by providing three pairs, maximum 1 6-bit resolution of PWM 0 output with programmable period and duty. The architecture makes user easy to drive the one -phase or three -phase brushless DC motor (BLDC), or three -phase AC induction motor. Each of six PWM can be configured as one of independent mode, complementary mode, or synchronous mode. If the complementary mode is used, a programmable dead -time insertion is available to protect MOS turn-on simultaneously. The PWM waveform can be edge -aligned or center-aligned with variable interrupt points. The MS51 PWM1/2/3 provide individual configurable period and duty. maximum 16-bit resolution output. Each of two PWM1/2/3 can be configured as one of independent mode, complementary mode, or synchronous mode.The PWM 1/2/3 waveform can be edge -aligned or cen ter-aligned with variable interrupt points. PWM output pin define and enable control register table. PWM Channel Output Pin Control register 1 Control register2 SFR Byte Name Bit name Value SFR Byte Name Bit name Value PWM0_CH0 P1.2 PIOCON0 PIO12 1 AUXR4[1:0] PWM1C0P 00 P3.3 PIOCON2 PIO33 1 - - - PWM0_CH1 P1.1 PIOCON0 PIO11 1 AUXR4[3:2] PWM1C1P 00 P1.4 PIOCON1 PIO14 1 AUXR4[3:2] PWM1C1P 00 PWM0_CH2 P0.5 PIOCON1 PIO05 1 AUXR4[5:4] PWM2C0P 00 P1.0 PIOCON0 PIO10 1 - - - PWM0_CH3 P0.4 PIOCON1 PIO04 1 AUXR4[7:6] PWM2C1P 00 P0.0 PIOCON0 PIO00 1 AUXR4[7:6] PWM2C1P 00 PWM0_CH4 P0.1 PIOCON0 PIO01 1 AUXR5[1:0] PWM3C0P 00 PWM0_CH5 P0.3 PIOCON0 PIO03 1 AUXR5[3:2] PWM3C1P 00 P1.5 PIOCON1 PIO15 1 AUXR5[3:2] PWM3C1P 00 PWM1_CH0 P2.3 PIOCON2 PIO23 1 AUXR4[1:0] PWM1C0P P1.2 PIOCON0 PIO12 1 10 PWM1_CH1 P2.2 PIOCON2 PIO22 1 AUXR4[3:2] PWM1C1P P1.4 PIOCON1 PIO14 1 10 P1.1 PIOCON0 PIO11 1 11 PWM2_CH0 P2.1 PIOCON2 PIO21 1 AUXR4[5:4] PWM2C0P P1.0 PIOCON0 PIO10 1 01 P0.5 PIOCON1 PIO05 1 10 PWM2_CH1 P3.0 PIOCON2 PIO30 1 AUXR4[7:6] PWM2C1P 00

Feb. 25, 2021 38 of 81 Rev 1.02 MS51 SERIES DATASHEET PWM Channel Output Pin Control register 1 Control register2 SFR Byte Name Bit name Value SFR Byte Name Bit name Value P3.1 PIOCON2 PIO31 1 01 P0.0 PIOCON0 PIO00 1 10 P0.4 PIOCON1 PIO04 1 11 PWM3_CH0 P3.2 PIOCON2 PIO32 1 AUXR5[1:0] PWM3C0P P0.1 PIOCON0 PIO01 1 10 P1.7 PIOCON1 PIO17 1 - PWM3_CH1 P3.4 PIOCON2 PIO34 1 AUXR5[3:2] PWM3C1P P1.5 PIOCON1 PIO15 1 10 P0.3 PIOCON0 PIO03 1 11 Table 6.5-1 PWM Pin Define And Enable Control Register

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6.6 Watchdog Timer (WDT)

6.6.1 Overview

The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT reset recover the system. It provides a system monitor, which imp roves the reliability of the system. Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system, which is able to operate during Idle or Power -down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the WDT to operate as a time-out reset timer or a general purpose timer. The Watchdog time-out interval is determined by the formula 64×scalar divider clock×F LIRC , where FLIRC is the frequency of internal 10 kHz oscillator. The following table shows an example of the Watchdog time-out interval with different pre-scales. WDPS.2 WDPS.1 WDPS.0 Clock Divider Scale WDT Time-Out Timing[1] 0 0 0 1/1 6.40 ms 0 0 1 1/4 25.60 ms 0 1 0 1/8 51.20 ms 0 1 1 1/16 102.40 ms 1 0 0 1/32 204.80 ms 1 0 1 1/64 409.60 ms 1 1 0 1/128 819.20 ms 1 1 1 1/256 1.638 s Note: This is an approximate value since the deviation of LIRC. Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars Since the limitation of the maxima vaule of WDT timer delay. To up MS51 from idle mode or power down mode suggest use WKT function see Chapter 6.7 Self Wake-Up Timer (WKT).

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6.7 Self Wake-Up Timer (WKT)

6.7.1 Overview

The MS51 has a dedicated Self Wake -up Timer (WKT), which serves for a periodic wake -up timer in low power mode or for general purpose timer. WKT remains co unting in Idle or Power -down mode. When WKT is being used as a wake -up timer, a start of WKT can occur just prior to entering a power management mode. WKT has one clock source, internal 10 kHz. Note that the system clock frequency must be twice over WKT clock. If WKT starts counting, the selected clock source will remain active once the device enters Idle or Power -down mode. Note that the selected clock source of WKT will not automatically enabled along with WKT configuration. User should manually enable th e selected clock source and waiting for stability to ensure a proper operation. The WKT is implemented simply as a 8 -bit auto-reload, up-counting timer with pre-scale 1/1 to 1/2048 selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK re gister to determine its overflow rate. The WKTR (WKCON.3) can be set to start counting. When the counter rolls over FFH, WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of the RWK register to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT interrupt service routine will be served. WKTR (WKCON.3) Internal 16-bit Counter RWK WKT OverflowPre-scalar (1/1~1/2048) WKPS[2:0] (WKCON[2:0]) WKTF (WKCON.4) WKT Interrupt 10 kHz Internal Oscillator FLIRC Figure 6.7-1 Self Wake-Up Timer Block Diagram

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6.8 Serial Port (UART0 & UART1)

6.8.1 Overview

The MS51 includes two enhanced full duplex serial ports enhanced with automatic address recognition and framing error detection. As control bits of these two serial ports are implemented the same . Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to serial port 0. Each serial port supports one synchronous communication mode, Mode 0, and three modes of full duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it can transmit and receive simultaneously. The serial port is also receiving -buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. The receiving and transmitting registers are both accessed at SB UF. Writing to SBUF loads the transmitting register, and reading SBUF accesses a physically separate receiving register. There are four operation modes in serial port. In all four modes, transmission initiates by any instruction that uses SBUF as a destination register.

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6.9 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4)

6.9.1 Overview

The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE provides ISO 7816-3 Interface controller (SC controller) with asynchronous protocal based on ISO/IEC 7816 -3 standard. Software controls GPIO pins as the smartcard reset function and card detection function. This controller also provides UART emulation for high precision baud rate communication. RX_FIFO TX_FIFO TX/RX Control Unit RX Shift Register TX Shift Register ETU Clock Generator Control and Status Registers Baud Rate Generator Internal Data Bus TX_OUTRX_IN Figure 6.9-1 SC Controller Block Diagram  ISO-7816-3 T = 0, T = 1 compliant  Programmable transmission clock frequency  Programmable extra guard time selection  Supports auto inverse convention function  Supports UART mode – Full duplex, asynchronous communications – Supports programmable baud rate generator for each channel – Programmable transmitting data delay time between the last stop bit leaving the TX - FIFO and the de-assertion by setting SCnEGT register – Programmable even, odd or no parity bit generation and detection – Programmable stop bit, 1 or 2 stop bit generation Following is the ISO 7816-3 multi function pin define URAT Pin SC Pin Pin Name SFR Define SFR Byte Name SFR Bit Name Value UART2_TXD SC0_CLK P0.3 AUXR2[7:6] UART2TXP P3.0 10 UART2_RXD SC0_DAT P0.4 AUXR2[5:4] UART2RXP P1.7 10

Feb. 25, 2021 43 of 81 Rev 1.02 MS51 SERIES DATASHEET URAT Pin SC Pin Pin Name SFR Define SFR Byte Name SFR Bit Name Value UART3_TXD SC1_CLK P1.2 AUXR3[3:2] UART3TXP P1.5 10 P0.5 11 UART3_RXD SC1_DAT P1.1 AUXR3[1:0] UART3RXP P2.5 10 P3.4 11 UART4_TXD SC2_CLK P2.3 AUXR3[7:6] UART4TXP 01 UART4_RXD SC2_DAT P2.2 AUXR3[5:4] UART4RXP 01 Table 6.9-1 Smart Card or UART Pin Define And Enable Control Register

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6.10 Inter-Integrated Circuit (I2C)

6.10.1 Overview

The MS51 provides two Inter-Integrated Circuit (I2C) bus to serves as an serial interface between the microcontrollers and the I2C devices such as EEPROM, LCD module, temperature sensor, and so on. The I2C bus used two wires design (a serial data line I 2C0_SDA and a serial clock line I 2C0_SCL) to transfer information between devices. The I2C bus uses bi -directional data transfer between masters and slaves. There is no central master and the multi-master system is allowed by arbitration between simultaneously transmitting masters. The serial clock synchronization allows devices with different bit rates to communicate via one serial bus. The I2C bus supports four transfer modes including master transmitter, master recei ver, slave receiver, and slave transmitter. The I 2C interface only supports 7 -bit addressing mode. A special mode General Call is also available. The I2C can meet both standard (up to 100kbps) and fast (up to 400k bps) speeds.

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6.11 Serial Peripheral Interface (SPI)

6.11.1 Overview

The MS51 provides two Serial Peripheral Interface (SPI) block to support high -speed serial communication. SPI is a full -duplex, high -speed, synchronous communication bus between microcontrollers or other peripheral devices such as serial EE PROM, LCD driver, or D/A converter. It provides either Master or Slave mode, high-speed rate up to FSYS/2, transfer complete and write collision flag. For a multi-master system, SPI supports Master Mode Fault to protect a multi-master conflict. Divider /2, /4, /8, /16 Select MSB LSB Pin Contorl Logic MISO MOSI SPCLK SS SPI Status Control Logic SPI Status Register SPI Control Register Clock Logic S M M S CLOCK SPIF WCOL SPIOVF MODF DISMODF SPI Interrupt SPIEN MSTR MSTR SSOE DISMODF SPR0 SPR1 SPR0 SPR1 CPHA CPOL MSTR LSBFE SPIEN SSOE SPIEN Internal Data Bus FSYS Write Data Buffer 8-bit Shift Register Read Data Buffer Figure 6.11-1 SPI Block Diagram Figure15.1 SPI Block Diagram shows SPI block diagram. It provides an overview of SPI architecture in this device. The main blocks of SPI are the SPI control register logic, SPI status logic, clock rate control logic, and pin control logic. For a serial data transfer or receiving, The SPI bl ock exists a write data buffer, a shift out register and a read data buffer. It is double buffered in the receiving and transmit directions. Transmit data can be written to the shifter until when the previous transfer is not complete. Receiving logic consists of parallel read data buffer so the shift register is free to accept a second data, as the first received data will be transferred to the read data buffer. The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SPCLK), and Slave Select (SS̅̅̅̅). The MOSI pin is used to transfer a 8-bit data in series from the Master to the Slave. Therefore, MOSI is an output pin for Master device and a n input for Slave. Respectively, the MISO is used to receive a serial data from the Slave to the Master.

Feb. 25, 2021 47 of 81 Rev 1.02 MS51 SERIES DATASHEET be considered as one 16-bit circular shift register. Therefore, while a transfer data pushed from Master into Slave, the data in Slave will also be pulled in Master device respectively. The transfer effectively exchanges the data, which was in the SPI shift registers of the two MCUs. By default, SPI data is transferred MSB first. If the LSBFE (SPCR.5) is set, SPI data shifts LSB first. This bit does not affect the position of the MSB and LSB in the data register. Note that all the following description and figures are under the condition of LSBFE logic 0. MSB is transmitted and received first. There are three SPI registers to support its operations, including SPI control register (SPCR), SPI status register (SPSR), and SPI data register (SPDR). These registers provide control, status, data storage functions, and clock rate selection. The following registers relate to SPI function.

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6.12.1 Overview

The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog input signal to a 12 -bit binary representation of that signal. The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE is selected as 8-channel inputs in single end mode. The internal band -gap voltage 1.22 V also can be the internal ADC input. The analog input, multiplexed into one sample an d hold circuit, charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation and stores the result in the r esult registers. The ADC controller also supports continuous conversion and storage result data into XRAM.

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7 APPLICATION CIRCUIT

7.1 Power supply scheme

0.1uF 10uF+0.1uF EXT_PWR EXT_VSS as close to VDD as possible as close to the EXT_PWR as possible MS51 Series Figure 7.1-1 NuMicro® MS51 Power supply circuit

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7.2 Peripheral Application scheme

UART_RXD UART_TXD DVCC 10 uF nRESET VDD VSS I2C DeviceCLK DIOI2C_SDA I2C_SCL DVCC DVCC VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC 10K 4.7K4.7K Reset Circuit VDD VSS nRESET ICE_DAT ICE_CLK ICE / ICP Interface DVCC 100K100K 100 * 100 * *ICE/ICP interface ICE_DAT/ICE_CLK pin 100ohm resister is selectable only for filter the disturb of noise on the circuit. 4~32 MHz crystal XT1_OUT XT1_IN 20pF 20pF HXT Note: 1. It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin. 2. It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. 3. It is optional add 100ohm resistor series between ICE_DAT/ICE_CLK pin to help filtering noise interference. 4. The HXT external capacitor value please reference Section 8.3.2.2Typical Crystal Application Circuits Capacitors Value Figure 7.2-1 NuMicro® MS51 Peripheral interface circuit

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8 ELECTRICAL CHARACTERISTICS

Please refer to the relative Datasheet for detailed information about the MS51 electrical characteristics.

8.1 General Operating Conditions

(VDD-VSS = 2.4 ~ 5.5V, TA = 25C, Fsys = 16 MHz unless otherwise specified.) Symbol Parameter Min Typ Max Unit Test Conditions TA Temperature -40 - 105 ℃ VDD Operation voltage 2.4 - 5.5 V AVDD[*1] Analog operation voltage VDD VBG Band-gap voltage[2] 1.17 1.22

1.30 TA = 25 °C

Note: 1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between VDD and AVDD can be tolerated during power-on and power-off operation . 2. Based on characterization, tested in production. Table 8.1-1 General operating conditions

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8.2 DC Electrical Characteristics

8.2.1 Supply Current Characteristics

The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The curren t consumption is measured as described in below condition and table to inform test characterization result.  All GPIO pins are in push pull mode and output high.  The maximum values are obtained for VDD = 2.4V ~ 5.5 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.  VDD = AVDD  When the peripherals clock base is the system clock Fsys.  Program run “while (1);” in Flash. Symbol Conditions Fsys Typ [6] Max[6][7] Unit TA = 25 °C TA = -40 °C TA = 25 °C TA = 105 °C IDD_RUN Normal run mode, executed from Flash, all peripherals disable

24 MHz(HIRC)[1]

@5.5V 3.6 4.2 4.6 4.8 mA @3.3V 3.2 @2.4V 2.9

16 MHz (HIRC) [1]

@5.5V 3.3 3.4 3.9 4.6 16 MHz (HIRC) [1] @3.3V 3.1 @2.4V 2.8 10 kHz (LIRC)[2] 0.30 0.32 0.46 2.33 Notes: 1. This value base on HIRC enable, LIRC enable 2. This value base on HIRC disable, LIRC enable 3. LVR17 enabled, POR enable and BOD enable. 4. Based on characterization, not tested in production unless otherwise specified. Table 8.2-1 Current consumption in Normal Run mode

Feb. 25, 2021 53 of 81 Rev 1.02 MS51 SERIES DATASHEET Symbol Conditions Fsys Typ [3] Max[3][4] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_IDLE Idle mode, executed from Flash, all peripherals disable @5.5V 2.8 2.9 3.2 3.8 mA @3.3V 2.4 @2.4V 2.2

16 MHz (HIRC)[1]

@5.5V 2.2 2.5 2.6 3.2 @3.3V 1.9 @2.4V 1.8 10 kHz (LIRC)[2] 0.3 0.5 0.9 2.3 Notes: 1. This value base on HIRC enable, LIRC enable 2. This value base on HIRC disable, LIRC enable 3. LVR17 enabled, POR enable and BOD enable. 4. Based on characterization, not tested in production unless otherwise specified. Table 8.2-2 Current consumption in Idle mode Symbol Test Conditions Typ[1] Max[2] Unit TA = 25 °C TA = -40 °C TA = 25 °C TA = 105 °C IDD_PD Power down mode, all peripherals disable@5.5V 6.5 6.2 9 55 µA Power down mode, all peripherals disable@3.3V 6 Power down mode, all peripherals disable@2.4V 5.8 Power down mode, LVR enable all other peripherals disable 7.5 6.7 10[3] 57 Power down mode, LVR enable BOD enable all other peripherals disable 180 165 197 292 Notes: 1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 disabled, POR disabled and BOD disabled. 2. Based on characterization, not tested in production unless otherwise specified. 3. Based on characterization, tested in production. Table 8.2-3 Chip Current Consumption in Power down mode

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8.2.2 Wakeup Time from Low-Power Modes

Symbol Parameter Typ Max Unit tWU_IDLE [1] Wakeup from IDLE mode 5 6 cycles tWU_NPD[2][3] Wakeup from Power down mode Fsys = HIRC @16MHz - 30 µs Fsys = HIRC @ 24MHz 30 µs Notes: 1. Measured on a wakeup phase with a 16 MHz HIRC oscillator. 2. Based on test during characterization, not tested in production. 3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first. Table 8.2-4 Low-power mode wakeup timings

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8.2.3 I/O DC Characteristics

8.2.3.1 PIN Input Characteristics

Symbol Parameter Min Typ Max Unit Test Conditions VIL Input low voltage 0 - 0.3*VDD V VIL1 Input low voltage (I/O with TTL input) VSS-0.3 - 0.2VDD-0.1 V VIH Input high voltage 0.2VDD+0.9 - VDD+0.3 V VIH1 Input high voltage (I/O with Schmitt trigger input and Xin) 0.7*VDD - VDD V VHY[1] Hysteresis voltage of schmitt input - 0.2*VDD - V ILK[2] Input leakage current -1 1 VSS < VIN < VDD, Open-drain or input only mode -1 1 VDD < VIN < 5.5 V, Open-drain or input only mode Notes: 1. Guaranteed by characterization result, not tested in production. 2. Leakage could be higher than the maximum value, if abnormal injection happens. 3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than the maximum value, if positive current is injected on adjacent pins Table 8.2-5 I/O input characteristics

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8.2.3.2 I/O Output Characteristics

Symbol Parameter Min Typ Max Unit Test Conditions ISR[1] [2] Source current for quasi- bidirectional mode and high level -7.4 - -7.5 µA VDD = 5.5 V VIN =(VDD-0.4) V -7.3 - -7.5 µA VDD = 3.3 V VIN =(VDD-0.4) V -7.3 - -7.5 µA VDD = 2.4 V VIN =(VDD-0.4) V -57.2 - -58.3 µA VDD = 5.5 V VIN = 2.4 V Source current for push-pull mode and high level -9 - -9.6 mA VDD = 5.5 V VIN =(VDD-0.4) V -6 - -6.6 mA VDD = 3.3 V VIN =(VDD-0.4) V -4.2 - -4.9 mA VDD = 2.7 V VIN =(VDD-0.4) V -18 - -20 mA VDD = 5.5 V VIN = 2.4 V ISK[1] [2] Sink current for push-pull mode and low level 18 - 20 mA VDD = 5.5 V VIN = 0.4 V 16 - 18 mA VDD = 3.3 V VIN = 0.4 V 9.7 - 11 mA VDD = 2.4 V VIN = 0.4 V CIO[1] I/O pin capacitance - 5 - pF Notes: 1. Guaranteed by characterization result, not tested in production. 2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not exceed ΣIDD and ΣISS. Table 8.2-6 I/O output characteristics

Feb. 25, 2021 57 of 81 Rev 1.02 MS51 SERIES DATASHEET 8.2.3.3 nRESET Input Characteristics Symbol Parameter Min Typ Max Unit Test Conditions VILR Negative going threshold, nRESET - - 0.3*VDD V VIHR Positive going threshold, nRESET 0.7*VDD - - V RRST[1] Internal nRESET pull up resistor 45 - 60 KΩ VDD = 5.5 V 45 - 65 VDD = 2.4 V tFR[1] nRESET input response time - 1.5 - µs Normal run and Idle mode 10 - 25 Power down mode Notes: 1. Guaranteed by characterization result, not tested in production. 2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable. Table 8.2-7 nRESET Input Characteristics

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8.3 AC Electrical Characteristics

8.3.1 Internal High Speed RC Oscillator (HIRC)

8.3.1.1 16MHz RC Oscillator (HIRC) Symbol. Parameter Min Typ Max Unit Test Conditions VDD Operating voltage 2.4 - 5.5 V FHRC Oscillator frequnecy - 16[1] - MHz TA = 25 °C, VDD = 3.3 Frequency drift over temperarure and volatge -1[3] - 1[3] % TA = 25 °C, VDD = 3.3V VDD = 2.4 ~ 5.5V VDD = 2.4 ~ 5.5V IHRC[2] Operating current - 490 550 µA TS[3] Stable time - 3 5 µs TA = -40C ~ +105 °C, VDD = 2.4 ~ 5.5V Notes: 1. Default setting value for the product 2. Based on reload value. 3. Based on characterization, tested in production. 4. Guaranteed by characterization result, not tested in production. 5. Guaranteed by design. Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics

Feb. 25, 2021 59 of 81 Rev 1.02 MS51 SERIES DATASHEET 8.3.1.2 24MHz RC Oscillator (HIRC) Symbol. Parameter Min Typ Max Unit Test Conditions VDD Operating voltage 2.4 - 5.5 V FHRC Oscillator frequnecy - 24[1] - MHz TA = 25 °C, VDD = 3.3 Frequency drift over temperarure and volatge -1[3] - 1[3] % TA = 25 °C, VDD = 3.3V VDD = 2.4 ~ 5.5V VDD = 2.4 ~ 5.5V IHRC[2] Operating current - 490 550 µA TS[3] Stable time - 3 5 µs TA = -40C ~ +105 °C, VDD = 2.4 ~ 5.5V Notes: 1. Default setting value for the product 2. Based on reload value. 3. Based on characterization, tested in production. 4. Guaranteed by characterization result, not tested in production. 5. Guaranteed by design. Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics

Feb. 25, 2021 60 of 81 Rev 1.02 MS51 SERIES DATASHEET The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min[1] Typ Max[1] Unit Test Conditions[2] VDD Operating voltage 1.8 - 5.5 V Rf Internal feedback resister - 500 - kΩ fHXT Oscillator frequency 4 - 24 MHz IHXT Current consumption - 80 180 µA

4 MHz, Gain = L0

• 110 300 8 MHz, Gain = L1 - 180 500 12 MHz, Gain = L2 - 230 650 16 Mhz, Gain = L3 - 360 975 24 MHz, Gain = L4 TS Stable time - 3500 3700 µs
• 950 1050 8 MHz, Gain = L1 - 700 850 12 MHz, Gain = L2 - 450 550 16 Mhz, Gain = L3 - 400 570 24 MHz, Gain = L4 DuHXT Duty cycle 40 - 60 % Notes: 1. Guaranteed by characterization, not tested in production. 2. L0 ~ L4 defined by SFR XLTCON[6:4] HXSG Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator Typical Crystal Application Circuits Capacitors Value For C1 and C2, it is recommended to use high -quality external ceramic capacitors in 10 pF ~ 25 pF range, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C1 and C2. CRYSTAL C1 C2 R1

4 MHz ~ 24 MHz 10 ~ 25 pF 10 ~ 25 pF without

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8.3.3 External 4~24 MHz High Speed Clock Input Signal Characteristics

For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive external clock. The external clock signal has to respect the below Table. The characteristics result from tests performed using a wavefrom generator. Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions fHXT_ext External user clock source frequency 4 - 24 MHz tCHCX Clock high time 8 - - ns tCLCX Clock low time 8 - - ns tCLCH Clock rise time - - 10 ns Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 10 ns High (90%) to low level (10%) fall time DuE_HXT Duty cycle 40 - 60 % VIH Input high voltage 0.7*VDD - VDD V VIL Input low voltage VSS - 0.3*VDD V XT1_IN External clock source tCHCX 90% 10% tCLCH tCHCL tCLCX tCLCL VIL VIH Notes: 1. Guaranteed by characterization, not tested in production. Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal

Feb. 25, 2021 62 of 81 Rev 1.02 MS51 SERIES DATASHEET 8.3.4 10 kHz Internal Low Speed RC Oscillator (LIRC) Symbol Parameter Min Typ Max Unit Test Conditions VDD Operating voltage 2.4 - 5.5 V FLRC Oscillator frequnecy - 10 - kHz Frequency drift over temperarure and volatge VDD = 5V Without software calibration ILRC[3] Operating current - 0.85 1 µA VDD = 3.3V TS Stable time - 500 - μs TA=-40~105°C Notes: 1. Guaranteed by characterization, tested in production. 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design. Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics

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8.3.5 I/O AC Characteristics

Symbol Parameter Typ. Max[*1]. Unit Test Conditions[*2] tf(IO)out Normal mode [4] output high (90%) to low level (10%) falling time 4.6 5.1 ns CL = 30 pF, VDD >= 5.5 V 2.9 3.3 CL = 10 pF, VDD >= 5.5 V 6.6 8 CL = 30 pF, VDD >= 3.3 V 4.3 5 CL = 10 pF, VDD >= 3.3 V 8.5 12.5 CL = 30 pF, VDD >= 2.4 V 8.0 10.7 CL = 10 pF, VDD >= 2.4 V tf(IO)out High slew rate mode [5] output high (90%) to low level (10%) falling time 4.0 4.3 ns CL = 30 pF, VDD >= 5.5 V 2.1 2.5 CL = 10 pF, VDD >= 5.5 V 4.9 5.8 CL = 30 pF, VDD >= 3.3 V 3.0 3.7 CL = 10 pF, VDD >= 3.3 V 9.5 13.8 CL = 30 pF, VDD >= 2.4 V 5.4 7.4 CL = 10 pF, VDD >= 2.4 V tr(IO)out Normal mode [4] output low (10%) to high level (90%) rising time 5.6 6.1 ns CL = 30 pF, VDD >= 5.5 V 3.4 3.7 CL = 10 pF, VDD >= 5.5 V 8.1 9.4 CL = 30 pF, VDD >= 3.3 V 5.1 5.8 CL = 10 pF, VDD >= 3.3 V 15.1 20.3 CL = 30 pF, VDD >= 2.4 V 9.6 12.4 CL = 10 pF, VDD >= 2.4 V tr(IO)out High slew rate mode [5] output low (10%) to high level (90%) rising time 4.8 5.2 ns CL = 30 pF, VDD >= 5.5 V 2.1 2.5 CL = 10 pF, VDD >= 5.5 V 6.4 7.4 CL = 30 pF, VDD >= 3.3 V 3.0 3.7 CL = 10 pF, VDD >= 3.3 V 12.7 16.9 CL = 30 pF, VDD >= 2.4 V 5.4 7.4 CL = 10 pF, VDD >= 2.4 V fmax(IO)out [*3] I/O maximum frequency 24 24 MHz CL = 30 pF, VDD >= 2.4 V CL = 10 pF, VDD >= 2.4 V Notes: 1. Guaranteed by characterization result, not tested in production. 2. CL is a external capacitive load to simulate PCB and device loading. 3. The maximum frequency is defined by 𝑓𝑚𝑎𝑥 = 3 × (𝑡𝑓+𝑡𝑟) . 4. PxSR.n bit value = 0, Normal output slew rate 5. PxSR.n bit value = 1, high speed output slew rate Table 8.3-6 I/O AC characteristics

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8.4 Analog Characteristics

8.4.1 Reset and Power Control Block Characteristics

The parameters in below table are derived from tests performed under ambient temperature. Symbol Parameter Min Typ Max Unit Test Conditions IPOR[*1] POR operating current 10 20 µA AVDD = 5.5V ILVR[*1] LVR operating current 0.5 - 1 AVDD = 5.5V IBOD[*1] BOD operating current - 0.5 2.9 AVDD = 5.5V VPOR POR reset voltage 1 1.15 1.3 V - VLVR LVR reset voltage 1.7 2.0 2.4 - VBOD BOD brown-out detect voltage 4.25 4.4 4.55 BOV[1:0] = [0,0] TLVR_SU[*1] LVR startup time 60 - 80 µs - TLVR_RE[1] LVR respond time 0.4 - 4 Fsys = HIRC@16MHz 180 - 350 Fsys = LIRC TBOD_SU[1] BOD startup time 180 - 320 Fsys = HIRC@16MHz TBOD_RE[1] BOD respond time 2.5 - 5 Fsys = HIRC@16MHz Notes: 1. Guaranteed by characterization, not tested in production. 2. Design for specified applcaiton. Table 8.4-1 Reset and power control unit RVDDR VPOR VDD Time RVDDF VLVR VBOD

Feb. 25, 2021 65 of 81 Rev 1.02 MS51 SERIES DATASHEET BODFLT (BODCON1.1) BOD Operation Mode System Clock Source Minimum Brown-out Detect Pulse Width

0 Normal mode

(LPBOD[1:0] = [0,0]) Any clock source Typ. 1μs Low power mode 1 (LPBOD[1:0] = [0,1]) Any clock source 16 (1/FLIRC) Low power mode 2 (LPBOD[1:0] = [1,0]) Any clock source 64 (1/FLIRC) Low power mode 3 (LPBOD[1:0] = [1,1]) Any clock source 256 (1/ FLIRC) Normal mode (LPBOD[1:0] = [0,0]) HIRC/ECLK Normal operation: 32 (1/FSYS) Idle mode: 32 (1/FSYS) Power-down mode: 2 (1/FLIRC) LIRC 2 (1/FLIRC) Low power mode 1 (LPBOD[1:0] = [0,1]) Any clock source 18 (1/FLIRC) Low power mode 2 (LPBOD[1:0] = [1,0]) Any clock source 66 (1/FLIRC) Low power mode 3 (LPBOD[1:0] = [1,1]) Any clock source 258 (1/ FLIRC) Table 8.4-2 Minimum Brown-out Detect Pulse Width

Feb. 25, 2021 66 of 81 Rev 1.02 MS51 SERIES DATASHEET 8.4.2 12-bit SAR ADC Symbol Parameter Min Typ Max Unit Test Conditions TA Temperature -40 - 105 ℃ AVDD Analog operating voltage 2.7 - 5.5 V AVDD = VDD VREF Reference voltage 2.7 - AVDD V VREF = AVDD VIN ADC channel input voltage 0 - VREF V IADC[1] Operating current (AVDD + VREF current) - - 418 µA AVDD = VDD = VREF = 5.5 V FADC = 500 kHz TCONV = 17 * TADC NR Resolution 12 Bit TADC[2] Conversion Time TADC = TSMP +TADCEC 2.375 19 μs FSYS = 16MHz; 2.417 13.3 μs FSYS = 24MHz; FADC Conversion Rate FADC = 1/TADC 52.6 421 kHz FSYS = 16MHz; 75.2 413 kHz FSYS = 24MHz; TSMP Sampling Time [2]z 0.375 - 17 μs FSYS = 16MHz; 0.417 - 11.3 μs Fsys = 24MHz; ADCAQT = 1 by software[3] TADCEC Encoding Time 2 - - μs This value is fixed by ADC module FADCEC[1] Encoding Rate - - 500 kHz This value is fixed by ADC module TEN Enable to ready time 20 - - μs INL[*1] Integral Non-Linearity Error -3 - +3 LSB VREF = AVDD =VDD DNL[*1] Differential Non-Linearity Error -2 - +4 LSB VREF = AVDD=VDD EG[*1] Gain error -3.5 - +0.4 LSB VREF = AVDD=VDD EO[*1]T Offset error -2 - +2.8 LSB VREF = AVDD=VDD EA[*1] Absolute Error -7 +7 LSB VREF = AVDD=VDD Notes: 1. Guaranteed by characterization result, not tested in production. 2. ADC Convertion time = ADC Sampling Time (TSMP) + ADC Encoding Time (TADCEC). 3. ADC Sampling Time =. ADCF 6ADCAQT*4  （FADC base on ADCDIV (ADCCON1[5:4]) If HIRC = 16MHz, ADC Sampling Time Minimum condition 16MHz 6 (ADCAQT = 0, ADCDIV = 0), ADC Sampling Time Maximum condition 8 / 16MHz 67*4  (ADCAQT = 7, ADCDIV = 7) If HIRC = 24MHz, ADC Sampling Time Minimum condition 24MHz 61*4  (ADCAQT = 1, ADCDIV = 0), Since the minimum sampling time must over 370ns that means when FADCAQT = 24MHz, ADCAQT must be set as 1 by software at least. ADC Sampling Time Maximum condition 8 / 24MHz 67*4  (ADCAQT = 7, ADCDIV = 7) Table 8.4-3 ADC characteristics

Feb. 25, 2021 67 of 81 Rev 1.02 MS51 SERIES DATASHEET 4095 4094 4093 4092 Ideal transfer curve Actual transfer curve Offset Error EO Analog input voltage (LSB) 4095 ADC output code Offset Error EO Gain Error EG EF (Full scale error) = EO + EG DNL

1 LSB

Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.

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8.5 Flash DC Electrical Characteristics

The devices are shipped to customers with the Flash memory erased. Symbol Parameter Min Typ Max Unit Test Condition VFLA[1] Supply voltage 1.62 1.8 1.98 V TA = 25℃ TERASE Page erase time - 5 - ms TPROG Program time - 10 - µs IDD1 Read current - 4 - mA IDD2 Program current - 4 - mA IDD3 Erase current - 12 - mA NENDUR Endurance 100,000 - cycles[2] TJ = -40℃~125℃ TRET Data retention 50 - - year 100 kcycle[3] TA = 55℃ 25 - - year 100 kcycle[3] TA = 85℃ 10 - - year 100 kcycle[3] TA = 105℃ Notes: 1. VFLA is source from chip internal LDO output voltage. 2. Number of program/erase cycles. 3. Guaranteed by design. Table 8.5-1 Flash memory characteristics

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8.6 Absolute Maximum Ratings

Volrage Stesses above the absolute maximum ratings may cause permanent damage to the device. The limiting values are stress ratings only and cannot be used to functional operation of the device. Exposure to the absolute maximum ratings may affect d evice reliability and proper operation is not guaranteed.

8.6.1 Voltage Characteristics

Symbol Description Min Max Unit VDD-VSS[*1] DC power supply -0.3 6.5 V ΔVDD Variations between different power pins - 50 mV |VDD –AVDD| Allowed voltage difference for VDD and AVDD - 50 mV ΔVSS Variations between different ground pins - 50 mV |VSS - AVSS| Allowed voltage difference for VSS and AVSS - 50 mV VIN Input voltage on I/O VSS-0.3 5.5 V Notes: 1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply. Table 8.6-1 Voltage characteristics

8.6.2 Current Characteristics

Symbol Description Min Max Unit ΣIDD[*1] Maximum current into VDD - 200 mA ΣISS Maximum current out of VSS - 200 IIO Maximum current sunk by a I/O Pin - 22 Maximum current sourced by a I/O Pin - 10 Maximum current sunk by total I/O Pins[*2] - 100 Maximum current sourced by total I/O Pins[*2] - 100 Note: 1. Maximum allowable current is a function of device maximum power dissipation. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins. 3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. Table 8.6-2 Current characteristics

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8.6.3 Thermal Characteristics

The average junction temperature can be calculated by using the following equation: TJ = TA + (PD x θJA )  TA = ambient temperature (°C)  θJA = thermal resistance junction-ambient (°C/Watt)  PD = sum of internal and I/O power dissipation Symbol Description Min Typ Max Unit TA Operating ambient temperature -40 - 105 °C TJ Operating junction temperature -40 - 125 TST Storage temperature -65 - 150 θJA[*1] Thermal resistance junction-ambient 20-pin QFN(3x3 mm) 68 - °C/Watt Thermal resistance junction-ambient 20-pin TSSOP(4.4x6.5 mm) 38 - °C/Watt Thermal resistance junction-ambient 28-pin TSSOP(4.4x9.7 mm) 30 - ℃/Watt Thermal resistance junction-ambient 32-pin LQFP(7x7 mm) 62 - ℃/Watt Thermal resistance junction-ambient 33-pin QFN(4x4 mm) 28 - ℃/Watt Note: 1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Table 8.6-3 Thermal characteristics

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8.6.4 EMC Characteristics

8.6.4.1 Electrostatic discharge (ESD)

For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any damage that can be caused by typical levels of ESD.

8.6.4.2 Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:  A supply overvoltage is applied to each power supply pin  A current injection is applied to each input, output and configurable I/O pin

8.6.4.3 Electrical fast transients (EFT)

In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of narrow high-frequency transients on the power distribution system..  Inductive loads: – Relays, switch contactors – Heavy-duty motors when de-energized etc. The fast transient immunity requirements for electronic products are defined in IEC 61000 -4-4 by International ElectrotechnicalCommission (IEC). Symbol Description Min Typ Max Unit VHBM[*1] Electrostatic discharge,human body mode -8000 - +8000 V VCDM[*2] Electrostatic discharge,charge device model -1000 - +1000 LU[*3] Pin current for latch-up[*3] -400 - +400 mA VEFT[*4] [*5] Fast transient voltage burst -4.4 - +4.4 kV Notes: 1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) – Component Level 2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing – Charged Device Model (CDM) – Component Level. 3. Determined according to JEDEC EIA/JESD78 standard. 4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test. 5. The performace cretia class is 4A. Table 8.6-4 EMC characteristics

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8.6.5 Package Moisture Sensitivity(MSL)

The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been opened. All Nuvoton surface mount chips have a moisture level classification. The information is also displayed on the bag packing. Pacakge[1] MSL 20-pin QFN(3x3 mm) MSL 3 20-pin TSSOP(4.4x6.5 mm) MSL 3 28-pin TSSOP (4.4 x 9.7 x 1.0 mm) MSL 3 32-pin LQFP (7.0 x 7.0 x 1.4 mm) MSL 3 33-pin QFN ( 4.0 x 4.0 x0.8 mm) MSL 3 Note: 1. Determined according to IPC/JEDEC J-STD-020 Table 8.6-5 Package Moisture Sensitivity(MSL)

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8.6.6 Soldering Profile

Figure 8.6-1 Soldering profile from J-STD-020C Porfile Feature Pb Free Package Average ramp-up rate (217°C to peak) 3°C/sec. max Preheat temperature 150°C ~200°C 60 sec. to 120 sec. Temperature maintained above 217°C 60 sec. to 150 sec. Time with 5°C of actual peak temperature > 30 sec. Peak temperature range 260°C Ramp-down rate 6°C/sec ax. Time 25°C to peak temperature 8 min. max Note: 1. Determined according to J-STD-020C Table 8.6-6 Soldering Profile

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9 PACKAGE DIMENSIONS

9.1 QFN 33-pin (4.0 x 4.0 x 0.8 mm) Figure 9.1-1 QFN-33 Package Dimension

Feb. 25, 2021 75 of 81 Rev 1.02 MS51 SERIES DATASHEET 9.2 LQFP 32-pin (7.0 x 7.0 x 1.4 mm) Figure 9.2-1 LQFP-32 Package Dimension

Feb. 25, 2021 76 of 81 Rev 1.02 MS51 SERIES DATASHEET 9.3 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) Figure 9.3-1 TSSOP-28 Package Dimension

Feb. 25, 2021 77 of 81 Rev 1.02 MS51 SERIES DATASHEET 9.4 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) Figure 9.4-1 TSSOP-20 Package Dimension

Feb. 25, 2021 78 of 81 Rev 1.02 MS51 SERIES DATASHEET 9.5 QFN 20-pin (3.0 x 3.0 x 0.6mm) Figure 9.5-1 QFN-20 Package Dimension for MS51XC0BE

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10 ABBREVIATIONS

10.1 Abbreviations List

ADC Analog-to-Digital Converter BOD Brown-out Detection GPIO General-Purpose Input/Output Fsys Frequency of system clock HIRC 12 MHz Internal High Speed RC Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) LVR Low Voltage $eset PDMA Peripheral Direct Memory Access POR Power On Reset PWM Pulse Width Modulation SPI Serial Peripheral Interface UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID WKT Wakeup Timer WDT Watchdog Timer Table 10.1-1 List of Abbreviations

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11 REVISION HISTORY

Date Revision Chapter Description 2019.11.28 1.00 Initial release 2019.12.25 1.01 Section 3.2 Section 4.2 Section 8.6.4 Modified selection guide table MS51FC0AE/MS51XC0BE ISO 7816-3 number to 2. Added description for MS51FC0AE. Added P3.0 PWM2_CH1 pin define in Pin Description table. Modified EFT level to 4.4kV 2021.02.25 1.02 Section 3.2 Section 8.4.2 Section 9.1 Section 9.5 Added description for MS51EB0AE. Added ADC sampling timing data of FSYS = 24MHz. Modified QFN33 package dimension to add lead length L1 condition. Modified QFN20 package dimension to add lead length L1 condition.

Feb. 25, 2021 81 of 81 Rev 1.02 MS51 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damages and liabilities thus incurred by Nuvoton.