MP103

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 6

Technical content

P r o d u c t I n n o v a t i o n F r o m MP103 MP103U 1 MP103 GENERAL DESCRIPTION The MP103 is a high voltage, high output current dual channel operational amplifier for driving capaci - tive loads such as piezo devices use in ink jet print - ing applications. The MP103 utilizes proprietary IC’s combined with discrete semiconductor and passive elements on a thermally conductive insulated metal substrate, delivering very high power from a compact module. The amplifier gain is fixed at 65 V/V when the feedback pin is connected to the VOUT pin. Internal compensation provides optimum slew rate and insures stability. The only external components required are the current limit resistors RLIM, a series isolation resis- tor RS and the power supply bypass capacitors.

FEATURES

♦ Low Cost Integrated Solution ♦ Output Current >10A Within SOA ♦ Internal Power Dissipation 35 W Per Channel ♦ 167V/µS Slew Rate

APPLICATIONS

♦ Piezoelectric Actuation For Ink Jet Printer Nozzles Power Operational Amplifiers MP103P r o d u c t I n n o v a t i o n F r o m EQUIVALENT CIRCUIT DIAGRAM Feedback A -Vs IN_A +Vaux +Vs Out B IL Out A Feedback B -Vs +Vs IL -Vs +Vs IL -Vs +Vs IL -Vs +Vs IL -Vs +Vs IL IN_B GND -5V Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved)http://www.cirrus.com SEP 2009 APEX − MP103UREVA

P r o d u c t I n n o v a t i o n F r o m MP103

2 MP103U

Parameter Symbol Min Max Units SUPPLY VOLTAGE, +VS to −VS +VS to −VS 200 V SUPPLY VOLTAGE, −VS −VS -30 V SUPPLY VOLTAGE, +VAUX +VAUX 30 V OUTPUT CURRENT, pk, per Channel (Within SOA) IO(PK) 15 A POWER DISSIPATION, internal, Each Channel PD 35 W INPUT VOLTAGE VIN -5 VAUX V TEMPERATURE, pin solder, 10s 225 °C TEMPERATURE, junction (Note 2) TJ 150 °C TEMPERATURE RANGE, storage TS −40 105 °C CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Parameter Test Conditions Min Typ Max Units INPUT (Each Channel) OFFSET VOLTAGE -6.7 ±2 6.7 mV OFFSET VOLTAGE vs. temperature Full temperature range ±2 µV/°C BIAS CURRENT, initial (Note 3) -6.6 ±3.3 6.6 µA INPUT RESISTANCE, DC 300 KΩ INPUT CAPACITANCE 1.5 pF INPUT VOLTAGE RANGE -3.4 +VAUX - 2 V NOISE f = 10KHz 600 nV/√Hz GAIN (Each Channel) FIXED GAIN Feedback connected to VOUT 63.5 65 66.5 V/V GAIN BANDWIDTH, -3db CL = 47nF 230 KHz POWER BANDWIDTH, 130VP-P +VS = 145V, -VS = -15V 230 KHz OUTPUT (Each Channel) VOLTAGE SWING IO = 10A +VS - 15 +VS - 9 V VOLTAGE SWING IO = -5A -VS + 15 -VS + 14 V CURRENT, Peak, Source 12 A SLEW RATE RS=1.0Ω, CL=47nF, VIN ≥ 8VP-P 167 V/µS POWER SUPPLY (Note 4) VOLTAGE, -VS -7 -15 -20 V VOLTAGE, +VAUX 24 25 V VOLTAGE, +VS -VS + 20 145 -VS + 200 V CURRENT, quiescent, -VS 19 26 mA CURRENT, quiescent, +VAUX 13.5 15 mA CURRENT, quiescent, +VS 1 5 mA SPECIFICATIONS

P r o d u c t I n n o v a t i o n F r o m MP103 MP103U 3 NOTES: 1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi - tions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25°C). 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve high MTTF. 3. Doubles for every 10°C of case temperature increase. 4. +VS and −VS denote the positive and negative supply voltages to the output stages. +VAUX denotes the positive supply voltage to the input stages. 5. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz. Parameter Test Conditions Min Typ Max Units THERMAL RESISTANCE, AC, junction to case (Note 5) Full temperature range, f ≥ 60Hz 1.5 1.75 °C/W RESISTANCE, DC, junction to case Full temperature range, f < 60Hz 3.1 3.6 °C/W RESISTANCE, junction to air Full temperature range 12.5 14 °C/W TEMPERATURE RANGE, case 0 70 °C TOTAL SUPPLY VOLTAGE, VAUX (V) INPUT BIAS CURRENT vs. VAUX SUPPLY NORMALIZED BIAS CURRENT, IB (X) 5 25201510 0.2 0.4 0.6 0.8 1.0 1.2 1.4 TOTAL SUPPLY VOLTAGE, VAUX (V) OFFSET VOLTAGE vs. VAUX SUPPLY NORMALIZED OFSET VOLTAGE, VOS (X) 5 25201510 1.2 1.0 0.8 0.6 0.4 0.2 TOTAL SUPPLY VOLTAGE, VSS (V) OFFSET VOLTAGE vs. VS SUPPLY NORMALIZED OFSET VOLTAGE, VCS (X) 5 205180155130105805530 0.995 1.035 1.030 1.025 1.020 1.015 1.010 1.005 1.000 CASE TEMPERATURE, TC (°C) INPUT BIAS CURRENT vs. TEMPERATURE NORMALIZED BIAS CURRENT, IB (X) 0 20 40 60 80-20-40 0.7 1.2 1.1 1.0 0.9 0.8 0.6 1.6 1.5 1.4 1.3 MAX. OUTPUT PULSE DUTY CYCLE 100 OUTPUT VOLTAGE, VO (V) MAXIMUM DUTY CYCLE, DC (%) TC = 25°C TC = 70°C 100 180160140120 MAX. DC OUTPUT VOLTAGE 100 110 120 130 140 150 CASE TEMPERATURE, T C (°C) DC OUTPUT VOLTAGE, VO (Vdc) 0 755025 CASE TEMPERATURE, TC (°C) OFFSET VOLTAGE vs. TEMPERATURENORMALIZED BIAS CURRENT, IB (X) 0 20 40 60 80-20-40 0.7 1.2 1.1 1.0 0.9 0.8 0.6 QUIESCENT CURRENT 0.96 0.98 1.02 1.04 1.06 1.08 1.1 CASE TEMPERATURE, TC (°C) NORMALIZED QUIESCENT CURRENT, IQ (X) +VS VAUX -VS 0 755025-25 FREQUENCY RESPONSE -20 -10 1K 10K 1M FREQUENCY, F (Hz) GAIN, A V (DB) -180 -150 -120 -90 -60 -30 PHASE, (°) 100K CLOAD = 50nF LEFT SCALE RIGHT SCALE OUTPUT VOLTAGE SWING OUTPUT CURRENT, IO (A) VOLTAGE DROP FROM SUPPLY (V) SOURCE SINK 0 107.552.5 SOA SUPPLY TO OUTPUT DIFFERENTIAL, VS - VO (V) OUTPUT CURRENT FROM +VS OR -VS (A) 10 1001 1mS 10mS SINK DC SOURCE DC POWER DERATING CASE TEMPERATURE, TC (°C) INTERNAL POWER DISSIPATION PER CHANNEL, PD (W) EACH CHANNEL 0 100755025

P r o d u c t I n n o v a t i o n F r o m MP103

4 MP103U

TOTAL SUPPLY VOLTAGE, VAUX (V) INPUT BIAS CURRENT vs. VAUX SUPPLY NORMALIZED BIAS CURRENT, IB (X) 5 25201510 0.2 0.4 0.6 0.8 1.0 1.2 1.4 TOTAL SUPPLY VOLTAGE, VAUX (V) OFFSET VOLTAGE vs. VAUX SUPPLY NORMALIZED OFSET VOLTAGE, VOS (X) 5 25201510 1.2 1.0 0.8 0.6 0.4 0.2 TOTAL SUPPLY VOLTAGE, VSS (V) OFFSET VOLTAGE vs. VS SUPPLY NORMALIZED OFSET VOLTAGE, VCS (X) 5 205180155130105805530 0.995 1.035 1.030 1.025 1.020 1.015 1.010 1.005 1.000 CASE TEMPERATURE, T C (°C) INPUT BIAS CURRENT vs. TEMPERATURE NORMALIZED BIAS CURRENT, IB (X) 0 20 40 60 80-20-40 0.7 1.2 1.1 1.0 0.9 0.8 0.6 1.6 1.5 1.4 1.3 MAX. OUTPUT PULSE DUTY CYCLE 100 OUTPUT VOLTAGE, VO (V) MAXIMUM DUTY CYCLE, DC (%) TC = 25°C TC = 70°C 100 180160140120 MAX. DC OUTPUT VOLTAGE 100 110 120 130 140 150 CASE TEMPERATURE, T C (°C) DC OUTPUT VOLTAGE, VO (Vdc) 0 755025 CASE TEMPERATURE, TC (°C) OFFSET VOLTAGE vs. TEMPERATURENORMALIZED BIAS CURRENT, IB (X) 0 20 40 60 80-20-40 0.7 1.2 1.1 1.0 0.9 0.8 0.6 QUIESCENT CURRENT 0.96 0.98 1.02 1.04 1.06 1.08 1.1 CASE TEMPERATURE, TC (°C) NORMALIZED QUIESCENT CURRENT, IQ (X) +VS VAUX -VS 0 755025-25 FREQUENCY RESPONSE -20 -10 1K 10K 1M FREQUENCY, F (Hz) GAIN, A V (DB) -180 -150 -120 -90 -60 -30 PHASE, (°) 100K CLOAD = 50nF LEFT SCALE RIGHT SCALE OUTPUT VOLTAGE SWING OUTPUT CURRENT, IO (A) VOLTAGE DROP FROM SUPPLY (V) SOURCE SINK 0 107.552.5 SOA SUPPLY TO OUTPUT DIFFERENTIAL, VS - VO (V) OUTPUT CURRENT FROM +VS OR -VS (A) 10 1001 1mS 10mS SINK DC SOURCE DC POWER DERATING CASE TEMPERATURE, TC (°C) INTERNAL POWER DISSIPATION PER CHANNEL, PD (W) EACH CHANNEL 0 100755025 EXTERNAL CONNECTIONS 42-Pin DIP Package Style FC 40 8060 450 -SLR +SLR CASE TEMPERATURE, TC (°C) SLEW RATE vs. TEMPERATURE SLEW RATE, SLR (V/µs) -20 200-40 150 400 350 300 250 200 EXTERNAL FEEDBACK RESISTOR, RFDBK (Ω) AMPLIFIER GAIN vs. RFDBK AMPLIFIER GAIN, AV (V/V) 500 150010000 105 100 TOTAL SUPPLY VOLTAGE, VSS (V) INPUT BIAS CURRENT vs. VSS SUPPLY NORMALIZED BIAS CURRENT, IB (X) 5 20515510555 0.2 0.4 0.6 0.8 1.0 1.2 1801308030

P r o d u c t I n n o v a t i o n F r o m MP103 MP103U 5 Pin # Pin name Description 1,2,3 +VS _A Positive high voltage power supply pins for channel A. 4,5,6 IL _A High current output pins for channel A. A current limit resistor must be placed between these pins and the output pin 8. 8 Out_A Output pin for channel A. 15 Out_B Output pin for channel B. 18,19,20 +VS _B Positive high voltage power supply pins for channel B. 21,22,23 -VS _B Negative power supply pins for channel B. 24,25,26 IL _B High current output pins for channel B. A current limit resistor must be placed between these pins and the output pin 15. 28 IN_B Input pin for channel B.

30 Feedback_B

Feed back pin for channel B. This pin must be connected to output B pin 15 to close the feedback loop. When connected directly to pin 15 the closed loop voltage gain of channel B is 65 V/V. The gain can be increased by inserting a 1/4 W resistor between pins 30 and 15.

32 GND Ground

+24V voltage power supply pin. A 24 V power supply is required for operation of front end small signal circuitry of each channel.

36 Feedback_A

Feed back pin for channel A. This pin must be connected to output A pin 8 to close the feedback loop. When connected directly to pin 8 the closed loop voltage gain of channel A is 65 V/V. The gain can be increased by inserting a 1/4 W resistor between pins 36 and 8. 38 IN_A Input pin for channel A. 40,41,42 -VS _A Negative power supply pins for channel A. PIN DESCRIPTIONS GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, power supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.Cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit, heat sink selection, Apex Precision Power’s complete Application Notes library, Technical Seminar Workbook and Evaluation Kits. AMPLIFIER GAIN When the feedback pin for each channel is connected to the corresponding OUT pin, the gain of the amplifier is internally set to 65 V/V. The amplifier gain can be increased by connecting a resistor between the feedback and Out pin. The amplifier gain will be increased approximately 1 V/V for each additional 49.9Ω added between the feedback and OUT pin. SAFE OPERATING AREA The MOSFET output stage of the MP103 is not limited by second breakdown considerations as in bipolar output stages. Only thermal considerations and current handling capabilities limit the SOA (see Safe Operating Area graph). The output stage is protected against transient flyback by the parasitic body diodes of the output stage MOSFET structure. However, for protection against sustained high energy flyback external fast-recovery diodes must be used. POWER SUPPLY BYPASSING Bypass capacitors to power supply terminals +VS and -VS must be connected physically close to the pins to prevent local parasitic oscillation in the output stage of the MP103. Use electrolytic capacitors at least 10μF per output amp required. Bypass the electrolytic capacitors with high quality ceramic capacitors (X7R) 0.1μF or greater. Duplicate the supply bypass for the supply terminals of each amplifier channel. A bypass capacitor of 0.1μF or greater is rec- ommended for the +VAUX terminal.

P r o d u c t I n n o v a t i o n F r o m MP103

6 MP103U

For proper operation, the current limit resistor (R LIM) must be connected as shown in the external connection dia - gram. For optimum reliability the resistor value should be set as high as possible. The value is calculated as follows; with the maximum practical value of 30Ω. The current limit function can be disabled by shorting the IL pin to the OUT pin. RLIM = 0.7/ILIM POWER SUPPLY PROTECTION Unidirectional zener diode transient suppressors are recommended as protection on the supply pins. The zeners clamp transients to voltages within the power supply rating and also clamp power supply reversals to ground. Whether the zeners are used or not, the system power supply should be evaluated for transient performance in - cluding power-on overshoot and power-off polarity reversal as well as line regulation. Conditions which can cause open circuits or polarity reversals on either power supply rail should be avoided or protected against. Reversals or opens on the negative supply rail is known to induce input stage failure. Unidirectional transzorbs prevent this, and it is desirable that they be both electrically and physically as close to the amplifier as possible. SERIES ISOLATION RESISTOR, RS To insure stability with all capacitive loads a series isolation resistor should be included between the output and the load as shown in the external connections drawing. A 1Ω resistor works well for capacitive loads between 135pF and 44nF. The resistor will affect the rise and fall time of the output pulse at the capacitive load. This can be com - pensated for on the input signal. BACKPLATE GROUNDING The substrate of the MP103 is an insulated metal substrate. It is required that it be connected to signal ground. This is accomplished when the ground pin (Pin 32) is properly connected signal ground. CONTACTING CIRRUS LOGIC SUPPORT For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP - ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD - UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS- TOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.