MMC4046

MMC4046 MICRO-ELECTRONICS | Alldatasheet

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This file has been download from www.datasheetcatalog.com fi ROT i Ir alg wale »\\| 4) MOKEZOGGEWOINIGG wmc4oas oT _ ee MICROPOWER PHASE -LOCKED LOOP GENERAL DESCRIPTION FEATURES The MMC 4046 micropower phase-locked loop @ Wide supply voltage range -3V to 18V (PLL) consists of a low powere, linear, voltage-con- | @ Low dynamic power consumption —70 uW Ityp) at trolled oscillator (VCO), a source follower, a zener fo=10 kHz, Vop=5V diode, and two stage comparators. The two phase © V¥co frequency —1.3 MHz ityp) at Vop=10V comporators have a common signal input and a com- mon comparator input. The signal input can be di- rectly coupled for a large voltage signal or capaciti- vely coupled to the self-biasing amplifier at the sig- nal input for a small voltage signal.

APPLICATIONS

@ FM demodulator and modulator @ Frequency synthesis and multiplication @ Frequency discrimination @ Data synchronization and conditioning © Voltage-to-frequency conversion @ Tone decoding @ Motor speed control SS UU NEESER ABSOLUTE MAXIMUM RATINGS Voo* Supply voltage: G and H types -O.5to 20 Vv E and F types -0.5 to 18 Vv V, Input voltage -O5to VpptO5 Vv I OC input current {any one input) +10 mA Prot Total power dissipation (per package) 200 =mwW Dissipation per output transistor for T, = full package-temperature r nge 100 mw Ta Operating temperature: G and H types -55 to 125 °C € and F types -40to 85 °C Tytg Storage temperature -65to 150 °c nn * All voltage values are referred to Veg pin voltage RECOMMENDED OPERATING CONDITIONS eee Eee Voo* Supply voltage: G and H types 3to 18 Vv E and F types gto 415 Vv v. input voltage Oto Voo Vv Ta Operating temperature G and H types -55 to 125 °c E and F types -40 to 65 °c eA CONNECTION DIAGRAM PuAse Pulses [1] 16) vdd PHASE COMP.1.0UT [2] 5} ZENER CompanATOR IN [3] (ia) SIGNAL IN veo our (] HI) PHASE COMP. 11. OUT nna hz] #2 en (6) hi) aL aw [To] DemoouLATeD out ss (8) (3) vco IN eee

This file has been download from www.datasheetcatalog.com MMC 4046 eT BLOCK DIAGRAM SIGNAL 'N ‘bo 5 9 th % y COMPARATOR I COMPARATOR ‘PHASE COMP 1 OUT IN ----- ot LD 0 0 ' p PHASE 2 eo PHASE COMP II OUT COMPARATOR || 4 ri OPHASE PULSES vco ‘ OUT R3 L----ot O c : | 9 veo IN Low vCco O PASS Li) 1 FRTER Veg" o DEMODULATOR C2 Po | SOURCE 40 OUT T Veg o FOLLOWER a \\ss 5 Rs INHBIT © [8 15 Vss | Ves, ZENER FUNCTIONAL DESCRIPTION VCO SECTION The VCO requires one external capacitor C1 and one or two external resistors (RA, or R, and Re Resistor A, and capacitor C, determine the frequency range of the VCO and resistor A, enables the VCO to have 8 frequency offset if required. The high input impedance (10'? ) of the VCO simplifiers the design of low- pass filters ny permitting the designer a wide choice of resistor-to-capacitor ratios in order not to load the low pass filter, a source-follower output of the VCO input voltage is provided st terminal 10 (DEMOQULATED OUTPUT). if this terminal is used, a load resistor (Ag) of 10K or more should be connec- ted from this terminal to Vgs, if unused this terminal should be left open. The VCO can be connected eit- her directly or through frequency dividers to the comparator input of the phase real nga A full CMOS logic swing 1s available at the ae of the VCO and allows direct coupling to CMOS frequency di- viders such as the MMC 4024. MMC 4018, MMC 4020, MMC 4022, MMC4823, MMC4059. One or inure MMC 4018 (Presettable Divide-by-N-Counter) or MMC 4029 (presettable Up/Down Counter’, to- gether with the MMC 4046, (phase-Locked Loop) can be used to build a micropower low-frequency synthesizer A logic O on the INHIBIT input .enables” the VCO and the source follower, while a logic _turns off” both to minimize standby power consumption. nr

This file has been download from www.datasheetcatalog.com MMC 4046 ae PHASE COMPARATORS The phase-comparator signal input (terminal 14) can be direct-coupled provided the signal swing is within CMOS logic levels /logic “O" < 30% (Von—Vgq), logic “1” > 70% (Vop—Vsg)/. For smaller swings the sig- nal must be capacitively coupled to the self-biasing amplifier at the signal input. Phase comparator | is an exclusive-OR network, ot operates analogously to an over-driver balanced mixer.. To maximize the tock range, the signal-and comparator -input frequencies must have a 50% duty cycle. With no et or noise on the signal input, this phase comparator has an average output voltage equal to Voo/2. The low-pass filter connected to the output of phase comparator | supplies the averaged voltage to the VCO input, and causes the VCO to oscillate at the center frequency (fo). The frequency range of input signals on'which the PLL will lock if it was initially out of lock is defined as the frequency capture range (2f,). The frequency range of input Signals on which the loop will stay locked if it was initially in lock is defined as the frequency lock range (ef). The capture range is <the lock range. With phase comparator | the range of frequencies over which the PLL can acquire lock (capture range) is dependent on the !ow-pass-filter characteristics, and can be made as large as the lock range. Phase-comparator | enables a PLL system to remain in lock in spite of high amounts of noise in the input signal, One characteristic of this type of phase comparator is that it may lock into input frequencies that are close to harmonics of the VCO center-frequency. A second characteristic is that the phase angle between the signal and the comparator input varies between O° and 180°, and is 30° at the center frequency. Fig. (a) shows the typical, triangular, phase-to-output response characteristic of phase-comparator |. Typical waveforms for a eMos phase-locked-loop employing phase comparator | in locked condition f, is shown in Fig. (b). Phase-comparator |! is an edge-controlled digital memory network. It consists of four flip-flop stages, contro! gating, and a three-stage output comprising p-and n-type drivers having a common output node. When the p-MOS or n-MOS drivers are ON they pull the output up to Vpp or down to Veg, respectively. This type of phase comparator acts only on the positive edges of the signal and comparator inputs. The duty cycles of the signal and comparator inputs are not important since positive transitions control the PLE system utilizing this type of comparator. If the signal-input frequency is higher than the comparator- input frequency. the p-type output driver is maintained On most of the time, and both n-and p-drivers OFF (3 state) the remainder of the time. If the signal-input frequency is lower than the comparator-input fre- quency, the n-type output driver is mainteined ON most of the time, and both the n-and p-drivers OFF (3 state) the remainder of the time. If the signal and comparator-input frequencies are the same, but the signal input tags the comparator input in phase, the n-type output driver is maintained ON for a time cor- responding to the phase difference. If the signal and comparator-input frequencies are the same, but the comparator input lags the signal in phase, the p-type output driver is maintained ON for a time correspon- ding to the phase difference. Subsequently, the capacitor voltage of the low-pass filter connected th this phase comparator is adjusted until the signal and comparator inputs are equal in both phase and frequ- ency. At this stable point both p-and n-type output drivers remain OFF and thus the phase comparator output becomes an open circuit and holds the voltage on the capacitor of the low-pass filter constant. Mo- reaver the signal at the “phase pulses” output is a high level which can be used for indicating a locked condition. Thus, for phase comparator Il, no phase difference exists between signal and comparator input over the full VCO frequency range. More-over, the power dissipation due to the low-pass filter is reduced when this type of phase comparator is used because both the p-and n-type output drivers are OFF for most of the signal input cycle. it should be noted that the PLL lock range for this type of phase comparator is equal to the capture range, independent of the low-pass filter. With no signal present at the signal input, the VCO is adjusted to its lowest frequency for phase comparator Jl. Fig. (c) shows typical waveforms for a CMOS PLL employing phase comparator II in a locked condition. Fig. (al — Phase comparator | characteristics low-pass filter output Fig. (b) — Typical waveforms for CMOS Phase Locked-Loop empleying phose comparator | in locked condition of fo. Fig. (c) — Typical waveforms for CMOS Phase-Locked-Loop employing phase comparator Il in locked condition AVERAGE OUTPUT VOLTAGE ‘bp Sink NUT (PW 41 JS LIL VCO. OUTPUT (PIN 4) COMPARATOR 'NPLT (9:N 3) ‘poe PHASE COMPARATOR | | OUTPUT [ PIN 2) VCO INPUT ( PIN 9) *00 0 oF w wea —— \\ANAXZAZ SIGNAL TO COMPARATOR INPUTS oe oa PHASE DIFFERENCE eee

SIGNAL INPUT(PIN14) oe ee VO OUTPUTIPIN4) COMPARATOR INPUT (PIN 3) PHASC COMPARATOR —"po I OUTPUT (PIN 13 ) fb -----w-- 2-2 eo ee = 4. YOO INPUT (PIN 9, = (Gi BSS FRTER ——o— OUTPUT ; —s PHASE PULSE(PIN1) | ens | —oo —Vss NOTE: DASHED LINE iS AN OPEN -CIRCUIT CONDITION STATIC ELECTRICAL CHARACTERISTICS {over recommended operating conditions) ey TEST CONDITIONS VALUES PARAMETER vo | Vo lo | Yoo} Ttow 25°C Lae MLM [rnin Jinan [min T tye Tmax] ron [rar. VCO SECTION Vow Output high o/ 5 <1 5 1495 4.95 4.95 voltage 10/10 <1] 10 ]995 9.95 9.95 Vv 0/15 <1] 15 114.95 14.95) 14.95 Vor Output low 5 /0 <1[ 5 0.05 0.05 005 voltage 10/0 <1] 10 0.05 0.05 G05} Vv 15/0 <1 15 0.05 005 0.05 Jon Output GH 0/5 25 is) e ~16 }-3e 415 drive types JO/ 5 46 5 }-064 -O.514]-1 036 current 0/10 3.5 10 |-16 137-26 og 0/15 | 135 15 42 3.4 |-68 24 A mi types |O/ 5 46 5 }-052 0.44) --14 0.36 10/10. 95 10 13 411-26 ~O.9 0/15 | 135 15 36 30} 68 24 fey Output GH 10/5 04 5 | 064 os 1 036 Sink types }0/10 05 10 16 43 | 26 og current, 0/18 15 15 | 42 34 | 68 a4 an EF 10/5 04 5 | Ose g44] 1 036 types [0/10 05 10} 13 111 26 os 0/15 15 16 | 36 30} 68 a4 lia dy Input BH log 18 +01 +10 °44+01 44 leakage types Any uA ™ ™ Led pes pofed | : tunes ass. 100

PARAMETER v1 Vo | tot | Voo [Teo] uN MyM ea [max. [min | typ [max] PHASE COMPARATOR SECTION ——— Ipp Total device .j GH]0/ 5 5 5 5 150 current types| 0/10 10 10 10 300 0/15 15 15 20 600 0720 20 100 4100 3000} yA Pin 14=Vcg EFIO/ 5 5 2G 30 300 or Vop types] 0/10 10 40 60 600 Pin 5=Voo 0/15 15 80 400 4000 Vou —foput hah O5/45[ <1 9] a5 35 3.5 voltaye wa }<1} 10] 7 7 7 v 15/135 <11 15/11 1 11 Vi, Input low 45/05} <1 5 1.5 15 45 voltage g/1 <1 10 3 3 3 Vv 135/15} <1] 15 4 4 4 o drive mA current EFluss 25 5 |-1.53 -1.34-3.2 -11 0-15] 135 15 | 36 “30; 68 ea Io, —Output GH{O/ 5 0.4 5 | 064, O51] 1 0.36 sink types ]0/10. os 10 | 16 13] 26 og current 0/15 15 15 |} 42 3.4] 68 24 an EF }O/ 5 04 5 | 052 044) 1 036 types|0/10 as 10 | 13 1.4 7 26 og: 0/15 15 15 | 36 3.0] 68 24 aa fel fel betel leakage types wh SUNal2 EF loys] (put 15 03 +10 1403 +1 types lon = G—state GH ote] 0/18 48 +04 +107) -04 +12 Output Lape. prays [P| Rel ele a types * Trow = 55°C tor G, H devices; ~ 40°C for E, F devices * Tuc = +125°C for G, H devices; +85°C for E, F devices The Noise Margin for bath "1" and “O" level is 1. V min. with Vpp = SV 2.V min, with Vgg = 10 V 2.5 V min. with Von = 15 V 101

This file has been download from www.datasheetcatalog.com MMC d045 een ry DYNAMIC ELECTRICAL CHARACTERISTICS {Ta=25°C; C,=5OpF; R,=200K; typical temperature coefficient for all Voo values is O3%/9C, ail input rise and fall time = 20 ns). VALUES PARAMETER TEST CONDITIONS nnn UNIT Voo(V) | Min. Typ. Max. VCO SECTION Po Pp Operating power fo 1OkHz Ay=1M0 5 15 3.0 dissipation Ryze 10 8.0 16.0 mW C,=50pF 15 30.0 60.0 fmax Maximum frequency |R,=10K C,=50pF 5 o2 0.4 Ra=00 10 | 04 oe Vcow=VOO 15 06 4.2 MHz R,=5K C,=50pF 5 a3 0.6 Rp=0 10 | 06 1.2 Vcoin-Vo00 15 10 2.0 Center frequency Programmable with external components {fo) and frequency R,, Ag and C, range tmax—fmun Nonlinearity Voow=2.5V£0.3 A,=10K 5 ro Vecon=7.5Vt5 R,=1M 15 46 Vco Output duty cycle 5,10,15 EE Yo tra, VCO output transition 5 100 200 trey time 10 50 100 ns 18 40 80 Source follower RS>10k 5,10,15 v output (demodulated output) offset voltage Vcooin—Voem Source follower Veon=2.5Vt03 Ag=100K 5 CS oa Veow=5Vt2.5 Ag= 1 % Idemaduiated output! |Ycow=8V# = 300K of | Nonlinearity Veow=7.5V+5 Rg-500K 15 Ry Zener dynamic ____resistance ig=2mA 100 2 ee 102

This file has been download from www.datasheetcatalog.com MMC 42046 oe eee asnnnEE NEE RRERREEEERRERREEREREER ae PHASE COMPARATOR SECTION a R14 Pin 14 (signal in) 5 Os input rezistance 10 0.1 mo 45 0.05 AC. coupled signal fin=100KHz 5 1,2 input voltage sine wave 10 2.4 v sensitivity? 15 4.8 (peak-to-peak) a D tp, Propagation delay time 5 225 450 High to iow level 10 100 200 ns Pins 14 to 13 45 65 130 a cn EE tein. Propagation delay time 5 350 700 Low to high, level 10 150 300 ns 15 100 200 EEE tprz, Propagation delay time 5 225 450 3-state High level to 10 100 200 ns High impedance p Pins 14 to 13 15 65 130 I tpz, Low level to high S 285 570 ~ impedance 10 130 260 ns 15 95 130 ee ty tyinput rise or fall 5 50 time 10 4 us Comparator Pin 3 15 03 a An aN Signal Pin 14 5 500 410 20 aS 15 25 —_— tray Transition time 5 100 200 TH 10 50 100 ns 15 40 80 ee 3¢ For sine wave the frequency must begreater than 10 kHz for Phase Comparator 11 DESIGN INFORMATION This information is a guide for approximating the values of external components for the 4046 in a Phase -Locked-Loop system. The selected external components must be within the following ranges. Sk <R,, Ra RS<1M C1>100pF at Vop>SV C1>S0pF at Vop>10V 103

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