MMC4035

MMC4035 MICRO-ELECTRONICS | Alldatasheet

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This file has been download from www.datasheetcatalog.com im Ts 7 i} . hi Ya A PS fa I MUSTO GES EHOMUEG) mMc. 4038 SS ——— eo oOoOovMCR aan 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER GENERAL OESCRIPTION The MMC 4035 (G and H types) and MMC 4035 (E ded on the first stage SERIAL input to minimize and F types) are monolithic integrated circuit, availa- logic requirements particulary In Counting and sequ- ble in 16-lead dual in-line plastic or ceramic package — ence-generation applications. With JK inputs connec- The MMC 4035 integrated . circuit ts a four- ted together, the first stage becomes a D flip-flop. stage clocked signal serial register with provision for An asynchronous common RESET is also provided. synchronous PARALLEL inputs to eagh stage and SERIAL inputs to the first stage via JK logic. Regis- ter stages 2, 3, and 4 are coupled in a serial D flip- flop configuration when the register is in the serial mode [PARALLEL/SERIAL control low). Parallel entry FEATURES into each register stage is permitted when the PA- RALLEL/SERIAL contro! is high. In the paralle! or se- @ 4-stage clocked shift operation rial mode information is transfered on positive clock @ Synchronous parallel entry on all 4 stages Sate When the ere COMELEMENT control @ JK inputs on first stage is high, the true contents of the register are available - the output terminals, When the TRUE/COMPLE. e ee TRUE/COMPLEMENT contro! an all MENT control is low, the outputs are the comple- 7" sla) 5 ments of the data in the register. The TRUE/COM- a ae fip-flap operation, master-slave configura PLEMENT control functrons asynchronously with @ Buffered inputs and outputs respect to the CLOCK signal. JK input logic is provi- @ High speed 12 MHz typ.) at Vop = 10 V. a ABSOLUTE MAXIMUM RATINGS Voo* Supply voltage: G and H types -0.5 to 20 Vv E and F types -0.5 to 18 Vv v, Input voltage -0.5t0 Vp pt 0.5 v | DC input current (any one input) £10 mA Pree Total power dissipation [per package) 200 mW Dissipation per output transistor for Ty ~ full package-temperature rangr 100 mW Th Operating temperature G and H types -55 to 125 #05 E and F types -40 to 85 “C Tog Storage temperature -65 to 150 °C * All voltage values are referred to Voy pin voltage RECOMMENDED OPERATING CONDITIONS Von" Supply voltage: G and H types 3to 18 Vv ° E and F types 3to 45 Vv ; Input voltage Oto Voo Vv B Operating temperature G and H types: -§5 to 125 c E and F types 40 to 85 Cc CONNECTION DIAGRAM avai gi 160) Veo TRUEJ/COMP (J2 154) 2/02 KQ3 swf) 03/03 Qe Pouce reseT Js yoy Pt-& Lok Ge NEJPL 3 ps7 op a-2 Veg 8 9Pet-1 —_ eee

This file has been download from www.datasheetcatalog.com ns sas FUNCTIONAL DIAGRAM TRUTH TABLE PARALLEL TW? 3 N FIRST STAGE et i) Tete Tero les epee Po cxf] HMC toss jv fi [xfofo [4] PS. ? 4&-STAGE REGSTER aa . a a , an cae PR [TT Tons [oer] Vo: 6 Fr as ee 7 A =? TELL Hoes wm our LoGic DIAGRAM . O» On On On J V/ V/ rO-4q DB; D; | Pp 5 po D p Pa otal ellie ia 0, L Q rm Q pe oa —Po-f>{ [EE ee es res t+ t}+— TP BGP hh oF Ga Tt T T T T mg Dold, Dod) Yo d>4 eds “Ded d Or Orn Ox On P/Ss 0 SERIAL MODE Rm oat omy awd nh C21 eTRUE OUTPUTS a 4 1 Bp ct . q Cp $ ja i q a HK Ch. H 4: _—_% ‘ a a f Ps es dp a

This file has been download from www.datasheetcatalog.com MMC 4035 ee STATIC ELECTRICAL CHARACTERISTICS fyver recamimended aperating conditions) TEST CONDITIONS VALUES PARAMETER | vo [Hol | Yoo a i Quiescent GHjO/ 5 5 5 0.04) 5 150 current types 0/10 10 10 0.04; 10 300 0/15 15 20 0.04}; 20 600 0/20 20 100 0.08 | 100 3000 uA : EF ]O/ 5 5 20 0.04} 20 150 types {0/10 10 40 0.04] 40 300 10/15 15 80 0.04] 80 600 Von Output high o/ 5 <1 5 | 495 495 435 voltage 0/10 <1] 10 19.95 9.95 9.95 Vv O/15 <1; 15 114.95 14.95) 14.95 Vo. Output low 5/0 <1 is) 0.05 0.05 0.05 voltage 10/0 <1] 10 0.05 0.05 0.05] Vv 15/0 <1] 15 0.05 0.05 0.05 Viq Input high as/asi<1{ 5] 35 35 35 voltage 1/9 <1] 1017 7 7 Vv IS/1B5S} <1 15 |11 11 11 Vie Input low 45/05] <1 b) 15 15 1.5 voltage g/1 <1] 10 3 3 3 Vv 13.5/1.51 <1 18 4 4 4 lon Output GH|O/ 5} 25 5 |-2 -1.6 |-3.2 14 drive types}O/ 5 46 5 }-0.64 -0.51]-1 0.36) m Ons} 135 15 | 38 30} 68 ea lo Output GH{O/ 5} O4 5 | 064 O51} 1 0.36 sink types]0/10} O05 10 | 1.6 13 | 26 leks) current O/15} 15 15 | 42 34 |] 68 24 mA EF /OQ/ 5} 04 5 | 052 0.44) 1 0.36 types}O/10} O5 10 | 13 1.4] 26 Og o/s} 615 15 1 36 3.0 | 68 24 Ine hy input GH s| leakage types 0/18 Any 18 +01 +10 5) +0.1 +1 current uA E.F input 5 1 5] C, Input. Capacitance Any input. 75 pF * Trow = 85°C for G, H devices; —40°C for E, F devices. "Thus = +125°C for G, H devices; +B5°C for E, F devices The Noise Margin for both “1” and “O" level is:

1 Vin with Vog = 5V

2 V min. with Vog = 10 V 25 V min. with Vog = 15 V _ eee

This file has been download from www.datasheetcatalog.com mc cas OYNAMIC ELECTRICAL CHARACTERISTICS (Ta = 25°C, C, = 50 pF, R, = 200 kohm, typical temperature coefficient for all Vop = 0.3%/°C values, all input rise and fall time = 20 ns} TEST CONDITIONS VALUES PARAMETER ETE! Voo V) min) wp) mac) Unt Clocked operation et ten Propagation delay time 5 250 | 500 tre : 10 100 | 200 | ns 15 75 | 150 ns Ome Transitian time 5 100 } 200 trum 10 50 | 100] ns 15 40] 80 fox Maximum clock input frequency 5

10 MHz

lw Clock pulse width 5 100 | 200 f 10 45} 90] ns 15 30] 60 ty ly Clock input rise or fall time 418 15 us L Data setup time J/K lines, 5 110 | 220 “we 10 40 | 80 | ns 15 30] 60 ‘sere Data Set up ime Paraliel-in-Lines 5 70 | 140 10 25]; S50] ns 15 20} 40 Reset operation "Oa Propanation delay time 5 230 | 460 Pm 10 100 | 200} ns 18 80 | 160 tw Reset pulse width Ky} 425 | 250 10 55} 110} ns 15 40} 40 TYPICAL APPLICATIONS Shift left/shift right register LEFT of} of yl LEFT/ RIGHT. 5 INPUT RIGHT SHIFT neuT-Lakp CLOCK-——$-47100) TRE/COMPL —f4 RESET R Qi Q 0 4, LEFT SHIFT [fe is RIG OUTPUT T OUTPUT LT Tne nsesreresssssnnnteneennrnenewenninnenrernnsewesusssnsemnaranssennnenense

This file has been download from www.datasheetcatalog.com mmc 4035 ae Binary — to — BCD converter | ol ul lr. bis PHT PLZ PIS Pia | fps Re Pa cock abc F~aIcrock al wt ae. 4035 ‘oo ¢ 1} ioe Vokengfive TENS REGISTER ‘ESET Fo woo P___o1 97 3 g WEE Tass | Pa) BcO apart T_| TENS Pore ro? PS BCD UNTS FS co TENS FORWARD. TO NEXT (BIDEC LOGIC) (BIDEC LOGIC) DECADE prt] Te nonts (=o TO TeNs{ “pre REGISTER) “py REGISTER} “*51- BIDEC logic Double sequence generator 01 a2 39s ‘bo | bf : is PIT PLZ PES aii Tycock MMC 4035 PIS S]z 4 STAGE. REGISTER RY patie Ror ag Ou rt fe PL2 a PH — alt ll Gg \\) v2 . 4002 Pre CONTROL Oe Oz Ox - 4930 030 | ire

This file has been download from www.datasheetcatalog.com nr State sequences Using a control fine (E) two different state sequences can be generated. For example, suppose the follo- wing two sequences are desired on command {control line). Control = E=0 Neen nearer eee e eee ne nn ee EEE EE EE EIEN EnnennnENGSnnEnnRNnD “Enema ] Qa Q, Qy Q Q, G2 Qs a A 8 c 18) A 8 c is) [o) is) is) [e] i} 15 1 1 1 1 1 41 ie) ie} ie] 414 oO ie) 4 4

2 Le) 1 ie} ie) 13 1 0 4 4

Ss 1 [¢) 4 (2) 10 i) 1 oO 4 10 oO 4 ie) 1 5 4 0 4 Qo 4 0 ie) 4 is) 1 4 1 i*) 4 9 4 0 ie} 4 6 is) 4 4 ie) 3 1 4 ie} is) 12 is} ie} 41 1 6 ie) 1 4 0 9g 4 0 Qa 4 13 1 ie 41 1 2 ie) 4 Q is} 1 4 4 is) a 4 0 is} 1 is} 7 4 4 4 [o} 8 ie) [e) is) 4 14 0 1 4 4 1 4 fe) Q i*) 12 iy 0 4 41 3 4 1 og ie} 8 oO i?) is} 1 7 4 4 4 [e) ee Ba