MMC4021

MMC4014 MICRO-ELECTRONICS | Alldatasheet

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This file has been download from www.datasheetcatalog.com Mi wwareteesven\\Vervenl='e' ve-Tex\\ Biinweteletetelcevela MMC 4014 Mmcaoe1 a RT 8-STAGE STATIC SHIFT REGISTERS: SYNCHRONOUS PARALLEL OR SERIAL INPUT /SERIAL OUTPUT: MMC 4014 ASYNCHRONOUS PARALLEL INPUT OR SYNCHRONOUS SERIAL INPUT/SERIAL OUTPUT: MMC 4021 GENERAL DésSCRIPTION When the PARALLEL/SERIAL .CONTROL input is high, data is jammed into the 8-stage register via the The MMC 4014, MMC 4021 series types are parallel input lines and synchronous with the positive 8-stage parallel-or serial-input/serial-output reais transition of the clock line. ters having common CLOCK and PARALLEL/SERIAL In the MMC 4021, the CLOCK input of the internal CONTROL inputs, a single SERIAL data input, and in- stage is “forced” when asynchronous parallel. entry dividual earailel “JAM"” inputs to each register is made, stage. Each register stage is a D type, master-slave Register expansion using multiple package is permit- flip-flop; in addition to an output from stage 8, “Q" ted, outputs are also available from stage 6 and 7., The MMC _ 4014, MMC 4021 series types are sup- Parallel as well as serial entry is made into the regis- plied in 16-lead dual-in-line plastic or ceramic pac- ter Sake with the positive clock line transi- kage. tion in the MMC 4014. In the MMC 4021 serial entry is synchronous with the clock but parallel entry is asynchronous. FEATURES In both types, entry is controlled by the PARALLEL/ SERIAL CONTROL input. ; @ Medium speed operation-12 MHz (typ.) clock rate. When the PARALLEL/SERIAL CONTROL input is low, at Vop—Ves = 10 V data is serially shifted into the 8-stage reget @ Fully static operation synchronously with the positive, transition of the @ 8 Master-Slave flip-flops plus output buffering and clock line. control gating a ABSOLUTE MAXIMUM RATINGS Vop" Supply voltage: G and H types -0.5 to 20 Vv

0 E and F types “05 to 18 Vv

Vi {nput voltage -O.5to VpptO.5 Vv \\ DC input current {any one input) £10 mA Brot Total power dissipation (per package) 200 mw Dissipation per output transistor for Ta = full package-temperature range 100 mw Ta Operating temperature: G and H types -55 to 125 Ge} E and F types -40 to 85 °C Tota Storage temperature -65 to 150 °c * All voltage values are referred to Vgg pin voltage RECOMMENDED OPERATING CONDITIONS Vop* Supply voltage: G and H types 3to 18 Vv °° y E and F types 3to 15 OV t oes GandH sto Bok Operating temperature : an types - 0 “ E and F types “40 to a °C eee CONNECTION DIAGRAM TRUTH TABLE For 4014 Pi-8 G1 16D Yoo ao G2 BpPr7 ~~ x 1 0 0 0 0 os (3 Tey PI-6 x us i i W : W PLS ~ x 4 Oo + ie) 4 OLE p War x 1 1] 1 1 1 pi-3 GS po? al 0 (ej x x ie) G,-1 P+? Os ni] SERIAL IN ~~ 4 ie) x x 1 Q,-1 pi 7 vf} clock x x x x Q, Q, | NC \\s Ge 5p Haha X = Dont care case NC = No change

This file has been download from www.datasheetcatalog.com MMC 9014 MMC 4024 ce nA RMS dal LOGIC DIAGRAMS AND TRUTH TABLE For MMC 4021 [eases] Eft x x 1 o | 0 i) i) x x 1 0) 1 fe) 1 x x 1 1 {| 0 1 [e) x x 1 1 1 1 1 S ) fs) x | x QO 4G,1 1 ) x | x 1 Qy1 ae x oO x [| Xx Gi Gy_} NC X =: Don't care case NU = No change MMC 4014 Pt P2 P3 Ps PS PB PB SERIAL Y ] | Y ] ae S t anak - Dob at—b ap” DT Oo seal a V VV CONTROL P a a ® 1D) Q6 Q7 a8 | a a La y 4) D y p p ATH * Ge ° Kt a ( cu ica MMC 4021 Pt 2 P3 Py PS Ps P? PB V/ Y 7 VV \\V, VV SERAL ] i NP , O{>e ne Ge Gee moe CONTROL > a Th Y V cL @) (@) 06 ra a8 Pp a = fn TO 5 y Popp a eo in cL ce a

_This file has been download from www.datasheetoatalog.com | MMC 4014 MMC 4021 STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions) TEST CONDITIONS VALUES nial na ae I Quiescent GHjO/ 5 5 5 0.04 5 150 current, types|0/10 10 10 0.04} 10 300 0715 15 20 0.04; 20 -600 0/20 20 100 0.08 | 100 3000 aA EF {0/5 5 20 0.04) 20 150 types /0/10 10 40 aoa} 40 300 s 0/15 15 80 0.04] 80 600 Von Output high a/v 5 <17 5 [495 495 4.95 voltage 0/10 <1] 10 |995 9.95 9.95 Vv 0/15 <1] 15 114.95 1495 14.95 voltage 10/0 <1] 10 0.05 0.05 0.05} v 15/0 <1] 15 0.05 0.05 0.05 Vin Input high 09/45} 1 § 735 35 35 voltage 4/9 <1 10 | 7 7 7 Vv 15/13.5) <1] 15 ]11 11 11 Vit Input low 45/05} <1 b} 15 15 1.5 voltage 9/1 <1} 10 3 3 3 Vv 13.5/1.5} <1 15 4 4 4 low Output GHIO/ 5 25 5 2 1.6 |-32 ~1.15 drive types|O/ 5 46 5 }|-064 -O.51]-1 ~0.36 current, 0/10 3.5 10 1.6 1.3] 26 -09 0/15! 13.5 15 1-42 -34) 68 ~2.4 n my 0/15] 135 15 | 36 -30 |-68 -24 lor Output GHIO/ 5 04 S | 064) 051} 1 0.36 sink types 10/10 Os 10 | 16 13 | 26 ag current o/15 15 18 | 42 34 | 68 24 a m EF {0/5 04 5 | 052 044).1 0.36 types J0/10 05 10 | 1.3 4.1 | 26 og 0/15 15 15 | 36 30 | 68 24 tie hy Input GH log +014 +10 5} +0.1 +1 leakage types. Any uA current F types Cc Input. capacitance Any input 5} 75 pF * TLow = ~58°C for G. H devices; -40°C for E, F devices. * Tracy = +125°C for G, H devices: +85°C for E, F devices. The Noise Margin for both “1” and “0” level is: 1.Vimun. with Vop = SV 2 V min. with Vpp = 10 V 25 Vmin. with Vog = 15 V s,s eee Ka)

_ eee DYNAMIC ELECTRICAL GHARACTERISTICS (T, = 25°C, C, = 50 pF, Ry = 200 kohm, typical temperature coefficient for all Vop = 0.3% /°C values, all input rise and ‘all times= 20 ns} TEST PARAMETER CONDITIONS eee UNIT [Yoo ran [oe [ea] tpi. Propagation delay time ts) 160 320 tpn. 10 80 | 160 | os 15 60 120 try. Transition time 5 100 200 trun 10 50 | 100 | ns 15 40 80 fer’ Maxiraum clack input frequency Ss 3 6 10 6 12 MHz 1S 85 17 ty Clock pulse width 5 180 30 10 80 40 ns 15 50 25 ee — t,t; Clock input rise or fall time i) 15 10 15 us 15 15 Csetup Setup time, serial input (ref. to CL) 5) 120 60 10 80 40 ns 415 60 30 toetup Setup time, parale! inputs (4014) (ref. to CU &) 80 40 10 50 25 ns 15 40 20 tsetup Setup time, parallel inputs (4021) i) 50 25 10 30 15 ns 15 20 10 tsetup Setup time, parallel /serial contro! (4014) 5 160 90 (ref. to CU) 10 80 40 ns 15 60 30 Uhoig Hold time, serial in, parallet in, te) parallel /serial control 10 ns tw P/S Pulse width (4021) 5 160 80 . 10 80 40 ns 15 50 25 trem P/S Removal, time (4021) (ref. to CU is} 280 140 10 140 70 ns 15 100 50 * If more then one unit is cascated t,CL should be made fess than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. eee