MK2049-45SI

MK2049-45 ICST | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Features

• Packaged in 20 pin SOIC
• 3.3 V + 5% operation
• Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
• Locks to 8 kHz + 100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs
• Exact internal ratios enable zero ppm error
• Output rates include T1, E1, T3, E3, and OC3 submultiples
• Available in Pb (lead) free package
• See also the MK2049-34 and MK2049-36 Block Diagram Charge Pump VCXO X2X1ISET CAP2 Feedback Divider (N) Reference Divider (used in buffer mode only) ICLK Reference Divider Phase Detector VCXO PLL Feedback Divider VCO Translator PLL CLK CAP1 Output Divider Divide by 2 CLK/2 RS RSET CP CS Optional Crystal Load Caps Divider Value Look-up TableFS3:0 CL CL External Pullable Crystal

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Pin Assignment Pin Descriptions FS1 FS0 RES VDD CAP2 FCAP VDD GND CAP1 VDD GND GND CLK ICLK CLK/2 FS3 8k FS2 Pin Number Pin Name Pin Type Pin Description 1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 2 X2 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2. 3 X1 Input Crystal connection. Connect to a MHz crystal as shown in table on page 2. 4 VDD Power Power supply. Connect to +3.3V. 5 FCAP - Filter capacitor. Connect a 1000 pF ceramic capacitor to ground. 6 VDD Power Power supply. Connect to +3.3V.

7 GND Power Connect to ground

8 CLK Output Clock output determined by st atus of FS3:0 per tables on page 2. 9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of CLK. 10 8k Output Recovered 8 kHz clock output. 11 FS2 Input Frequency select 2. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 12 FS3 Input Frequency select 3. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. 13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND Power Connect to ground. 15 VDD Power Power Supply. Connect to +3.3V.

16 CAP1 Loop

Connect the loop filter capacitors and resistor between this pin and CAP2. 17 GND Power Connect to ground.

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Output Decoding Table - External Mode (MHz) Output Decoding Table - Buffer Mode (MHz) 0 = connect directly to ground, 1 = connect directly to VDD Crystal is connected to pins 2 and 3; clock input is applied to pin 13. Functional Description The MK2049-45 is a clock generator IC that generates an output clock directly from an internal VCXO circuit which works in conjunction with an external quartz crystal. The VCXO is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an input reference clock. The MK2049-45 is configured to provide a high frequency communications reference clock output from an 8 kHz input clock or to jitter attenuate and buffer a high frequency input clock. There are 14 selectable output frequencies and two buffer mode selections. Please refer to the Output Clock Selection Table on Page 2. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal,

18 CAP2 Loop

Connect the loop filter capacitors and resistor between this pin and CAP1. 19 RES - Connect a resistor to ground. See table. 20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 2. Internal pull-up resistor. ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal Used (MHz) N 8 k H z 00001 . 5 4 43 . 0 8 88 k H z2 4 . 5 7 6 3 0 7 2 8 k H z 00012 . 0 4 84 . 0 9 68 k H z2 4 . 5 7 6 3 0 7 2 8 k H z 0010 2 2 . 3 6 8 4 4 . 7 3 6 8 k H z2 4 . 5 7 6 3 0 7 2 8 k H z 0011 1 7 . 1 8 4 3 4 . 3 6 8 8 k H z2 4 . 5 7 6 3 0 7 2 8 k H z 01001 9 . 4 43 8 . 8 88 k H z 1 9 . 4 4 2 4 3 0 8 k H z 0101 1 2 . 8 2 5 . 6 8 k H z 2 5 . 6 3 2 0 0 8 k H z 01102 5 . 9 25 1 . 8 48 k H z 1 7 . 2 8 2 1 6 0 8 k H z 01114 . 0 9 68 . 1 9 28 k H z1 6 . 3 8 4 2 0 4 8 8 k H z 1000 1 8 . 5 2 8 3 7 . 0 5 6 8 k H z2 4 . 7 0 4 3 0 8 8 8 k H z 1001 1 2 . 3 5 2 2 4 . 7 0 4 8 k H z2 4 . 7 0 4 3 0 8 8 8 k H z 1010 2 4 . 5 7 6 4 9 . 1 5 2 8 k H z1 6 . 3 8 4 2 0 4 8 8 k H z 1011 1 6 . 3 8 4 3 2 . 7 6 8 8 k H z1 6 . 3 8 4 2 0 4 8 8 k H z 11001 7 . 2 83 4 . 5 68 k H z 1 7 . 2 8 2 1 6 0 8 k H z 1101 6 2 . 5 1 2 5 8 k H z 2 5 3 1 2 5 Pin Number Pin Name Pin Type Pin Description ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N 2 0 - 5 0 1110 I C L K 2 * I C L K N / A I C L K / 2 3 1 0 - 2 5 1111 I C L K / 2 I C L K N / A I C L K3

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 the MK2049-45 is able to generate a low jitter, low phase-noise output clock within a low bandwidth PLL. This serves to provide input clock jitter attenuation and enables stable operation with a low frequency reference clock. The VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth.

Application Information

Output Frequency Configuration The MK2049-45 is configured to generate a set of output frequencies from an 8 kHz input clock. Please refer to the Output Clock Selection Table on Page 2. Input bits FS3:0 are set according to this table, as is the external crystal frequency. Please refer to the Quartz Crystal section on this page regarding external crystal requirements. Quartz Crystal It is important that the correct type of quartz crystal is used with the MK2049-45. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The MK2049-45 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The MK2049-45 incorporates variable load capacitors on-chip which “pull”, or change, the frequency of the crystal. The crystals specified for use with the MK2049-45 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF . To achieve this, the layout should use short traces between the MK2049-45 and the crystal. A complete description of the recommended crystal parameters in the ICS application note, MAN05 To obtain a list of qualified crystal devices please visit our website at: http://www.icst.com/products/telecom/vcxocrystals.htm PLL Loop Filter Components All analog PLL circuits use a loop filter to establish operating stability. The MK2049-45 uses external loop filter components for the following reasons: 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Referencing the External Component Schematic on this page, the external loop filter is made up of components R S, CS and CP. RSET establishes PLL charge pump current and therefore influences loop filter characteristics. Tools for optimizing the values of these four components can be found at: http://www.icst.com/products/telecom/ CAP2 CAP1 0.0003 µF 820 kohms 0.1 µF Figure 3. Typical Loop Filter

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Charge Pump Current Table Special considerations must be made in choosing loop components CS and CP. These recommendations can be found at http://www.icst.com/products/telecom/loopfiltercap.htm Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. (The optional series termination resistor is not shown in the External Component Schematic.) Decoupling Capacitors As with any high performance mixed-signal IC, the MK2049-45 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK2049-45 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. Recommended Power Supply Connection for Optimal Device Performance Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as C L in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Please refer to MAN05 for the procedure to determine capacitor values. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01 µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. C P should be closest to the device. Coupling of noise from other system RSET (kΩ) Charge Pump Current (ICP) (µA) 13.02 139 15 125 16 119 18 109 20 100 22 93 24 86 27 68 36 56 47 43 56 35 75 28 100 22 150 15 200 12 Connection to 3.3V Power Plane Ferrite Bead Bulk Decoupling Capacitor (such as 1 µF Tantalum) VDD Pin VDD Pin VDD Pin 0.01 µF Decoupling Capacitors

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI the 33 Ω series termination resistor, if needed, should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK2049-45. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. MAN05 may also be referenced for additional suggestions on layout of the crystal section. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2049-45. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 °C Storage Temperature -65 to +150 °C Junction Temperature 125 °C Soldering Temperature 250 °C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 °C Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.3 3.45 V Supply Current IDD Clock outputs unloaded, VDD = 3.3V 25 mA Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Input High Current I IH VIH = VDD -10 +10 µA Input Low Current I IL VIL = 0 -10 +10 µA Input Capacitance, except X1 C IN 7p F Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -8 mA 2.4 V Output Low Voltage V OL IOL = 8 mA 0.4 V Short Circuit Current I OS ±50 mA VIN, VCXO Control Voltage V XC 0V D D V Parameter Symbol Conditions Min. Typ. Max. Units VCXO Crystal Pull Range f XP Using Recommended Crystal -115 +115 ppm Input Jitter Tolerance t ji In reference to input clock period 0.4 UI Input pulse width (1) t pi 10 ns Output Duty Cycle (% high time) tOD Measured at VDD/2, CL=15pF 40 60 % Output Rise Time t OR 0.8 to 2.0V, CL=15 pF 1.0 ns Output Fall Time t OF 2.0 to 0.8V, CL=15 pF 1.0 ns Skew, ICLK to Output Clock Note 2 tIO All output clock selections except 1.544 and 2.048 MHz -5 +5 ns Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) t jf Referenced to Mitel/Zarlink MT9045, Note 3 400 ps

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Note 1: Minimum high or low time of input clock. Note 2: For the 1.544 MHz and 2.048 MHz output selections, the input to output clock skew is not controlled nor predictable and will change between power up cycles. Because it is dependent on the phase relationship between the output and feedback divider states following power up, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or MK2069 products. Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode (SEL2:0 = 100, 19.44 MHz external crystal). Marking Diagram Marking Diagram (Pb free) Notes: 2. YYWW is the last two digits of the year and the week that the part was assembled. 3. “LF” designates Pb (lead) free package. Timing Jitter, Filtered 65kHz-1.3MHz (OC-3) t jf Referenced to Mitel/Zarlink MT9045, Note 3 230 ps Frequency Error Relative to ICLK 0 ppm Nominal Output Impedance Z OUT 20 Ω Parameter Symbol Conditions Min. Typ. Max. Units 1 10 1120 MK2049-45SI YYWW 1 10 1120 MK2049-45SILF YYWW

3.3V Communications Clock PLL Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK2049-45 Package Outline and Package Dimensions (20 pin SOIC, 300 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK2049-45SI MK2049-45SI Tubes 20-pin SOIC -40 to +85 ° C MK2049-45SITR MK2049-45SI Tape and Reel 20-pin SOIC -40 to +85 ° C MK2049-45SILF MK2049-45SILF Tubes 20-pin SOIC -40 to +85 ° C MK2049-45SILFTR MK2049-45SILF Tape and Reel 20-pin SOIC -40 to +85 ° C D E H BeA1 Index Area A CL h x 45 o Millimeters Inches Symbol Min Max Min Max A- - 2 . 6 5 - - 0 . 1 0 4 A2 2.05 2.55 0.081 0.100 B 0.33 0.51 0.013 0.020 C 0.18 0.32 0.007 0.013 D 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 Basic 0.050 Basic H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8°