MK2049-34 ICST | Alldatasheet

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Technical content

3.3 V Communications Clock PLL

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

  • Packaged in 20 pin SOIC
  • 3.3 V ±5% operation
  • Fixed I/O phase relationship on all selections
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
  • Accepts multiple inputs: 8 kHz backplane clock, Loop Timing frequencies, or 10-36 MHz
  • Locks to 8 kHz ±100 ppm (External mode)
  • Buffer Mode allows jitter attenuation of 10–36 MHz input and x1/x0.5 or x2/x4 outputs
  • Exact internal ratios enable zero ppm error
  • Output clock rates include T1, E1, T3, E3, ISDN, xDSL, and OC3 submultiples
  • See the MK2049-01, -02, and -03 for more selections at VDD = 5 V The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks frequency-locked and phase-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-34 can also accept a T1 or E1 input clock and provide the same output for loop timing. All outputs are frequency locked together and to the input. This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-34 is ideal for filtering jitter from 27 MHz video clocks or other clocks with high jitter. ICS/MicroClock can customize these devices for many other different frequencies. Contact your ICS/MicroClock representative for more details. Block Diagram Description Features VDD GND PLL Clock Synthesis, Control, and Jitter Attenuation Circuitry Output Buffer Output Buffer External/ Loop Timing Mux FS3:0 Clock Input CAP1 CAP2 CLK CLK/2 Output Buffer 8 kHz (External Mode only) Crystal Oscillator Reference Crystal X1 3 3 RES FCAP

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com Pin Descriptions Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter connections Pin Assignment 20 pin (300 mil) SOIC VDD GND VDD GND 1110

9 FS3

Number Name Type Description 1 FS1 I Frequency Select 1. Determines CLK input/outputs per tables on page 4. 2 X2 XO Crystal connection. Connect to a MHz crystal as shown in the tables on page 4. 3 X1 XI Crystal connection. Connect to a MHz crystal as shown in the tables on page 4. 4 VDD P Connect to +3.3V. 5 FCAP - Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground. 6 VDD P Connect to +3.3V. 7 GND P Connect to ground. 8 CLK O Clock output determined by status of FS3:0 per tables on page 4. 9 CLK/2 O Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK. 10 8K O Recovered 8 kHz clock output. 11 FS2 I Frequency Select 2. Determines CLK input/outputs per tables on page 4. 12 FS3 I Frequency Select 3. Determines CLK input/outputs per tables on page 4. 13 ICLK I Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND P Connect to ground. 15 VDD P Connect to +3.3V. 16 CAP1 LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP2. 17 GND P Connect to ground. 18 CAP2 LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP1. 19 RES - Connect a 10-200k Ω resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app. 20 FS0 I Frequency Select 0. Determines CLK input/outputs per tables on page 4.

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (Note 1) ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs -0.5 VDD+0.5 V Ambient Operating Temperature MK2049-34SI -40 85 °C Soldering Temperature Max of 10 seconds 250 °C Storage Temperature -65 150 °C DC CHARACTERISTICS (VDD = 3.3 V unless noted)DC CHARACTERISTICS (VDD = 3.3 V unless noted) Operating Voltage, VDD 3.15 3.3 3.45 V Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Output High Voltage, VOH, CMOS level IOH=-4 mA VDD-0.4 V Output High Voltage, VOH IOH=-8 mA 2.4 V Output Low Voltage IOL=8 mA 0.4 V Operating Supply Current, IDD No Load, VDD=3.3 V 7 mA Short Circuit Current Each output ±50 mA Input Capacitance, FS3:0 5 pF AC CHARACTERISTICS (VDD = 3.3 V unless noted)AC CHARACTERISTICS (VDD = 3.3 V unless noted) Input Frequency, External Mode ICLK 8.000 kHz Input Clock Pulse Width 10 ns Propagation Delay ICLK to CLK 0 6 ns Output-Output Skew CLK to CLK/2 150 ps Output Clock Rise Time 0.8 to 2.0 V 2 ns Output Clock Fall Time 2.0 to 0.8 V 2 ns Output Clock Duty Cycle, High Time At VDD/2, except 8K 40 60 % Actual mean frequency error versus target Any clock selection 0 0 ppm Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. Electrical Specifications

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

  • 0 = connect directly to ground, 1 = connect directly to VDD.
  • Crystal is connected to pins 2 and 3; clock input is applied to pin 13. MK2049-34 Output Decoding Table – External Mode (MHz) ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal 8 kHz 0 0 0 0 1.544 3.088 8 kHz 12.352 8 kHz 0 0 0 1 2.048 4.096 8 kHz 12.288 8 kHz 0 0 1 0 22.368 44.736 8 kHz 11.184 8 kHz 0 0 1 1 17.184 34.368 8 kHz 11.456 8 kHz 0 1 0 0 19.44 38.88 8 kHz 9.72 8 kHz 0 1 0 1 16.384 32.768 8 kHz 8.192 8 kHz 0 1 1 0 17.664 35.328 8 kHz 17.664 8 kHz 0 1 1 1 18.688 37.376 8 kHz 9.344 8 kHz 1 0 1 0 7.68 15.36 8 kHz 15.36 8 kHz 1 0 1 1 10.752 21.504 8 kHz 10.752 8 kHz 1 1 0 0 10.24 20.48 8 kHz 10.24 8 kHz 1 1 0 1 38.88 77.76 8 kHz 9.72 ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal 1.544 1 0 0 0 1.544 3.088 N/A 12.352 2.048 1 0 0 1 2.048 4.096 N/A 12.288 MK2049-34 Output Decoding Table – Loop Timing Mode (MHz) ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal 19 - 36 1 1 1 0 ICLK/2 ICLK N/A ICLK/2 10 - 18 1 1 1 1 2*ICLK 4*ICLK N/A ICLK MK2049-34 Output Decoding Table – Buffer Mode (MHz)

with the rising edge of the 8 kHz ICLK; refer to Figure 1 for more details. used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs. the input and output, a requirement in many communications systems. Figure 1. MK2049-34 Input and Output Clock Waveforms

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com Measuring Zero Delay on the MK2049 The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth--on the order of a few Hertz. Since most 8 kHz input clocks will have high jitter, this can make measuring the input-to-output skew (zero delay feature) very difficult. The MK2049 is designed to reject the input jitter; when the input and output clocks are both displayed on an oscilloscope, they may appear not to be locked because the scope trigger point is constantly changing with the input jitter. In fact, the input and output clocks probably are locked, and the MK2049 will have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies. Frequency Locking to the Input In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified output frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.

MK2049. You may also refer to MAN05 for additional suggestions on layout of the crystal section. Figure 2. Typical MK2049-34 Layout Cutout in ground and power plane. Route all traces away from this area.

performance and reliability, the layout guidelines shown on the previous page must be closely followed. to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal. achieve this, the layout should use short traces between the MK2049 and the crystal. mechanical energy is converted directly to voltage noise on the VCO input. Figure 3. Loop Filter Component Values

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com Parameter Minimum Typical Maximum Units Operating Temperature Range 0 25 70 °C Initial Accuracy at 25 C -20 20 ppm Temperature stability -30 30 ppm Aging, first year -5 5 ppm Aging, 10 years -20 20 ppm Load Capacitance Note 1 Shunt Capacitance, C0 7 pF Motional Capacitance, C1 none none pF C0/C1 ratio 250 none Equivalent Series Resistance 35 Ohms Crystal Specifications *This ratio decreases for lower crystal frequencies. EXTERNAL COMPONENT SELECTION (continued) Note 1: Nominal crystal load capacitance specifications varies with frequency. Contact the ICS MicroClock applications department at (408)297-1201 Note 2: The third overtone mode of the crystal and all spurs must be >200 ppm away from 3x the fundamental resonance shown in the table below. For recommended crystal devices, please contact the ICS MicroClock application department at 408-297-1201.

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com Determining the Crystal Frequency Adjustment Capacitors To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a frequency counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified load capacitance, C L . To determine the value of the crystal capacitors: 1. Connect VDD of the MK2049 to 3.3 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK or CLK/2 output . 2. Adjust the voltage on pin 18 to 3.3 V. Measure and record the frequency of the same output. To calculate the centering error: Centering error = 10 6 (f3.3V − ftarget) + (f0.0V - ftarget) ftarget     - errorxtal Where ftarget = 44.736000 MHz, for example, and error xtal = actual initial accuracy (in ppm) of the crystal being measured. If the centering error is less than ±15 ppm, no adjustment is needed. If the centering error is more than 15 ppm negative, the PC board has too much stray capacitance and will need to be redone with a new layout to reduce stray capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS MicroClock for details.) If the centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2*(centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than ±15 ppm). The MicroClock Applications department can perform this procedure on your board. Call us at 408–295–9800, and we will arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We will calculate the value of capacitors needed. EXTERNAL COMPONENT SELECTION (continued)

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

Ordering Information

Part/Order Number Marking Package Temperature MK2049-34SI MK2049-34SI 20 pin SOIC -40 to 85 °C MK2049-34SITR MK2049-34SI Add Tape & Reel -40 to 85 °C Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.) While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 20 pin SOIC Inches Inches Millimeters Millimeters Symbol Min Max Min Max A -- 0.104 -- 2.65 B 0.013 0.020 0.33 0.51 C 0.007 0.013 0.18 0.33 D 0.496 0.512 12.60 13.00 E 0.291 0.299 7.40 7.60 e .050 BSC .050 BSC 1.27 BSC 1.27 BSC H 0.394 0.419 10.01 10.64 h 0.01 0.029 0.25 0.74 L 0.016 0.050 0.41 1.27 B D E H e A1 C A h x 45° L INDEX AREA 1 2