MK1725 ICST | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 6

Technical content

Features

  • Packaged in 16-pin TSSOP
  • Available in Pb (lead) free package
  • Replaces a spread spectrum clock generator and a buffer
  • Input clock or crystal frequency of 20-34 MHz
  • Output frequency of 20-136 MHz
  • Four spread spectrum clock outputs
  • Duty cycle of 45/55
  • Operating voltage of 3.3 V
  • Advanced, low power CMOS process Block Diagram PLL/Clock Synthesis and Spread Spectrum Circuitry S3:0 CLK1:4 Crystal Oscillator X1/ICLK 20-34 MHz crystal or clock GND VDD PDTS Optional crystal capacitors.

Quad Output Spread Spectrum Clock Generator MDS 1725 C Revision 021605 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com MK1725 Pin Assignment CLK Output Selection Table Pin Descriptions VDD VDD GND PDTS VDD GND CLK3 CLK1 CLK4 CLK2 16 pin (173 mil) TSSOP CLK1:4 Multiplier Spread % -1% -0.5% +/- 0.5% +/- 0.25% -1% -0.5% +/- 0.5% +/- 0.25% -1% -0.5% +/- 0.5% +/- 0.25% OFF OFF OFF TEST TEST Pin Number Pin Name Pin Type Pin Description Input Connect to a 20 - 34 MHz crystal or clock input. Input Select pin 0. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. Input Select pin 3. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. VDD Power Connect to +3.3V. GND Power Connect to ground. Input Select pin 1. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. CLK1 Output Clock 1 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. CLK2 Output Clock 2 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. CLK3 Output Clock 3 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state.

Quad Output Spread Spectrum Clock Generator MDS 1725 C Revision 021605 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com MK1725 External Components Decoupling Capacitor As with any high performance mixed-signal IC, the MK1725 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with an 18 pF load capacitance, each crystal capacitor would be 24 pF [(18-6) x 2] = 24. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33Ω series termination resistor (if needed) should be placed close to the clock outputs. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1725. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. CLK4 Output Clock 4 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. GND Power Connect to ground. VDD Power Connect to +3.3V. Input Select pin 2. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. PDTS Input Power Down Tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. VDD Power Connect to +3.3V. Input 20MHz-34MHz crystal input. Float for clock input. Pin Number Pin Name Pin Type Pin Description

Quad Output Spread Spectrum Clock Generator MDS 1725 C Revision 021605 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com MK1725 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1725. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Item Rating Supply Voltage, VDD 5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Parameter Min. Typ. Max. Units Ambient Operating Temperature +70 Power Supply Voltage (measured in respect to GND) +3.135 +3.3 +3.465 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.3 3.465 V Supply Current IDD 20M in S3:0=[0100] mA Input High Voltage VIH Input selects V Input Low Voltage VIL Input selects 0.8 V Input High Voltage VIH ICLK VDD/2+1 V Input Low Voltage VIL ICLK VDD/2-1 V Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA 0.4 V Short Circuit Current IOS Clock outputs ±70 mA Input Capacitance CIN pF Nominal Output Impedance ZOUT Ω Internal Pull-up Resistor RPU PDTS pin 360 kΩ Internal Pull-down Resistor RPD Clock outputs; S3:0 510 kΩ

Quad Output Spread Spectrum Clock Generator MDS 1725 C Revision 021605 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com MK1725 Unless stated otherwise, VDD = 3.0 V ±5%, Ambient Temperature 0 to +70°C Note 1: Measured with a 15 pF load. Thermal Characteristics Marking Diagram Notes: 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. “L” denotes Pb (lead) free package. 4. Bottom marking: (origin). Origin = country of origin of not USA. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency fIN Crystal or clock input MHz Output Rise Time tOR 20% to 80%, Note 1 1.2 ns Output Fall Time tOF 80% to 20%, Note 1 1.0 ns Output Clock Duty Cycle At VDD/2, Note 1 1X, 2X modes at VDD/2, Note 1 4X mode Absolute Clock Period Jitter tJ Cycle to cycle, Note 1 150 ps Modulation Frequency fmod kHz Output to Output Skew Non-spread modes 250 ps Output Enable Time tOE PDTS high to output spread profile stable 2.6 ms Output Disable Time tOD PDTS low to tri-state ns Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air °C/W θJA 1 m/s air flow °C/W θJA 3 m/s air flow °C/W Thermal Resistance Junction to Case θJC °C/W MK1725GL YYWW

Quad Output Spread Spectrum Clock Generator MDS 1725 C Revision 021605 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●www.icst.com MK1725 Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK1725GLF see page 5 Tubes 16-pin TSSOP 0 to +70 °C MK1725GLFT Tape and Reel 16-pin TSSOP 0 to +70 °C INDEX AREA 1 2 D E SEATING PLANE A A A e - C - b aaa C c L Millimeters Inches Symbol Min Max Min Max A 1.20 0.047 0.05 0.15 0.002 0.006 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 4.90 5.1 0.193 0.201 E

6.40 BASIC

0.252 BASIC

4.30 4.50 0.169 0.177 e

0.65 Basic

0.0256 Basic

L 0.45 0.75 0.018 0.030 α aaa 0.10 0.004