MIRA130

MIRA130 AMSCO | Alldatasheet

Document overview

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Technical content

1.3 MP NIR Enhanced Global Shutter CMOS Image

v5-00 • 2022-Apr-05 Abstract This datasheet document describes the specification and functionalities of Mira130, a 1.3 MP global shutter NIR image sensor with excellent Quantum Efficiency in the near-infrared range. The main target application for this sensor is 3D-enabled consumer devices. The state-of-the-art NIR performance of Mira130 allows outstanding power consumption reduction of 3D systems in which this sensor is used.

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 2 Content Guide

3.2 RW (reconstructed wafer) Physical

3.3 Mira130 Fan-Out Package (for information

7 Electro-Optical Characteristics .. 21

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 3

1 General Description

Mira130 is a global shutter CMOS image sensor with NIR enhancement of the QE. It outputs monochrome images with an effective pixel array of 1080 H × 1280 V, and supports complex on-chip operations such as high dynamic range (HDR) mode, external triggering, windowing, horizontal or vertical mirroring. Its maximum frame rate is 120 fps at a full image resolution. On-chip registers can be accessed via the standard I2C interface.

1.1 Key Benefits & Features

Figure 1: Mira130 Key Benefits Benefits Features State-of-the-art NIR performance 56% QE at 850 nm, 36% QE at 940 nm HDR mode provides > 100 dB DR In-pixel HDR mechanism Motion blur robustness Global shutter pixel Standard camera interface MIPI CSI-2 / D-PHY High speed Up to 120 fps @ 10-bit data Optimized for size constrained applications 1.3 MP with 2.7 μm pixels

1.2 Other Features

• Support external triggering and multiple sensors synchronization
• Binning mode for increased full well charge
• AEC/AGC, minimum exposure time less than 1 line
• LED strobe
• Horizontal and vertical windowing
• 28x analog gain, and 32x digital gain
• High sensitivity
• Programmable registers through I2C
• Low power consumption
• Build-in temperature sensor

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1.3 Applications

• 3D structured light, 3D Active Stereo systems
• 2D NIR imaging
• Machine vision
• Barcode scanners
• Motion monitoring

1.4 Block Diagram

The functional blocks of this device are shown below: Figure 2: Functional Blocks of Mira130 Pixel Array 1080H x 1280V Analog Process Digital Process Row Input Column Input Block Diagram PLL EXTCLK System Control I2C Slave XSHUTDN SCL SDATRIG MIPI/LVDS LED Strobe PWDNB

Ordering Information

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2 Ordering Information

Ordering Code Package Marking Delivery Form Delivery Quantity Mira130-1QM2D0 Bare die N/A Reconstructed wafer 1 wafer

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3 Packaging Information

3.1 Mira130 Die Information

3.1.1 Mira130 Die Size

Figure 3: Mira130 Die Pinout (1) The COB center of the chip is not coincident with the optical center. Pixel Center (20,-25) is the same as the optical center. The units are in µm.

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3.1.2 Mira130 Pad Description

Figure 4: Pad Description of Mira130 Die Pad # Pad Name X-Axis Y-Axis Pin Type Description 1 AVDD -1791.5 1809 Power 2.5 V Analog Power Supply 2 AVDD -1791.5 1688.4 Power 2.5 V Analog Power Supply 3 AGND -1791.5 1567.8 GND Analog Ground 4 ATM -1791.5 1447.2 - NC 5 DVDD -1791.5 1326.6 Power 1.2 V Digital Power Supply 6 DVDD -1791.5 1206 Power 1.2 V Digital Power Supply 7 DOGND -1791.5 1085.4 GND I/O Ground 8 DOGND -1791.5 964.8 GND I/O Ground 9 TRIGL/FSYNC -1791.5 844.2 Input/ Output External Triggering of HDR Long Exposure/SYNC 10 LEDSTROBE -1791.5 723.6 Output LED STROBE Signal 11 XSHUTDOWN -1791.5 603 Input XSHUTDOWN Signal Input (internal pull- up, active low) 12 TM -1791.5 482.4 Input Connect to the DOGND pin 13 AGND -1791.5 361.8 GND Analog Ground 14 AVDD -1791.5 241.2 Power 2.5 V Analog Power Supply 15 TRIGS -1791.5 120.6 Input External Triggering of HDR Short Exposure 16 GPIO -1791.5 0 - NC 17 DOVDD -1791.5 -120.6 Power 1.8 V I/O Power Supply 18 DOGND -1791.5 -241.2 GND I/O GROUND 19 AVDD -1791.5 -361.8 Power 2.5 V Analog Power Supply 20 NC -1791.5 -482.4 - NC 21 VREFH -1791.5 -603 Output Internal Reference Voltage (connect an external capacitor to the AGND pin) 22 NC -1791.5 -723.6 - NC 23 AVDD -1791.5 -844.2 Power 2.5 V Analog Power Supply 24 AGND -1791.5 -964.8 GND Analog Ground 25 AGND -1791.5 -1085.4 GND Analog Ground 26 VREFN -1791.5 -1206 Output Internal Reference Voltage (connect an external capacitor to the AGND pin) 27 VREFN1 -1791.5 -1326.6 Output Internal Reference Voltage (connect an external capacitor to the AGND pin) 28 GS_VREF -1791.5 -1447.2 Output Internal Reference Voltage (connect an external capacitor to the AGND pin) 29 AVDD -1791.5 -1567.8 Power 2.5 V Analog Power Supply 30 DVDD -1791.5 -1688.4 Power 1.2 V Digital Power Supply 31 DOGND -1791.5 -1809 GND I/O GROUND

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 8 Pad # Pad Name X-Axis Y-Axis Pin Type Description 32 DOGND 1791.5 -1809 GND I/O GROUND 33 DVDD 1791.5 -1688.4 Power 1.2 V Digital Power Supply 34 MD3P 1791.5 -1567.8 Output MIPI Data 3 Positive 35 MD3N 1791.5 -1447.2 Output MIPI Data 3 Negative 36 DOGND 1791.5 -1326.6 GND I/O GROUND 37 MD1P 1791.5 -1206 Output MIPI Data 1 Positive 38 MD1N 1791.5 -1085.4 Output MIPI Data 1 Negative 39 DVDD 1791.5 -964.8 Power 1.2 V Digital Power Supply 40 MCP 1791.5 -844.2 Output MIPI Clock Positive 41 MCN 1791.5 -723.6 Output MIPI Clock Negative 42 DOGND 1791.5 -603 GND I/O Ground 43 DOGND 1791.5 -482.4 GND I/O Ground 44 DOVDD 1791.5 -361.8 Power 1.8 V I/O Power Supply 45 DVDD 1791.5 -241.2 Power 1.2 V Digital Power Supply 46 MD0P 1791.5 -120.6 Output MIPI Data 0 Positive 47 MD0N 1791.5 0 Output MIPI Data 0 Negative 48 DOGND 1791.5 120.6 GND I/O Ground 49 MD2P 1791.5 241.2 Output MIPI Data 2 Positive 50 MD2N 1791.5 361.8 Output MIPI Data 2 Negative 51 DVDD 1791.5 482.4 Power 1.2 V Digital Power Supply 52 DOVDD 1791.5 603 Power 1.8 V I/O Power Supply 53 SDA 1791.5 723.6 Input/ Output I2C Data Line (open drain) 54 DOGND 1791.5 844.2 GND I/O Ground 55 SCL 1791.5 964.8 Input I2C Clock 56 EXTCLK 1791.5 1085.4 Input Clock Input 57 SID0 1791.5 1206 Input I2C Device ID 0 58 SID1 1791.5 1326.6 Input I2C Device ID 1 59 DVDD 1791.5 1447.2 Power 1.2 V Digital Power Supply 60 DOGND 1791.5 1567.8 GND I/O Ground 61 AGND 1791.5 1688.4 GND Analog Ground 62 AVDD 1791.5 1809 Power 2.5 V Analog Power Supply (1) All pads bonding area is 70 µm x 70 µm. Units are in µm.

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3.2 RW (reconstructed wafer) Physical Dimensions

Max total die count: 8-inch: 1593 ea. Film frame: Compact disco stainless SUS420 Carrier tape: UV tape Figure 5: RW Physical Dimensions Figure 6: Wafer Dimensions Parameter Description Wafer Diameter 200 mm (8’’) Grinding Thickness 150 μm ± 10 μm Singulated Die Size X = 3750 μm ± 20 μm, Y = 4150 μm ± 20 μm Bond Pad Size X = 80 μm, Y = 88 μm

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 10 Parameter Description Bond Pad Opening X = 70 μm, Y = 70 μm Minimum Bond Pad Pitch 120.6 μm Optical Array (Optical center from die center) X = 20 μm, Y = 25 μm RW Offset (X1 - X2) ÷ 2 = 0 ± 5 mm; Placement Accuracy X,Y,Theta X, Y (±50 μm), Theta < 1° Maximum Total Die Count 8-inch: 1593 ea. RW Layout X = 47, Y = 43

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3.3 Mira130 Fan-Out Package (for information only)

3.3.1 Fan-Out Package Dimensions

The package drawing and dimensions are shown respectively on Figure 7 and Figure 8. Figure 7: Fan-Out Package Drawing Figure 8: Fan-Out Package Dimensions (in mm) Parameters Symbol Nominal Min Max Package Body Dimension Y A 7.800 7.700 7.900 Package Body Dimension X B 8.450 8.350 8.550 Package Height C 0.810 0.725 0.895 Ball Height C1 0.290 0.255 0.325 Package Body Thickness C2 0.520 0.470 0.570 Glass Thickness(with glue thickness) C3 0.220 0.210 0.230 Ball Diameter D 0.365 0.330 0.400 Die Body Dimension Y a 4.100 NA NA Die Edge To Ball Edge Dimension Y a1 1.368 1.343 1.393 Glass Package Body Dimension Y a2 4.942 4.917 4.967 A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 11 12 Side View C glue area c Top View(Ball Down) Back View(Ball Up) Chip center (-20,25) Optical Center =PKG center (0,0) A B a b Black material area Black material area Orientation Mark A1 Corner glue area 13 12345678910111213 A B C D E F G H J K L M

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 12 Parameters Symbol Nominal Min Max Slot Opening Dimension Y a3 4.000 NA NA Die Body Dimension X b 3.700 NA NA Die Edge To Ball Edge Dimension X b1 1.198 1.173 1.223 Glass Package Body Dimension X b2 4.402 4.377 4.427 Slot Opening Dimension X b3 3.353 NA NA Die Package Height c 0.167 0.152 0.182 Si Thickness c2 0.150 0.140 0.160 Gold Bump Height c1 0.017 0.012 0.022 Gold Bump Diameter d 0.075 0.070 0.080 Glue Area Width(Top) L1 NA NA 0.200 Glue Area Width(Bottom) L2 NA NA 0.400 Total Ball Count N 65 (6NC) Ball Pitch Y axis J1 0.650 Ball Pitch X axis J2 0.650 Edge to Ball Center Distance along Y S1 0.325 0.250 0.400 Edge to Ball Center Distance along X S2 0.325 0.250 0.400 (1) The center of the fan-out package is coincident with the optical center.

3.3.2 Fan-Out Package Pin List

Figure 9: Fan-Out Pin Description # Pin # Pin Name Pin Type Description

1 A1 NC - NC

2 A2 DVDD Power 1.2 V Digital Power Supply

3 A3 ATM - NC

4 A4 DOGND GND Analog/Digital GND

5 A5 AVDD Power 2.5 V Analog Power Supply 6 A6 AVDD Power 2.5 V Analog Power Supply

7 A7 DOGND GND Analog/Digital GND

8 A8 DOGND GND Analog/Digital GND

9 A9 DVDD Power 1.2 V Digital Power Supply

10 A10 SID1 Input I2C Device ID 1

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 13 # Pin # Pin Name Pin Type Description

11 A11 SID0 Input I2C Device ID 0

12 A12 EXTCLK Input Clock Input

13 A13 NC - NC

14 B1 DOGND GND Analog/Digital GND

15 B2 DVDD Power 1.2 V Digital Power Supply

16 B12 SCL Input I2C Clock

17 B13 SDA Input/Input I2C Data Line (open drain)

18 C1 TRIGL/FSYNC Input/Input External Triggering of HDR Long

19 C2 DOGND GND Analog/Digital GND

20 C12 DOGND GND Analog/Digital GND

21 C13 DOVDD Power 1.8 V I/O Power Supply

22 D1 XSHUTDOWN Input XSHUTDOWN Signal Input (internal pull-

up, active low)

23 D2 LEDSTROBE Output LED STROBE Signal

24 D12 DOVDD Power 1.8 V I/O Power Supply

25 D13 MD2N Output MIPI Data 2 Negative

26 E1 DOGND GND Analog /Digital GND

27 E2 TM Input Connect to DOGND pin

28 E12 DVDD Power 1.2 V Digital Power Supply

29 E13 MD2P Output MIPI Data 2 Positive

30 F1 TRIGS Input External Triggering of HDR Short

31 F2 AVDD Power 2.5 V Analog Power Supply

32 F12 DOGND GND Analog /Digital GND

33 F13 MD0N Output MIPI Data 0 Negative

34 G1 GPIO - NC

35 G2 DOVDD Power 1.8 V I/O Power Supply 36 G12 DVDD Power 1.2 V Digital Power Supply

37 G13 MD0P Output MIPI Data 0 Positive

38 H1 DOGND GND Analog GND/Digital GND

39 H2 AVDD Power 2.5 V Analog Power Supply 40 H12 DOVDD Power 1.8 V I/O Power Supply

41 H13 MCN Output MIPI Data Clock Negative

42 J1 NC - NC

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 14 # Pin # Pin Name Pin Type Description

43 J2 VREFH Output Internal Reference Voltage (connect an

external capacitor to the DOGND pin)

44 J12 DOGND GND Analog /Digital GND

45 J13 MCP Output MIPI Data Clock Positive

46 K1 NC - NC

47 K2 AVDD Power 2.5 V Analog Power Supply 48 K12 DVDD Power 1.2 V Digital Power Supply

49 K13 MD1N Output MIPI Data 1 Negative

50 L1 DOGND GND Analog/Digital GND

51 L12 DOGND GND Analog/Digital GND

52 L13 MD1P Output MIPI Data 1 Positive

53 M1 NC - NC

54 M2 VREFN Output Internal Reference Voltage (connect an

external capacitor to the DOGND pin)

55 M3 VREFN1 Output Internal Reference Voltage (connect an

external capacitor to the DOGND pin)

56 M4 GS_VREF Output Internal Reference Voltage (connect an

external capacitor to the DOGND pin) 57 M5 AVDD Power 2.5 V Analog Power Supply 58 M6 DVDD Power 1.2 V Digital Power Supply

59 M7 DOGND GND Analog GND/Digital GND

60 M8 DOGND GND Analog GND/Digital GND

61 M9 DVDD Power 1.2 V Digital Power Supply

62 M10 MD3P Output MIPI Data 3 Positive

63 M11 MD3N Output MIPI Data 3 Negative

64 M12 DOGND GND Analog/Digital GND

65 M13 NC - NC

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3.3.3 Fan-Out Package Pin Diagram

The following Figure 10 shows the pin assignment of Mira130. Figure 10: Fan-Out Pin Assignment E12 D12 A12 L12 K12 J12 H12 G12 E13 D13 C13 B13 A13 AVDD VREFH NC NC DOGND GPIO VREFN AVDD DOVDD DVDD DOVDD EXTCLK DVDD DOVDD DOGND DVDD DOGND GS_VREF AVDD MD2P MD2N DOVDD SDA NC VREFN1 DOGND F1 F2 F12 TRIGS AVDD DOGND C12 DOGND B12 SCL L13 K13 J13 H13 G13 DVDD MD1P MD1N MCP MCN MD0P F13 MD0N NC XSHUTDOWN TRIGL/ FSYNC DOGND NC DOGND LEDSTROBE DOGND DVDD DVDD TM M8 M9 DOGND DVDD DOGND M10 MD3P M11 M12 MD3N DOGND M13 NC A4 A5 DOGND AVDD ATM AVDD A8 A9 DOGND DVDD DOGND A10 SID1 A11 SID0

Typical Application Circuit Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 16

4 Typical Application Circuit

The typical application circuit of Mira130 using the MIPI interface is shown below. (1) The chip requires 3 power supplies: The AVDD pin shall be externally connected to a 2.5 V power supply, the DOVDD pin shall be externally connected to a 1.8 V power supply, and the DVDD pin shall be externally connected to a 1.2 V power supply. Filter capacitors shall be placed close to the corresponding pins. The capacitor values can be found in the figure above. (2) The GS_VREF, VREFN, VREFH pins shall be externally connected to ground through a 2.2 μF capacitor which is close to the corresponding pin but kept as far as possible from the I/O signals such as EXTCLK, TRIG, MIPI differential pairs. (3) The active low XSHUTDN pin is controlled by an external main control chip. It shall be connected to the DOVDD pin through a 10 kΩ pull-up resistor. (4) The external clock signal can be generated by a crystal connecting to the EXTCLK pin, or provided by an external ISP/MCU, applying directly to the EXTCLK pin. (5) The analog ground and the digital ground are recommended to be connected directly. (6) The SID0 and SID1 pins shall be either pulled up to the DOVDD pin or pulled down to the AGND pin, but shall never be floating. (7) The requirements of routing MIPI differential pairs areas follows: a) The control standard of the impedance of MIPI differential pairs is 100 Ω, and the tolerance is limited to ±10%. b) The differential pairs should not be right-angled in order to avoid reflections, and as a result affect high-speed transmission performance. c) Reference layer: There must be a reference layer below the MIPI differential pairs (a ground plane is recommended). The continuity of the layer must be guaranteed, that is the layer below the MIPI differential pairs cannot be fragmented, cannot consist of gaps, and cannot be cut by other lines. A whole layer of ground is preferred. If not possible, the minimum requirement is to ensure that the reference layer below the MIPI differential pairs is 4 W wider than each side of the MIPI signal wire, where W is the width of MIPI differential pairs. Mira130

Typical Application Circuit Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 17 d) Equal length: The difference in length between the two wires of a MIPI differential pair should be limited to 10 mils, and the difference in length among MIPI differential pairs should be controlled within 100 mils. These requirements ensure that the differential signals can reach the receiving end at the same time. When implementing the requirement of equal length, the symmetry should be considered. The distance between meander wires should be 4 times the trace width to avoid being too dense. The wires should be wound near the bonding pad as much as possible to keep equal length, and the wire width and distance cannot be changed arbitrarily. e) Symmetry: MIPI differential pairs should be kept equal length and distance. The purpose of symmetry is to ensure the consistency of trace impedance in order to reduce reflection. Poor symmetry may result in signal distortion, instability or no image. f) Keep clear of interference: The clearance between MIPI differential pairs should be larger than 2 W. The clearance between MIPI differential pairs and other high-speed signals (parallel data lines, clock lines, etc.) should be larger than 3 W, and they should not be routed in parallel. A larger clearance should be considered to avoid interference generated from circuits such as switching power supplies. g) Through holes: Through holes should be avoided for MIPI differential pairs. If unavoidable, through holes should be on both wires of the differential pair in order to maintain symmetry. If a differential pair is routed to another layer by means of through holes, the reference layer should also follow by means of through holes near the through holes of the differential pair.

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5 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 11: Absolute Maximum Ratings of Mira130 Symbol Parameter Min Max Unit Comments Electrical Parameters VAVDD Analog Supply Voltage -0.3 3.0 V VDOVDD I/O Supply Voltage -0.3 2.2 V VDVDD Digital Supply Voltage -0.3 1.4 V I/O Input Voltage -0.3 VDOVDD + 0.3 V I/O Output Voltage -0.3 VDOVDD + 0.3 V ISCR Input Current (latch-up immunity) ± 200 mA JEDEC JESD78E Nov 2016 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ± 3.5 kV MIL-STD-883J Method 3015.9 ESDCDM Electrostatic Discharge CDM ± 250 V C1=200pF ANSI/ESDA/JEDEC JS- 002-2014 Temperature Ranges and Storage Conditions TA Operating Ambient Temperature -30 80 °C TSPEC Operating Temperature Spec -20 60 °C Best performance (1) TJ Operating Junction Temperature -25 85 °C TSTRG_WAF Storage Temperature Range Wafer 20 30 °C tSTRG_WAF Storage Time Wafer 6 months RHNC_WAF Relative Humidity (non- condensing) Wafer 30 % N2 Wafer Stocker condition (2) MSLDIE Moisture Sensitivity Level bare die N/A (1) Ideal temperature range for best performance (2) Die and wafers, when in storage, should be stored at temperature between 20°C and 30°C, relative humidity of less than 30%, and in clean, dry, inert atmosphere (e.g. Nitrogen) or in a vacuum sealed bag.

Electrical Characteristics

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6 Electrical Characteristics

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 12: Symbol Parameter Conditions Min Typ Max Unit Power Supplies VAVDD Analog supply voltage 2.4 2.5 2.6 V VDOVDD I/O supply voltage 1.7 1.8 1.9 V VDVDD Digital supply voltage 1.14 1.2 1.26 V IAVDD Analog supply current @120 fps - 23(1) mA IDOVDD I/O supply current @120 fps - 0.5(1) mA IDVDD Digital supply current @120 fps - 49(1) mA Ptot Total power consumption @120 fps - 117(1) mW IAVDD Analog supply current @60 fps - 23(1) mA IDOVDD I/O supply current @60 fps - 0.5(1) mA IDVDD Digital supply current @60 fps - 33(1) mA Ptot Total power consumption @60 fps - 97.14(1) mW Digital Input (Reference: AVDD = 2.5 V, DOVDD = 1.8 V) VIL Input low level - - 0.3 x VDOVDD V VIH Input high level 0.7 x VDOVDD - - V CIN Input capacitor - - 10 pF Digital Output (25 pF standard load) VOH Output high level 0.9 x VDOVDD - - V VOL Output low level - - 0.1 x VDOVDD V Serial Interface Input (SCL and SDA) VIL Input low level -0.5 0 0.3 x VDOVDD V VIH Input high level 0.7 x VDOVDD VDOVDD VDOVDD + 0.5 V (1) Condition：MIPI:4lane_607.5 Mbit/s, Bitwidth:10-bit, Resolution:1080x1280

Electro-Optical Characteristics Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 21

7 Electro-Optical Characteristics

This section shows the typical electro-optical characteristics of Mira130, measured in typical conditions. Figure 15: Electro-Optical Characteristics of Mira130 Parameter Value Remark Active pixels 1080 (H) x 1280 (V) Pixel size 2.7 x 2.7 µm2 BSI Pixel type Voltage Domain Global Shutter Optical format 1/4" Full well charge 9 ke- Linear full well Temporal noise < 8 e- Dynamic range 57 dB in normal mode 100 dB in HDR mode In-pixel HDR allows exceptional performance SNR 40 dB PLS 1/7500 Responsivity 7000 mV/lux*s Quantum efficiency in NIR 58% at 850 nm 36% at 940 nm See QE measurement curve: Figure 16 Maximum frame rate Non-HDR:1080 H x 1280 V @10-bit 120 fps HDR (HDRC on): 1080 H x 1280 V @10-bit <60 fps HDR (HDRC off): 1080 H x 1280 V @10-bit 120 fps Output interface 10/8-bit 4lane MIPI 10/8-bit 4lane LVDS Output format RAW / MONO CRA 25 degree See Figure 17

Electro-Optical Characteristics Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 22 Figure 16: QE Measurement Curve

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8 Functional Description

8.1 Chip Description

8.1.1 Power-On Sequence

With an external supply of 1.2 V to DVDD, the following power-on sequence is required: Figure 18: Power-Up Sequence (1) T1 > 0 ms, T2 > 1 ms, T3 > 2 ms, T4 > 2 ms

8.1.2 I/O Pins Power-On Status

Figure 19: Pins Power-On Status Pin Name Built-In Pull-Up/Pull-Down Power Stable and XSHUTDOWN Low XSHUTDOWN High TRIGS No High-Z Low FSYNC No High-Z Low LED STROBE No High-Z Low GPIO No High-Z Low DOVDD DVDD XSHUTDN I2C I2C activity is ready AVDD cut off power

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8.1.3 Sleep Mode

Under sleep mode, this chip stops output data, works in a low power status, and keeps registers unchanged. This chip enters sleep mode by writing 0 to register 16'h0100[0]. I2C access remains active: Figure 20: Sleep Mode Control Register Function Address Default Value Description Sleep mode 16’h0100 1’b1 Bit[0]: Manual sleep mode control 0: Sleep mode enable 1: Sleep mode disable

8.1.4 Reset Mode

During reset, this chip stops outputting data, stays in sleep mode by the software approach, and resets its registers to their default values. This chip offers two approaches to reset: 1. Hard reset: Pull the XSHUTDN pin low, I2C read and write are not supported. 2. Soft reset: Write 1 to register 16'h0103[0], reset mode lasts for 150 ns Figure 21: Soft Reset Control Register Function Address Default Value Description Soft reset 16’h0103 1’b0 Bit[0]: Soft reset

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8.2 Configuration Interface

The on-chip registers can be read and written through the standard I2C interface. The device address of the I2C interface is determined by the SID0 and SID1 pins as shown in Figure 22. Figure 22: I2C Bus Device Address Control 7-bit I2C Bus Device Address SID0 SID1 7’h30 Low Low 7’h31 High Low 7’h32 Low High 7’h33 High High In the example below, the first line below shows a standard I2C communication protocol for 7-bit slave address, 16-bit sub address and 8-bit data. The slave address is the I2C bus device address, which is 7-bit. The R/W bit is either 1 for read or 0 for write. The 2 sub address bytes are the high byte and low byte of the 16-bit address of the register to be accessed. The second line in the example shows a write operation. The third line shows a read operation. A dummy write operation is required to set the sub address (i.e. register address) before the read operation. Information 16-bit register address, 8-bit data, 7-bit device address

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8.3 Sensor ID

Figure 26: Sensor ID Registers Function Address Default Value Sensor ID high byte 16’h3107 8’h01 Sensor ID low byte 16’h3108 8’h32

8.4 Data Interface

There are 2 types of data interfaces in this chip: the Mobile Industry Processor Interface (MIPI), and the Low Voltage Differential Signaling (LVDS). Only MIPI interface documentation is provided hereunder. For information on LVDS, please request this to your ams OSRAM contact.

8.4.1 Mobile Industry Processor Interface (MIPI)

This chip provides a Mobile Industry Processor Interface (MIPI), which supports 8/10/12-bit, 1/2/4-lane data serial output with a speed of lower than 1.25 Gbit/s per lane. Figure 27 shows the MIPI interface. Figure 27: MIPI Interface MIPI TX MIPI RX （-）MD3N （+）MD3P （-）MD3N （+）MD3P （-）MD0N （+）MD0P （-）MD0N （+）MD0P （-）MD2N （+）MD2P （-）MD2N （+）MD2P （-）MD1N （+）MD1P （-）MD1N （+）MD1P （Clock-）MCN （Clock+）MCP （Clock-）MCN （Clock+）MCP

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8.5 On-Chip PLL

The input clock frequency (FEXTCLK) of the phase locked loop (PLL) module ranges from 6 MHz to 27 MHz, while the VCO output frequency (FVCO) ranges from 400 MHz to 1200 MHz. The system clock frequency FSYSCLK is obtained by dividing FVCO. Figure 34 shows the PLL block diagram implemented on Mira130. Figure 34: PLL Block Diagram

8.5.1 Default Configurations and Clock Speeds

By default we provide some configuration files with predefined resolutions, framerates mipi lanes and clock speeds. Contact your ams OSRAM application engineer for more information. A typical configuration file is named according to the following example:

• AMS_Trig_Mira130_4lane_800Mbps_24Minput_120fps_1080x1280.ini From the filename, one can deviate the mipi clock speed (800Mbps x 4 lanes) with 24M main clock. Generally, 24M MCLK corresponds to a Systemclk of 108M, 27M MCLK corresponds to a Systemclk of 121.5M. To calculate the internal pixel clock (TPCLK), the formula below applies: pixel clock [MHz]=mipiclk [Mbps] / bit width * lane num Pre_Divider Divider PFD LPF VCO FEXTCLK FREFCLK Divider FVCO FSYSCLK

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9 Sensor Operation

9.1 Illumination Trigger

Mira130 supports an illumination strobe feature and can be used to control a light source (LED or VCSEL). During exposure, the LEDSTROBE pin outputs a logic level ‘high’ to enable an external illumination. Figure 35: Illumination Strobe Control Register Function Address Default Value Description Illumination strobe enable 16’h3361 8’h00 Bit[7:6]: LED strobe enable 2’b11: LED strobe disable 2’b00: LED strobe enable

9.2 External Triggering Mode

In external triggering mode, the exposure and data output of multiple sensors are synchronized by an external triggering signal applied on the TRIGL pin. When the rising edge of the signal is detected, the chip starts exposure after a short delay, and outputs data after completing exposure. The short delay is determined by register 16’h3226, and the exposure time is determined by registers {16’h3e00[3:0], 16’h3e01,16’h3e02}. The frame rate is determined by the signal. Figure 36 shows the timing diagram of external triggering mode which consists of the following time intervals: EXP Rows, Active Rows, and Blank Rows. Figure 36: External Triggering Global Shutter Mode Timing Diagram (1) EXP Rows = {16’h3e00[3:0], 16’h3e01, 16’h3e02[7:4]} + 16’h3226, in the unit of line. time frame valid TRIG EXP Rows Active Rows Blank Rows start exposure end of frame N start exposure start of frame N start of frame N+1

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 36 Figure 39: External Trigger Timing

9.3 High Dynamic Range (HDR)

Mira130 provides two exposure modes: Normal mode and High Dynamic Range (HDR) mode.

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 38 Figure 42: HDR Mode Control Registers Function Address Default Value Description HDR mode enable 16’h3220 8’h83 Bit[6]: HDR mode 1: Enable 0: Disable Total exposure time {16’h3e00[3:0], 16’h3e01, 16’h3e02} 20’h00200 In the unit of 1/16 line HDR exposure time {16’h3e31, 16’h3e32} 16’h0020 In the unit of 1/16 line HDRC exposure ratio setting 16’h5400 8’h00 Total exposure time -{16'h3e01, 16'h3e02}; the value of second exposure time {16'h3e31,16'h3e32}, value of 16'h5400=255*（1 – second exposure time/total exposure time）

9.4 AEC & AGC

The AEC/AGC adjustment is based on the image ’s brightness. AEC adjusts the exposure time while AGC adjusts the gain value so that the image’s brightness can fall within a range bounded by pre-set brightness thresholds.

9.4.1 AEC & AGC Control Strategy

This chip does not have the AEC function, so a back-end platform is needed in order to achieve AEC/AGC. During the AEC/AGC adjustment process, the exposure time and gain are interrelated and should be considered as a whole. A recommended adjustment strategy is as follows: maximize the exposure time first, and then apply gain if the exposure time has reached its maximum. Consider a dark scene, the sequence of adjustment is: 1) increase the exposure time with no gain until the exposure time reaches its maximum; 2) when the exposure time reaches its maximum but the image is still too dark, adjust the gain. It should be noted that when the gain is increased, the average image noise also increases. However, when the exposure time increases, the signal-to-noise ratio will improve. On the other hand, when the image is too bright, the gain should be reduced first. If all gains are reduced to their minimum but the image is still too bright, then the exposure time should be reduced.

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9.4.2 AEC Control Registers

Figure 43: Exposure (manual) Control Registers Function Address Description Exposure time {16’h3e00[3:0], 16’h3e01, 16’h3e02} Exposure time under normal mode/ total exposure time under HDR mode, in the unit of 1/16 line Exposure time under HDR mode {16’h3e31, 16’h3e32} In the unit of 1/16 line For AEC control, please refer to the following instructions: 1. The AEC adjustment step is 1/16 line of exposure time. One line of exposure time equals to line length × T_SystemClk, where T_SystemClk is the period of the system clock, and line length equals to the value of registers {16’h320c, 16’h320d}. 2. If the exposure time and gain are written to registers in the Nth frame, they are effective on the (N+2)th frame. 3. The upper limit of the exposure time is 0, and the upper limit is frame length - 8 lines, where frame length equals to the value of registers {16'h320e, 16'h320f}. Hence, the minimum value written to registers {16'h3e00[3:0], 16'h3e01, 16'h3e02} is 0, and the maximum value is (the value of registers {16'h320e, 16'h320f} - 8) x 16.

9.4.3 AGC Control Registers

Figure 44: Exposure (manual) Control Registers Mode ANA GAIN Register ANA FINE GAIN Register DIG GAIN Register DIG FINE GAIN Register Long exposure time under normal mode/HDR mode 16’h3e08 16’h3e09 16’h3e06 16’h3e07 Short exposure time under HDR mode 16’h3e12 16’h3e13 16’h3e10 16’h3e11

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 40 For AGC control, please refer to the following two methods: 1. When register 16'h3e03[3:0] is set to 4'h3, gain equals to the value of {ANA GAIN register, ANA FINE GAIN register } ÷ 8'h20. 2. When register 16'h3e03[3:0] is set to 4'hb, the analog gain and digital can be tuned. In general, the analog gain should be increased first. If the brightness is required to be further increased when the analog gain is increased to the maximum, the digital gain can be increased. The accuracy of the DIG FINE gain of this chip is 1/128. Figure 45: Analog Gain Settings ANA GAIN ANA FINE GAIN GAIN Value dB Value ANA GAIN ANA FINE GAIN GAIN Value dB Value ANA GAIN ANA FINE GAIN GAIN Value dB Value

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 41 ANA GAIN ANA FINE GAIN GAIN Value dB Value ANA GAIN ANA FINE GAIN GAIN Value dB Value ANA GAIN ANA FINE GAIN GAIN Value dB Value 8'h3F 8'h27 17.672 24.95 8'h3F 8'h37 24.922 27.93 8'h3F 8'h28 18.125 25.17 8'h3F 8'h38 25.375 28.09 8'h3F 8'h29 18.578 25.38 8'h3F 8'h39 25.828 28.24 8'h3F 8'h2A 19.031 25.59 8'h3F 8'h3A 26.281 28.39 8'h3F 8'h2B 19.484 25.79 8'h3F 8'h3B 26.734 28.54 8'h3F 8'h2C 19.938 25.99 8'h3F 8'h3C 27.188 28.69 8'h3F 8'h2D 20.391 26.19 8'h3F 8'h3D 27.641 28.83 8'h3F 8'h2E 20.844 26.38 8'h3F 8'h3E 28.094 28.97 8'h3F 8'h2F 21.297 26.57 8'h3F 8'h3F 28.547 29.11 8'h3F 8'h30 21.750 26.75 8'h3F 8'h31 22.203 26.93 8'h3F 8'h32 22.656 27.10 8'h3F 8'h33 23.109 27.28 8'h3F 8'h34 23.563 27.44 8'h3F 8'h35 24.016 27.61 8'h3F 8'h36 24.469 27.77 Figure 46: Digital Gain Settings DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 42 DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 43 DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value DIG GAIN DIG FINE GAIN Gain Value dB Value 8'h07 8'hEC 14.750 23.38 8'h0F 8'hC4 24.500 27.78 8'h07 8'hF0 15.000 23.52 8'h0F 8'hC8 25.000 27.96 8'h07 8'hF4 15.250 23.67 8'h0F 8'hCC 25.500 28.13 8'h07 8'hF8 15.500 23.81 8'h0F 8'hD0 26.000 28.30 8'h07 8'hFC 15.750 23.95 8'h0F 8'hD4 26.500 28.46 8'h0F 8'h80 16.000 24.08 8'h0F 8'hD8 27.000 28.63 8'h0F 8'h84 16.500 24.35 8'h0F 8'hDC 27.500 28.79 8'h0F 8'h88 17.000 24.61 8'h0F 8'hE0 28.000 28.94 8'h0F 8'h8C 17.500 24.86 8'h0F 8'hE4 28.500 29.10 8'h0F 8'h90 18.000 25.11 8'h0F 8'hE8 29.000 29.25 8'h0F 8'h94 18.500 25.34 8'h0F 8'hEC 29.500 29.40 8'h0F 8'h98 19.000 25.58 8'h0F 8'hF0 30.000 29.54 8'h0F 8'h9C 19.500 25.80 8'h0F 8'hF4 30.500 29.69 8'h0F 8'hA0 20.000 26.02 8'h0F 8'hF8 31.000 29.83 8'h0F 8'hA4 20.500 26.24 8'h0F 8'hFC 31.500 29.97 8'h0F 8'hA8 21.000 26.44 8'h0F 8'hAC 21.500 26.65 8'h0F 8'hB0 22.000 26.85 8'h0F 8'hB4 22.500 27.04 8'h0F 8'hB8 23.000 27.23 8'h0F 8'hBC 23.500 27.42 8'h0F 8'hC0 24.000 27.60

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 44

9.5 Group Hold

Group hold refers to the packing of a group of registers to be effective at a specific time within a frame. This chip supports a maximum of 4 groups with a total of 320 registers. Each group can be individually controlled (registers packaging, register values writing, and delay setting).The detail of controlling is as follows. 1. Set register 16'h3800 to 8'h0X (X= 0, 1, 2, 3) to start packing group X. 2. Set register 16'h3800 to 8'h1X to end packing group. 3. Set register 16'h3800 to 8'h6X, registers packed in group X are effective immediately. 4. Set register 16'h3800 to 8'h4X, registers packed in group X are effective after N frames, where N is set by a register. Information

• The maximum number of registers within a group is 16 by default.
• Registers in group X are effective in the (N + 1)th frame when setting register 16'h3800 to 8'h4X. Figure 47: Group Hold Control Registers Function Address Default Value Description Frame delay control 16’h3817 8’h20 Bit [3:0]: Determine the number of frames to be delayed before the group of registers is effective. Setting to N implies a delay of N frames, and the group of registers is effective in the (N + 1)th frame. Setting to 0 implies no delay and the group of registers is effective in the next frame. Status control 16’h3800 Write only Bit[7:0]: Status of group X (X=0,1,2,3) 8’h0X: Start packing group X 8’h1X: End packing group X 8’h6X: Registers in group X are effective immediately 8’h4X: Registers in group X are effective in the (N + 1)th frame, where N is the value of register 16’h3817[3:0]

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 45

9.6 HDR Calibration

In order to enhance image quality, this chip supports a HDR calibration (HDRC) feature which can eliminate image noise as a result of using HDR mode. When HDRC is enabled, one more frame named HDR point is read, so the readout time is doubled . Also, there is no exposure during reading when HDRC is enabled. The frame rate is determined by both the exposure time (texp) and image reading time (tread). For example, if the frame rate is 30 fps under HDR mode (i.e. one frame lasts for 33.33 ms), and tread is 11.11 ms (according to 90 fps), the maximum exposure time is 33.33 ms – 2*tread -11.11 ms. Figure 48: HDRC Control Registers Function Register Default Value Description HDR point read enable 16’h3222 8’h00 Bit[5:4]: HDR point 2’b00: HDR point not read 2’b11: HDR point read HDRC enable 16’h5001 8’h00 Bit[3]: HDRC feature 1’b0: Enable 1’b1: Disable

9.7 Temperature Sensor

The instantaneous temperature of this chip can be measured by an integrated temperature sensor and is stored in a register for reading. The unit is Kelvin, and the accuracy is 0.25 K. Figure 49: Temperature Sensor Control Register Function Register Default Value Description Chip temperature {16’h4c10, 16’h4c11[2:0]} Read only Temp [10:0]

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 46

9.8 Video Output Mode

9.8.1 Read Order

Figure 50 provides the first read pixel location as well as the entire array structure diagram. Figure 50: Mira130 Pixel Array Mira130 supports mirror mode and flip mode. Mirror mode reverses the sensor data readout order, and flip mode vertically reverses the sensor readout order (as shown in Figure 51 ). The registers that control these operations are shown in Figure 52. Figure 51: Mirror & Flip Examples Active Border (4 rows) Active Border (4 rows) Active Border (4 cols) Active Border (4 cols) Pixel Size: 2.7 μm x 2.7 μm Active Array 1080H x 1280V First Pixel (0, 0) Original Picture Mirror Flip Mirror and Flip

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 47 Figure 52: Mirror & Flip Control Registers Function Address Default Value Description Mirror 16’h3221 8’h00 Bit[2:1]: Mirror control 2’b00: Mirror off 2’b11: Mirror on Flip 16’h3221 8’h00 Bit[6:5]: Flip control 2’b00: Flip off 2’b11: Flip on

9.8.2 Output Window

The table below displays the control registers that define the image window to be read-out. Figure 53: Output Window Registers Function Address Default Value Description Window width {16’h3208, 16’h3209} 16’h0438 Output window width Window height {16’h320a, 16’h320b} 16’h0500 Output window height Column start {16’h3210, 16’h3211} 16’h0010 Output window column start Row start {16’h3212, 16’h3213} 16’h0010 Output window row start

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 48 Figure 54: Windowing Calculation example for outputting 100 lines: If you want to output 100 lines, you can modify the register as follows 1. Set the window height to 100,{0x320a,0x320b}=0x64; 2. Set Active Rows to image height + 8. Active Rows = Active Rows End - Active Rows Start +1 = {0x3206,0x3207}- {0x3202,0x3203}+1. eg.{0x3202,0x3203}=0x00, {0x3206,0x3207}=0x6b; 3. Set the Start Row to 4(default=0x10,min=0x04), {0x3212,0x3213}=0x04; 4. Set the VTS=window height+24, {0x320e,0x320f}=0x7c. This setting is the highest frame rate. If you need to adjust the window position, you need to adjust the Active Rows Start and Active Rows Start End.

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 49

9.9 Binning Mode

The sensor provides a binning mode to combine pixels 2x2. This will reduce the resolution, but increases the full well charge and SNR. Ask your application engineer for a binning configuration. Figure 55: Binning Mode Starting from an existing configuration, the following registers need to be modified to enable binning. Figure 56: Vbin Mode : (P11+P21)/2 Address Bit Value Default 0x3220[2] 1’b1 0x87 0x83 0x3215 8’h22 0x22 0x11 0x3213 8’h08 0x08 0x10 0x334f[5] 1’b1 0xbe 0x9e 0x3231[1] 1’b1 0x0a 0x08 0x3230[3:2] 2’b01 0x04 0x00

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 50 Figure 57: Hsum Mode : (P11+P12) Address Bit Value Default 0x5000[6] 1’b1 0x4e 0x0e 0x5901 8’h14 0x14 0x00 0x5900 8’hf6 0xf6 0x01 Figure 58: Window Address Value Description {0x3208，0x3209} 0x220 Image Width {0x320a，0x320b} 0x280 Image Height

9.10 Frame Rate Calculator

The special frame rate of this chip is provided by FAEs. For simplicity, the duration of one line can be calculated as 1/(frame rate * frame length) in seconds. The frame rate is the number provided in the configuration file. Figure 59: Frame Rate Related Registers Function Address Default Value Description Frame Length {16’h320e, 16’h320f} 16’h061a Frame Length or VTS Line Length {0x320c, 0x320d} 16’h0x0370 Line Length or HTS. HTS=0x2EE minimum

9.10.1 Adjusting Framerate

The following formula can be used to alter the default framerate. FPS = SystemClk/HTS/VTS, Trow=HTS./SystemClk

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 51

9.11 Test Mode

For the ease of testing, Mira130 provides a grey ramp test mode as shown below. Figure 60: Test Mode Image Figure 61: Test Mode Control Registers Function Address Register Value Description Grey Ramp Mode 16’h4501[3] 1’b1 Bit[3]: Incremental pattern enable 0~Normal image 1~Incremental pattern 16’h3902[6] 1’b0 Bit[6]: blc auto enable 0~Manual BLC 1~Auto BLC 16’h391d[2:0] 3’h0 Bit[2:0] : Only open in blc auto mode 16’h3e06[3:0] 4’hf Bit[3:0]: Digital gain 4’h0~ 1x 4’h1~ 2x 4’h3~ 4x 4’h7~ 8x 4’hf~ 16x

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 52 Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Changes from previous version to current revision v5-00 Page Added information about CRA 23

• Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
• Correction of typographical errors is not explicitly mentioned.

Datasheet • PUBLIC DS000715 • v5-00 • 2022-Apr-05 53 │ 53

11 Legal Information

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