MIN1072M POWERINT | Alldatasheet
Document overview
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Technical content
www.power.com May 2022 Bulk Capacitor Miniaturization and Inrush Management IC With
750 V PowiGaN for Very High Power Density AC/DC Converters
This Product is Covered by Patents and/or Pending Patent Applications. Product Highlights
- Up to 50% volume reduction of input bulk capacitors (E-CAPs)
- Eliminates inrush NTC
- Significantly reduces i2t stress on the input bridge rectifier and fuse
- Partners with the InnoSwitch™ IC family for lowest component count ultra-compact AC/DC converters
- Robust 750 V PowiGaN switch Advanced Protection / Safety Features
- Integrated temperature sensing and hysteretic thermal shutdown
- Input surge protection
- Pin open/short-circuit and E-CAP UV/OV fault reporting
Applications
- High power density universal input AC-DC converters
- Applications with very wide input range (90 – 350+ VAC)
Description
The MinE-CAP™ IC dramatically shrinks the size of input bulk capacitors without compromising output ripple, operating efficiency or requiring redesign of the transformer. When compared to traditional techniques such as very high switching frequency operation, MinE-CAP achieves the same or greater overall power supply size reduction whilst avoiding the challenges of complex EMI filtering and the increased transformer/ clamp dissipation associated with very high frequency designs. MinE-CAP also precisely manages inrush current at AC turn-on, eliminating the need for dissipative NTCs or large slow-blow fuses. Figure 1 illustrates, the circuit configuration when using MinE-CAP. The input E-CAPs are arranged with a small high-voltage capacitor (C HV typically 400 V) in parallel with a low-voltage capacitor (C LV typically 160 V) connected in series with the MinE-CAP IC. The physical size of the input capacitors is minimized because a high percentage of the input capacitance is 160 V rated rather than 400 V as would normally be used in conventional universal input converters. MinE-CAP can also be used in applications requiring extended wide-range input (90 VAC to 350+VAC), again with a high percentage of the input capacitance 160 V rated along with either stacked 400 V or 500-600 V rated capacitors of much smaller value than would normally be required. During steady state-operation MinE-CAP introduces C LV into the circuit at low AC line voltage when maximum input capacitance is required. To achieve this, MinE-CAP monitors the input rail and voltage across C LV to dynamically engage and disengage this capacitor during every AC line cycle as required to ensure that the power supply operates smoothly across the entire specified input voltage range. The selection chart of Figure 2 illustrates the recommended range of CHV and CLV values to achieve the required total input capacitance for a given output power. The capacitance split between C HV and CLV can differ from the proposed values in Figure 2 based on application requirements but it is recommended that the total capacitance is within the suggested range. CLV is an electrolytic capacitor while C HV can be selected as an electrolytic or ceramic. Ceramic capacitors in the range of 1 to 5 mF
400 V (depending on power level) have very low esr and typically offer
the most space saving when the power supply is designed to accommodate ceramic capacitor characteristics (see Applications Figure 1. InnoSwitch3-CP PI-9208-100720 CLV CHV MinE-CAP D D ISVL S VBOT FWD SR BPS GND VTOP BP S BPP VOUT Typical Application Schematic.
400 V CHV Range
Output Power (W) Capacitance (µF) 95908580757065605550454035302520 100 Total Bulk Capacitance Range
160 V C
Figure 2. Typical Component Value Ranges for Optimal Space Saving and Figure 3. MIN1072M MinSOP-16A Package. also derives its bias supply directly from the InnoSwitch BPP pin.
Figure 4. MinE-CAP IC Block Diagram.
negative end of the LV capacitor. Leave open. Should not be connected to any other pins or traces. Leave open. Should not be connected to any other pins or traces. These pins must be connected to the SOURCE pin. This pin is the power switch source connection. This pin is the power switch drain connection.
10 GND
9 GND
Figure 5. Pin Configuration.
line voltage conditions and disconnects it at high input line voltages. across CLV does not exceeded the rated voltage of the capacitor. thermal hotspot and increases conversion efficiency. charge up schemes to adopt as described below. deliver full power in less than 250 ms from initial AC line connection. Figure 6. Charging Algorithm used for Low-Line Start-Up. the bulk voltage remains below the user defined threshold (V COV+). contributing to output power delivery. control of the MinE-CAP power switch.
Figure 7. Steady-State MinE-CAP Power Switch Control. and undergoes a normal start-up sequence. The MinE-CAP IC has built-in the following fault detection capabilities. Fault communication to InnoSwitch is done via the LINE pin. is on and a surge event occurs, the power switch is disabled for 130 ms. reset and undergoes a normal start-up sequence. controller is reset and undergoes a normal start-up sequence.
Note: PD Controller Not Shown (Refer to DER-626 Report for Complete Schematic).
440 VAC
Figure 8. Schematic of DER-626, a 65 W USB PD 3.0 Adapter Design. differential mode noise filtering to minimize conducted EMI emissions. loss from two rectifiers is the same as that of a single device. limiting NTC thermistor is no longer necessary. MinE-CAP IC to sample the voltage at the negative terminal of C2. in the leakage inductance of the transformer.
Rev. H 05/22 MinE-CAP www.power.com Layout Considerations The following layout considerations are specifically for the MinE-CAP components. For placement and layout of InnoSwitch3-specific and power components, check the InnoSwitch3-Pro data sheet. 1. The MinE-CAP sense pins (VBOT and VTOP) and InnoSwitch3 IC’s V pin use current in the mA range to measure line and capacitor voltages. Avoid routing lines with high dV/dt or dI/dt signals near these pins. This rule must also be observed for the LINE pin. 2. Signal lines going to the pins stated above must also be routed away from high dV/dt or dI/dt nodes or tracks. 3. All resistors associated with the MinE-CAP IC, except for the bleed resistor in parallel with C LV must be placed near the MinE-CAP IC. 4. Place the MinE-CAP IC as close as possible to the InnoSwitch3-Pro IC to minimize the trace from the LINE pin to the V pin of the Innowitch IC. Placing the MinE-CAP IC next to the InnoSwitch3 IC also allows the use of a single bypass capacitor for both ICs. 5. Tie the GROUND pins to a copper plane for heat dissipation. If a large copper plane is not possible, thermal vias can also be used for boards with 2 or more copper layers. The MinE-CAP IC and InnoSwitch3-Pro IC can share the same GND plane. 6. Place both input bulk capacitors in such a way to minimize the primary switching loop. Prioritize placing the high-voltage capacitor closer to the transformer and InnoSwitch3-Pro IC since this capacitor is always part of the high-frequency switching loop. 7. Clean the board properly to prevent flux residues from interfering with the signals. Figure 9 shows the MinE-CAP layout used for the design in Figure 8 following the recommendation stated above. In this design, the layout did not permit the RTOP to be placed right next to the VTOP pin. However, the VTOP pin trace is shielded by a ground plane beside and beneath the trace. Additionally, there are no high di/dt or dv/dt signals near the track, pin or resistor.
Figure 9. Layout of the Design in Figure 8 Showing the Location of Major Components.
Rev. H 05/22 MinE-CAP www.power.com Absolute Maximum Ratings (1,2) Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Higher peak Drain current is allowed while the Drian voltage is simultaneously less than 400 V. 4. Normally limited by internal circuitry. 5. 1/16” from case for 5 seconds. Thermal Resistance Thermal Resistance: Notes: 2. Solder to 1 sq. in (645 mm2), 2 oz. (610 g/m2) copper clad. 3. The case temperature is measured on the top of the package. Parameter Symbol Conditions TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Analog Parameters BYPASS Supply Current IS1 TJ = 25 °C 300 430 475 mA BYPASS Pin Voltage VBPP 4.45 V BYPASS Pin Voltage Hysteresis VBPP(H) 0.6 V Bypass Power-Up Reset Threshold Voltage VBPP(RESET) TJ = 25 °C 3.45 3.75 3.90 V Brown-In IUV+ TJ = 25 °C 17 18 19 mA Brown-Out IUV- TJ = 25 °C 11 12 13 mA LV Capacitor OV Threshold ICOV+ TJ = -40 °C to 100 °C 33.8 37.0 38.25 mA ICOV(H) TJ = 25 °C 2.5 Trickle Charge Regulation Voltage VTRKLCHRG TJ = 25 °C Using 4M RTOP and 1M RBOT Resistors 145 V LINE Pin Brown-Out Injection Current IINJECT(UV) TJ = 25 °C 4 5 6 mA LINE Pin OV Injection Current IINJECT(OV) TJ = 25 °C 118 128 mA Off-State Drain Leakage Current IDSS1 VBPP = VBPP + 0.1 V VDS = 150 V TJ = 25 °C 4.5 10 mA IDSS2 VBPP = VBPP + 0.1 V VDS = 325 V TJ = 25 °C 5 10 mA On-State Resistance RDS(ON) TJ = 25 °C 0.35 0.44 W TJ = 100 °C 0.49 0.62 W Thermal Shutdown TSD See Note A 135 142 150 °C Thermal Shutdown Hysteresis TSD(H) See Note A 70 °C NOTES: A. This parameter is derived from characterization.
Rev. H 05/22 MinE-CAP www.power.com C POD_MinSOP-16A_E_042922 PI-8833-051622 MinSOP-16A (M Package) 12 Leads0.29 0.17 1.16 Ref. Detail A END VIEW 1.35 1.23 5.67 BOTTOM VIEW A
0.10 C A
4 Lead Tips
0.30 0.20 0.42 Ref. Pin #1 I.D. 2.03 Ref. 9.00 0.665 11.32
0.25 M C A B
B 0.15 C
8 Lead Tips
0.15
0.10 C B
0.85 0.55 0.22 0.07 Standoff 0.19 Gauge Plane Seating Plane 0.46 Ref. DETAIL A H 0° – 8° 2.16 Max. Total Mounting Height Seating Plane Coplanarity: 12 Leads 1.94
1.74 Body Thickness
C 0.10 C Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and inter-lead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include inter-lead flash or protrusions. 5. Controlling dimensions in millimeters. 6. Datums A and B to be determined at Datum H. 7. This dimension is the nominal dimension between leadtips, not including plating, and not including metal protrusions. Metal-to-metal distance (Creepage) is 1.85 mm minimum.
Rev. H 05/22 MinE-CAP www.power.com PI-9220-082120 MinSOP-16A A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year followed by 2-digit work week) C. Product Identification (Part #/Package Type) D. Lot Identification Code PACKAGE MARKING A D C BMIN1072M YYWW %%7654321A Part Ordering Information
- MinE-CAP Product Family
- Series Number
- Package Identifier M MinSOP-16A
- Tape & Reel and Other Options TL Tape & Reel, 2 k pcs per reel. MIN 1072 M - TL
D Production release . 11/20 E Updated DRAIN Pin Voltage and added Note 6 in Absolute Maximum Ratings table on page 11. 12/20 F Clarified LV capacitor and HV capacitor values and discharge sequence on pages 1 and 10. 08/21 G PowiGaN Updates to Page 1 and DRAIN Pin Peak Current Updated to 30 A. 01/22 H Updated MinSOP-16A (M package) drawing. 05/22 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2022, Power Integrations, Inc. World Headquarters
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