MC74HC164 ARTSCHIP | Alldatasheet
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8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 1 z Wide Operating Voltage Range of 2 V to 6V z Outputs Can Drive Up To 10 LSTTL Loads z Low Power Consumption, 80-ȰA Max ICC z Typical t pd =20 ns z 4-mA Output Drive at 5V z Low Input Current of 1ȰA Max z AND-Gated (Enable/Disable) Serial Inputs z Fully Buffered Clock and Serial Inputs z Direct Clear Description/ordering information These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) input permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. MC54HC164…J OR W PACKAGE MC74HC164…AD,N,NS, OR PW PACKAGE (TOP VIEW) MC54HC164…FK PACKAGE (TOP VIEW) NC-No Internal connection
ORDERING INFORMATION
T A PACKAGE† ORDERABLE PARTNUMBER TOP-SIDE MARKING PDIP –AN Tube of 25 MC74HC164 AN MC74HC164 AN PDIP –N Tube of 25 MC74HC164N MC74HC164N Tube of 50 MC74HC164AD Reel of 2500 MC74HC164AD SOIC - D Reel of 250 MC74HC164DT HC164 SOP –NS Reel of 2000 MC74HC164NSR HC164 Tube of 90 MC74HC164PW Reel of 2000 MC74HC164PWR -40¥ to 85 ¥ TSSOP – PW Reel of 250 MC74HC164PWT HC164 CDIP – J Tube of 25 MC54HC164J MCJ54HC164J CFP – W Tube of 150 MC54HC164W MCJ54HC164W -55¥ to 125 ¥ LCCC - FK Tube of 55 MC54HC164FK MCJ54HC164FK
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 2 FUNCTION TABLE INPUTS OUTPUTS C L K A B Q A Q B … Q H L X X X H L X X H ↑ H H H ↑ L X H ↑ X L L L L QAO Q BO Q HO H Q An Q Gn L Q An Q Gn L Q An Q Gn QA0, QB0,QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = the level of QA or QG before the most recent ↑ transition of CLK: indicates a 1-bit shift logic diagram (positive logic) Pin numbers shown are for the AD,J,N,NS, PW, and W packages.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 3 Typical clear, shift, and clear sequence absolute maximum ratings over operating free-air temperature range (unless otherwise noted) † Package thermal impedance, †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 4 Recommended operating conditions (see Note 3) MC54HC164 MC74HC164 M I N N O M M A X M I N N O M M A X UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC=2V 1.5 1.5 VCC=4.5V 3.15 3.15 VIH High-level input voltage VCC=6V 4.2 4.2 V VCC= 2 V 0 . 5 0 . 5 VCC= 4 . 5 V 1 . 3 5 1 . 3 5VIL Low-level input voltage VCC= 6 V 1 . 8 1 . 8 V VI Input voltage 0 V CC 0 V CC V VO O u t p u t v o l t a g e 0 V CC 0 V CC V VCC=2V 1000 1000 VCC=4.5V 500 500 ¶U¶W† Input transition rise/fall time VCC=6V 400 400 ns T A Operating free-air temperature -55 125 -40 85 ¥ NOTE 3: All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report. Implications of Slow or Floating CMOS Inputs, literature number SCBAOO4. † If this device is used in the threshold region (from V IL max = 0.5V to VIH min =1.5V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at t t =1000ns and V CC = 2V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA =25¥ MC54HC164 MC74HC164PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2V 1.9 1.998 1.9 1.9 6V 5.9 5.999 5.9 5.9 VOH V I= VIH or VI L V 2V 0.002 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 VOL V I= VIH or VI L V II V I = VCC o r 0 6 V 0.1 1 0 0 1000 1000 nA ICC V I = VCC o r 0 , I O =0 6 V 8 1 6 0 8 0 ȰA C i 2 V t o 6 V 3 1 0 1 0 1 0 p F
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 5 Timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA =25¥ MC54HC164AN MC74HC164AN VCC M I N M A X M I N M A X M I N M A X UNIT 2 V 6 4 . 2 5 4 . 5 V 3 1 2 1 2 5f clock Clock frequency
6 V 3 6 2 5 2 8
4.5V 20 30 25 low 6V 17 25 21 2V 80 120 100 4.5V 16 24 20 t W Pulse duration CLK high or low 6V 14 20 18 ns 2V 100 150 125 4.5V 20 30 25 Data 6V 17 25 21 2V 100 150 125 4.5V 20 30 25 t su Setup time before CLK ↑ inactive 6V 17 25 21 ns 2V 5 5 5 4.5V 5 5 5 t h Hold time, data after CLK↑ 6V 5 5 5 ns Switching characteristics over recommended operating free-air temperature range, CL = 50pF (unless otherwise noted) (see Figure1) TA =25¥ MC54HC164AN MC74HC164AN PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2V 6 10 4.2 5 4.5V 31 54 21 25 f max 6V 36 62 25 28 MHz 2V 140 205 295 255 4 . 5 V 2 8 4 1 5 9 5 1t PHL Any Q
6 V 2 4 3 5 5 1 4 6
4 . 5 V 2 3 3 5 5 3 4 4t pd CLK Any Q
6 V 2 0 3 0 4 5 3 8
2 V 3 8 7 5 1 1 0 9 5
4 . 5 V 8 1 5 2 2 1 9t t
6 V 6 1 3 1 9 1 6
Operating characteristics, TA = 25¥ PARAMETER TESTCONDITIONS TYP UNIT C pd Power dissipation capacitance No load 135 pF
NOTES: A. CL includes probe and test-fixture capacitance. having the following characteristics: PRR1MHz, ZO =50Ȥ, tr = 6ns, tf =6ns. C. For clock inputs, f max is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. t PLH and t PHL are the same as t pd . Figure 1. Load Circuit and Voltage Waveforms
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 7 J (R –GDIP –T **) CERAMIC DUAL IN-LINE PACKAGE
14 LEADS SHOWN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C . T h i s p a c k a g e i s h e r m e t i c a l l y sealed with a ceramic lid using glass frit. D. Index point is provided on cop for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL STD 1835 GD IP1-T14, GDIP1-T16, GDIP1-T18 and GDIP1-T20.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 8 MECHANICAL DATA W ( R - G D F P - F 1 4 ) CERAMIC DUAL FLATPACK 4040180-2/D 07/03 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provid ed on cap for terminal identification only. E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 9 MECHANICAL DATA F K ( S - C Q C C - N * * ) L E A D L E SS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 10 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body length (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 11 MECHANICAL DATA D (R-PDSO-G14) PLASTIC SMALL-OUTLINE PACKAGE 4040047-3/F 07/2004 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mo ld flash or protrusion not to exceed 0.006 (0.15). D. Falls within JEDEC MS-012 variation AB.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 12 MECHANICAL DATA NS(R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14-PINS SHOWN 4040062/C 03/03 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.15.
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS www.artschip.com 13 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.15. D. Falls within JEDEC MO-153.