DS1307

DS1307 ARTSCHIP | Alldatasheet

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64 x 8, Serial, I2C Real-Time Clock www.artschip.com 1 GENERAL DESCRIPTION The DS1307 serial real-time clock (RTC) is a low-power, full bina ry-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I 2C *, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the battery supply.

FEATURES

z Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the week, and Year with Leap-Year Compensation Valid Up to 2100 z 56-Byte, Battery-Backed, Nonvolatile (NV) RAM for Data Storage z I2C Serial Interface z Programmable Square-Wave Output Signal z Automatic Power-Fail Detect and Switch Circuitry z Consumes Less than 500nA in Battery Backup Mode with Oscillator Running z Optional Industrial Temperature Range: -40¥ to +85 ¥ z Available in 8-Pin Plastic DIP or SO z Underwriters Laboratory (UL) Recognized Typical operating circuit and Pin Configurations appear at end of data sheet.

ORDERING INFORMATION

PART TEMP RANGE VOLTAGE(V) PIN-PACKAGE TOP MARK* DS1307 0¥ to +70 ¥ 5.0 8 PDIP (300 mils) DS1307 DS1307+ 0¥ to +70 ¥ 5.0 8 PDIP (300 mils) DS1307 DS1307N -40¥ to +85 ¥ 5.0 8 PDIP (300 mils) DS1307 DS1307Z 0¥ to +70 ¥ 5.0 8 SO (150 mils) DS1307 DS1307Z+ 0¥ to +70 ¥ 5.0 8 SO (150 mils) DS1307 DS1307ZN -40¥ to +85 ¥ 5.0 8 SO (150 mils) DS1307N DS1307ZN+ -40¥ to +85 ¥ 5.0 8 SO (150 mils) DS1307N DS1307Z/T&R 0¥ to +70 ¥ 5.0 8 SO (150 mils) Tape and Reel DS1307 DS1307Z+T&R 0¥ to +70 ¥ 5.0 8 SO (150 mils) Tape and Reel DS1307 DS1307ZN/T&R -40¥ to +85 ¥ 5.0 8 SO (150 mils) Tape and Reel DS1307N DS1307ZN+T&R -40¥ to +85 ¥ 5.0 8 SO (150 mils) Tape and Reel DS1307N +Denotes a lead-free/RoHS-compliant device. *A “+” anywhere on the top mark indicates a lead-free device. An “N” on the lower left corner of the top mark indicates an industrial temperature grade device. ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (Noncondensing ) Soldering Temperature (surface mount)…………………………………………See JPC/JEDEC Standard J-STD-020A

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of th e device at these or any ot her conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0¥ to +70 ¥, TA =-40¥ to +85 ¥.) (Notes 1,2) PARAMTER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Vcc 4.5 5.0 5.5 V Logic 1 Input V IH 2 . 2 V c c + 0 . 3 V Logic 0 Input V IL - 0 . 3 + 0 . 8 V VBAT Battery Voltage V BAT 2 . 0 3 3 . 5 V DC ELECTRICAL CHARACTERISTICS (Vcc = 4.5V to 5.5V; TA=0¥ to +70 ¥, TA =-40¥ to +85 ¥.) (Notes 1,2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage (SCL) ILI - 1 1 µ A I/O Leakage (SDA, SQW/OUT) ILO - 1 1 µ A Logic 0 Output (IOL =5mA) VOL 0 . 4 V Active Supply Current (fSCL=100kHz) ICCA 1 . 5 m A Standby Current ICCS (Note 3) 200 µA VBAT Leakage Current IBATLKG 5 5 0 n A Power-Fail Voltage (VBAT=3.0V) VPF 1.216x 1.25x 1.28x VBAT V BAT V BAT V DC ELECTRICAL CHARACTERISTICS (Vcc = 0V, VBAT =3.0V; TA=0¥ to +70 ¥, TA=-40¥ to +85 ¥. ) (Notes 1,2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT Current (OSC ON); SQW/OUT OFF IBAT1 3 0 0 5 0 0 n A VBAT Current (OSC ON); SQW/OUT ON(32kHz) IBAT2 4 8 0 8 0 0 n A VBAT Data-Retention Current (Oscillator Off) IBATDR 1 0 1 0 0 n A

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 3 AC ELECTRICAL CHARACTERISTICS (Vcc=4.5V to 5.5V; TA=0¥ to +70 ¥, TA=-40¥ to +85 ¥) (Notes 1,2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL 0 100 kHz Bus Free Time Between a STOP and START Condition tBUF 4.7 µs Hold Time (Repeated) START Condition t HD:STA (Note 4) 4.0 µs LOW Period of SCL Clock t LOW 4.7 µs HIGH Period of SCL Clock t HIGH 4.0 µs Setup Time for a Repeated START Condition tSU:STA 4.7 µs Data Hold Time t HD:DAT 0 µs Data Setup Time t SU:DAT (Notes 5, 6) 250 ns Rise Time of Both SDA and SCL Signals tR 1 0 0 0 n s Fall Time of Bath SDA and SCL Signals t F 300 ns Setup Time for STOP Condition t SU:STO 4.7 µs CAPACITANCE (TA=+25¥) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Pin Capacitance (SDA, SCL) CI/O 1 0 p F Capacitance Load for Each Bus Line CB (Note 7) 400 pF Note 1: All voltages are referenced to ground. Note 2: Limits at -40¥ are guaranteed by design and are not production tested. Note 3: ICCS specified with Vcc =5.0V and SDA, SCL=5.0V. Note 4: After this period, the first clock pulse is generated. Note 5:A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 6: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 7: CB-total capacitance of one bus line in pF.

Figure 1. Block Diagram

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 5 TYPICAL OPERATING CHARACTERISTICS (Vcc=5.0V, TA=+25¥, unless otherwise noted.)

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 6 PIN DESCRIPTION PIN NAME FUNCTION 1 X1 2 X2 Connections for standard 32.768 kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1. Note: For more information on crystal selection and crystal layout considerations, refer to Application Note58: Crystal Considerations with ARTSCHIP Real-Time Clocks.

3 V BAT

Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes in series between the battery and the V BAT pin may prevent proper operation. If a backup supply is not required, VBAT must be grounded. The nominal power-fail trip point (VPF) voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x V BAT nominal. A lithium battery with 48m Ahr or greater will back up the DS1307 for more than 10 years in the absence of power at +25¥. UL recognized to ensure against reverse charging current when used with a lithium battery.

4 GND Ground

5 SDA Serial Data Input/Output. SDA is the data input/Output for the I2C serial interface. The SDA pin is open drain and requires an external pullup resistor. 6 SCL Serial Clock Input. SCL is the clock input for the I 2C interface and is used to synchronize data movement on the serial interface.

7 SWQ/OUT

Square Wave/Output Driver. When enabled, the SQ WE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4k Hz, 8kHz, 32kHz). The SQW/OUT pin is open drain and requires an external pullup resist or. SQW/OUT operates with either Vcc or V BAT applied.

8 Vcc

Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and Vcc is below V TP, read and writes are inhibited. Ho wever, the timekeeping function continues unaffected by the lower input voltage. DETAILED DESCRIPTION The DS1307 is a low-power clock/calendar with 56 bytes of battery-backed SRAM. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information . The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year . The DS1307 operates as a slave device on the I 2C bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP conditi on is executed. When Vcc falls below 1.25 x V BAT, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. When Vcc falls below VBAT, the device switches into a low-current battery-backup mode. Upon power-up, the devic e switches from battery to Vcc when Vcc is greater than V BAT +0.2V and recognizes inputs when Vcc is greater than 1.25 x VBAT. The block diagram in Figure 1 shows the main elements of the serial RTC. OSCILLATOR CIRCUIT The DS1307 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the exte rnal crystal. Figure 3 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second.

(CH bit=0) during initial configuration. the remaining time and date registers must be written within one second. Table 2. Timekeeper Registers

24 PM/AM

10 Hour Hours Hours 1-12

The DS1307 control register is used to control the operation of the SQW/OUT pin. SQWE=0, the logic level on the SQW/OUT pin is 1 if OUT=1 and is 0 if OUT =0. registers update on the falling edge of the square wave. been enabled. The following table lists the square-wave frequencies that can be selected with the RS bits.

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 9 I2C DATA BUS The DS1307 supports the I 2C protocol. A device that sends data onto to bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a mater. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master ar e referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), Controls the bus access, and ge nerates the START and STOP conditions. The DS1307 operates as a slave on the I2C bus. Figure 4,5, and 6 detail how data is transferred on the I2C bus. z Data transfer may be initiated only when the bus is not busy. z During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from High to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, af ter a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the 2-wire bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1307 operates in the standard mode (100kHz) only. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable Low during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 12 TYPICAL OPERATING CIRCUIT

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 13 PIN CONFIGURATIONS TOP VIEW

PACKAGE INFORMATION

LTR DESCRIPTION DATE APPRCMD A NEW DRAWING 12/01 8-PIN MIN MAX A - 0.170 A1 0.015 - A2 0.115 0.195 b 0.015 0.022 c 0.008 0.012 D 0.360 0.380 E 0.300 0.325 E1 0.240 0.260 e 0.090 0.110 L 0.125 0.135 eB - 0..430 ALL DIMENSIONS ARE IN INCHES

64 x 8, Serial, I2C Real-Time Clock www.artschip.com 14 PACKAGE INFORMATION (continued) REVISIONS LTR DESCRIPTION DATE APPRCMD A NEW DRAWING 2/95 J.W. B UPDATE DIMENSIONS PKG 8 PIN 14 PIN 16 PIN LTR MIN MAX MIN MAX MIN MAX A b c D IN. 0.050 BSC 0.050 BSC 0.050 BSC e MM 1.27 BSC 1.27 BSC 1.27 BSC H L THE CHAMFER ON THE BODY IS OPTIONAL. IF IT IS NOT PRESENT, A TERMINAL 1 IDENTIFIER MUST BE POSITIONED SO THAT 1/2 OR MORE OF IT’S AREA IS CONTAINED IN THE HATCHED ZONE.