MC1445 HARRIS | Alldatasheet
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Ce ORDERING INFORMATION : pe MC1445F O°C to +75°C Cerarme Flat a oe MC14456, OC to + 75°C Metal Can t ee MC1445t, O°C to +75°C Coramic OIF | Seng ee MC1S45F ~S8°C to 4125°C Ceramic Flat 4 “ae * MC1545G ~55°C to + 125°C Metal Can | Mci445 \\7 eee MC1545L 55°C to +125°C Ceramic DIP ee |i oe es Pr eo - GATE CONTROLLED TWO-CHANNEL-INPUT. eos WIDEBANO AMPLIFIER i GATE CONTROLLED ae F NEL-INPUT es. video switch, sense amplifier, multiplexer, modulator, FSK circuit, WiDES. €R e. Het A spapracieay Oe Ss BAbIMaNa ities SILICON MONOLITHIC i ae w arye Bandi 60 MUTAVERED INTEGRATED CIRCUIT : ee # Channel Select Time af 20 ns typical i i See eT f Bas TYPICAL APPLICATIONS ) G SUFFIX g ae ericson IAL a Marat racKaat a VIDEO SWITCH OF CASE 603 : oo pony io TT “ aan Se ” 3 ice se" wall “ — 7 4 input 8 i. vee | oo aan tort ed Sele jv |g Pas. Nontay SY Out Ee Bags tmout A er 4 i ae law. ape A j AaUTUDEMODULATOR | pusewiorwooucaTon i a i! | Age « sure ae bow i a mausie PACKAGE oo sere see y._| jm Yety ghee ee Bei np | Mga | ourout (1 [ane ee wo} ff oe om ine tot (SHS sre |) ec ca ceaamierackact fie a etanecomooutaron | navog smiten coro j a 1 woe fe [ 3 je vecy Yee | Meee g¥ee te : ee | | sdpierecameP | wae He Be. [ S a] _- ovwut [1 = ie a a 4 | ZO tne Input (4 Lule a. > ae input Bian Agjunt = alveqe ee 6-20 4 i ; i us i
| c1445, Mc1545 Rating Symbot_| Value Unit Power Supply Voltage Vee 2 vac : vee 2 Ve GATE CONTROLLED ~~ fF Input Dilferential Voltage Range = Vion 750 | vor TWO-CHANNEL-INPUT Load Current - in 25 | ma WIDEBAND AMPLIFIER Power Orssipation (Package Limitation! Po ‘ Fiat Package $00 ow SILICQN MONOLITHIC i is Derate above Ta = +25°C 33 ewe INTEGRATED CIRCUIT Ceramic Qual In-Line Package | 625, mw Orrate above Ta = +25°C 50 owe | : Mtn 680 mm | amen Derate above Ta = +2596 46 | Operating Ambient Temperature Range MC 1445 Ta Oto +75 Ld Ss 6 surFix mctsas 95 ta #125 METAL PACK lca aeenmenniantcaniienneiaesaens eT enue cual ‘Storage Temperature Range Tarp 65to +150] °C {109 view) ee oO r pal ELECTRICAL CHARACTERISTICS (voc = +50 Vue. Veg © 5.0 Ve. at Ta ~ #25°C, specifications apply to both input channe's ey. vunicis otherwe noted 1 aoe A | a = fa ee een ee ane one COE | r C1545 mci SS | L_ eee Fa No. | Symbol tye [Mex [ein] tye [Max | Una C\\+_'S) Ce) ins UR i nL ee Opa a beac Eades vonage Goin ue | An 1 [7 | | ws | |e pay] La” | Gye [nur tmpedonce sa], {ao | to 30 | 10 tone Oe al [te 50 KHa! _ _ : — et ©) curoet [Output impedance z 615 | t - 25 a | 3 ‘Onms | Poti AS [ite s0eMe _ a tow. Input A Bal tare Dutour Differentiat Voltage Range 413 | Vooa | 15 25 25 Vee * < Furie Teput Bias Current 16 Ve - 1s ES 18 Ade So SFE cenamic PacK: x eno case sco Taput Offset Current - 20 fee vad input Oitvet Voltage boa] ae a me ovwout (i Tai | Guescent Output de Level [ror one [z aah} Output de Level Change avo ov nour 8 [3 > File | (Gate Input Voltage Change +50 V 10.0 VI Inout 8 [aie | Carman Mode Rejection Ratio CHAR 3 ae trout a[s FFolee Po (f= 50 kHz} a taper ALS [seat = Input Common-Mode Voltage Range fia vicn { [as [as vp = Gate Characteristics yy 0.70 02 o4 Ve outous fr ————) Five LG) cs i Gare lnput Vottepe~ tow Logic Sate (Note 1 fe Gate tnput Vottage ~ High Logie State (Note 2) Yumi 1s | 22 - 1a_| 30 k surrix Gite Input Corrent ~ Low Logic State a 7 190 ma CERAMIC PACKAGE (yy “ o v Meee Shs WUIG) 25 ‘CASE 632 _—Witigh OVE oe Tote Gate Input Current = High Logie State 18 | tines 70 { «0 ry ne (Vinig) * +50) i ; Step Response ~ icy PL 65 es | - | = uteet = lag tol ‘eli 63 o | - Gate (2 {ra]e trux 65 6s = Fale tHe 190 zo | - topue8 [2 Widtband Tapat Nowe 7s = 25 a Pn) tnpur [a [rine {5.0 Hz — 10 MHz, Ag = 50 ohms} ; = BE Power Consumption be = ES snout a a PPSS [ale tGraumptie, ar Jee oe ee | mmouta leh [9}¥ee Note 1. Vig (gyi the gate voltage wich rests in channel gain of unity artes ad channel gun of 16 d8 or greater | as lote 2. Vyy4igy 16 the gate voltage which resits m channel B gain of unity oF less and channel A gain of 16 d8 or greater ovat [> -——— file) \\iatG) he gate votan ° ain 0 9 batt 6-21 i i
CS ae MC1445 , MC 1545 | 4 Bs FIGURE 1 ~ SINGLE ENOEO. FIGURE 2 ~ SINGLE ENDED SS VOLTAGE GAIN versus FREQUENCY VOLTAGE GAIN versus TEMPERATURE Ee 4 ay TTT Salil % r a Be 2 Seti fit a tq 8 i | \\ | i s i 3 Fi Daniele CTA PETRY ei = al ae ee meer sees 4 riguae a vourace Gain FoURE 4 ourPUT VOLTAGE smHNG eo. versus POWER SUPPLY VOLTAGES versus LOAD RESISTANCE ks os 2 | j i se Per tay ) LUNE et eee 5 ec 10 | con eee Bree oe Ht BBO S| q te 2 140 150 960 370 e809. or 02 rT Ty so of) aoe 4 a3 Ves. Vee Pare URCNLNCEea wba won Bes i poo FIGURE 5 ~ INPUT Cp AND Rp versus FREQUENCY FIGURE 6 - OUTPUT IMPEDANCE versus FREQUENCY F eee (BOTH CHANNELS! a Re "oT TET OT TTT, 2 OHH) RAMU OTT OMNI MRR Pe 2 ptt +— ++ we Sel : oS eer rin ry ins & fa CHCA Hee oS gob —p a ee 8 Pee Beek 2 rT Tqyi | Phra ¢ HTT 4H {Lh H Aten. ' East wwe soy tt ttt LL He Te ee He et - 8 PERCEPT TT ae v0 $0 w rn) oor on ho 0 ie i
MC1445 , MC1545 Op Terns ryp 20 a teem se rf | of | P°F Oe | “ARHIFP HE “| ee | | Lim i) 8 : Af - tio INPUT FREQUENCY imyy GATE voctaGe woxrs) : : no neal oue a connor noe NEUE ip wourmoreenn yo Lea LORD RESISTAACE ween ove FREQUENCY versus SOURCE RESISTANCE ini ni Cae: ae crt Pyar ttt 3 | He | i| i. LU Mee Spt et ty 3 obi Lil make i LHW 4 i : 3 tite tt Lg, SoU MeN | Mill iI iB bn Hint CONC RB EL ETT alli AAA Hee @ sai ny on fs _ . a MUU TS tii bit ! os 1020 SO 00 vo We 100 « wm, snkpnesctemn amet a 1, FREQUENCY (Ma) Rs, SOURCE RESISTANCE (OHMS) UTPUT IMPEDANCE vers FREQUENEY FIGURE 11 ~ CIRCUIT SCHEMATIC FIGURE 12 — SINGLE ENDED VOLTAGE GAIN AND ONC PSL |e | CC cna aS am & he | Tice aes ae petri a. 6-23 q
ae: MC1445 . MC1545 Bite } a FIGURE 13 — OUTPUT VOLTAGE SWING TEST ciACUIT FIGURE 14 ~ INPUT IMPEOANCE TEST CIRCUIT 2 al f= 50Kn tie adel 3 Bee | 5 eee a V+ 50 mvtrm Ge 7 Bee a f= s0KK ~o-g-0 x oe Yi = 200 mVtemel a he rece ; oe al 7 : i toe Bei vortmeter ee FIGURE 15 — OUTPUT IMPEDANCE Test CIRCUIT FIGURE 16 ~ INPUT BIAS CURRENT AND INPUT : ¥ ae OFFSET CURRENT TEST CIRCUIT Ce ssov -30v titae st ad Voltmeter a Ce ‘ ‘ae dour fo ° a | tio isthe altterenc ios af t= 50 kMe 1 in current reading 4 pee: * ~ (rena) 8 when either $1 oF. ae Vi = 50 mv Leek meiner f a FIGURE 18 ~ GATE CURRENT (NIGH AND LOW), aot FIGURE 17 — INPUT OFFSET VOLTAGE AND QUIESCENT COMMON-MODE REJECTION ANO- ae as OUTPUT LEVEL TEST CIRCUIT COMMON-MODE INPUT RANGE TEST CIRCUIT oe OV Fi 4 ae : as Fae raed Bae ae sia mae he Pararry ee Votse * ¥2 ct ae Asie ° : Cor L--- Le A conn 20 tof Aa : 4 ¥ ee rt a a + 4 Switeh Sy and readivet A, for V4-0 5.0V bei iam e | i i i i
: MC1445, MC1545 INPUT IMPEDANCE TEST cincury FIGURE 19 — PROPAGATION DELAY AND RISE ANO FIGURE 20 ~ POWER DISSIPATION ANO WIDEBAND FALL TIMES TEST CIRCUIT INPUT NOISE Test CIRCUIT snb¥ sov ssov tov To"A" Chonnat 68.0 with Boncvetamn ot Scope — bod $.0 Ma to 10 Mie Te tronis 667 £ i Gen, Q r™~ * Vie 2omv So sitcom — ‘ tt St “e
3 CL = 18 pF Inciuding probe ane ro Stee tag)
FIGURE 21 ~ LiMiTING CHARACTERISTIC PCT TTT rr 7 CURRENT TEST CIRCUIT 3 sop—4 tpt + son ten 3 4+ ee TF csoy iy f ‘ ee ee 1 a 4 3 3 | | L i } Fp —4+— 41 1 yy 7 rene ib sox LILY | 1 10% Pts : ] vost) 2A eS f--—+4 x a al | bi 10 35 a yo 4 the cterene Ws SINGLE ENOED INPUT VOLTAGE fave) __ woes orth re E CURRENT (HIGH ANO LOW), ° f *ODE REJECTION AND NPUT RANGE TEST CIRCUIT 1 “nov “nov ~ =A conn = 20109f Aa i Ne, ssov aes 6.25 '