MAS9179 MAS | Alldatasheet

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Technical content

1 (9) DA9179.002

19 May, 2005

  • Tri Band Receiver IC
  • High Sensitivity
  • Very Low Power Consumption
  • Wide Supply Voltage Range
  • Power Down Control
  • Control for AGC On
  • High Selectivity by Crystal Filter
  • Fast Startup Feature

DESCRIPTION

The MAS9179 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiving. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS9179 supports tri band operation by switching between three crystal filters and two additional antenna tuning capacitors. MAS9179 has differential input and different internal compensation capacitor options for compensating shunt capacitances of different crystals (See ordering information on page 9). FEATURES APPLICATIONS

  • Tri Band Receiver IC
  • Highly Sensitive AM Receiver, 0.4 µVRMS typ.
  • Wide Supply Voltage Range from 1.1 V to 5 V
  • Very Low Power Consumption
  • Power Down Control
  • Fast Startup
  • Only a Few External Components Necessary
  • Control for AGC On
  • Wide Frequency Range from 40 kHz to 100 kHz
  • High Selectivity by Quartz Crystal Filter
  • Multi Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HGB (Switzerland) and BPC (China) BLOCK DIAGRAM AGC Amplifier Power Supply/Biasing Demodulator Comparator RFIM RFI2 VDD VSS PDN1 AGC DEC OUT QO3 QI AONQO1QO2 RFI3 PDN2 RFIP

2 (9) DA9179.002 1892 µm 1620 µm PDN2 DEC QO3 RFIP AON MAS9179Ax, x=1..4 VDD DIE size = 1.62 x 1.89 mm; round PAD ∅ 80 µm Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is t he first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Name X-coordinate Y-coordinate Note Power Supply Voltage VDD 174 µm 1657 µm Quartz Filter Output for Crystal 2 QO2 174 µm 1452 µm Quartz Filter Output for Crystal 1 QO1 174 µm 1248 µm Quartz Filter Output for Crystal 3 QO3 174 µm 1043 µm Quartz Filter Input for Crystals QI 174 µm 839 µm AGC Capacitor AGC 174 µm 634 µm Power Down/Frequency Selection Input 2 PDN2 174 µm 429 µm 3 Receiver Output OUT 175 µm 225 µm 1 Demodulator Capacitor DEC 1442 µm 240 µm AGC On Control AON 1442 µm 444 µm 2 Power Down/Frequency Selection Input 1 PDN1 1442 µm 649 µm 3 Receiver Input 3 (for Antenna Capacitor 3) RFI3 1442 µm 853 µm Positive Receiver Input RFIP 1442 µm 1058 µm 4 Negative Receiver Input RFIM 1442 µm 1262 µm 4 Receiver Input 2 (for Antenna Capacitor 2) RFI2 1442 µm 1467 µm Power Supply Ground VSS 1442 µm 1671 µm Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |I OUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 3) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power up 4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing MOSFET-transistors towards ground

3 (9) DA9179.002 The frequency selection and power down control is accomplished via two digital control pins PDN1 and PDN2. The control logic is presented in table 1. Table 1 Frequency selection and power down control PDN1 PDN2 RFI2 Switch RFI3 Switch Selected Crystal Output High High Open Open - Power down High Low Open Open QO1 Frequency 1 Low High Closed Open QO2 Frequency 2, RFI2 capacitor connected in parallel with antenna Low Low Closed Closed QO3 Frequency 3, RFI2 and RFI3 capacitors connected in parallel with antenna The internal antenna tuning capacitor switches (RFI2, RFI3) and crystal filter output switches (QO1, QO2, QO3) are controlled according table 1. See switches in block diagram on page 1. If frequency 1 is selected the RFI2 and RFI3 switches are open and only crystal output QO1 is active. Antenna frequency is determined by antenna inductor L ANT (see Typical Application on page 5), antenna capacitor C ANT1 and parasitic capacitances related to antenna inputs RFIP, RFIM, RFI2 and RFI3 (see Antenna Tuning Considerations below). Frequency 1 is the highest frequency of the three selected frequencies. If frequency 2 is selected then RFI2 switch is closed to connect C ANT2 to pin RFIM in parallel with ferrite antenna and tune it to frequency 2. Then only crystal output QO2 is ac tive. Frequency 2 is the medium frequency of the three selected frequencies. If frequency 3 is selected both RFI2 and RFI3 switches are closed to connect both C ANT2 and CANT3 capacitors to RFIM pin in parallel with ferrite antenna and tune it to frequency 3. Then only crystal QO3 is active. Frequency 3 is the lowest frequency of the three selected frequencies. It is recommended to switch the device to power down for 50ms before switching to another frequency. This guarantees fast startup in switching to another frequency. The 50ms power down period is used to discharge AGC capacitor and to initialize fast startup conditions.

4 (9) DA9179.002 ANTENNA TUNING CONSIDERATIONS The ferrite bar antenna having inductance L ANT and parasitic coil capacitance C COIL is tuned to three reception frequencies f 1, f 2 and f 3 by parallel capacitors C ANT1, C ANT2 and C ANT3. The receiver input stage and internal antenna capacitor switches have capacitances C RFIP, COFF2, COFF3 which affect the resonance frequencies. C OFF2 and C OFF3 are switch capacitances when switches are open. When switches are closed these capacitances are shorted by on resistance of the switches and they are effectively eliminated. Following relationships can be written into three tuning frequencies. Frequency f 1 (highest frequency): CTOT1=CCOIL+CANT1+CRFIP+COFF2+COFF3=CCOIL+CANT1+6pF+37pF+119pF=CCOIL+CANT1+162pF, TOTANT CL f π Frequency f2 (middle frequency): CTOT2=CCOIL+CANT1+CANT2+CRFIP+COFF3=CCOIL+CANT1+CANT2+ 6pF+119pF=CCOIL+CANT1+CANT2+ 125pF, TOTANT CL f π Frequency f3 (lowest frequency): CTOT3=CCOIL+CANT1+ CANT2+ CANT3+CRFIP=CCOIL+CANT1+ CANT2+ CANT3+6pF, TOTANT CL f π

5 (9) DA9179.002 Parameter Symbol Conditions Min Max Unit Supply Voltage V DD-VSS -0.3 6 V Input Voltage V IN V SS-0.3 V DD+0.3 V Power Dissipation P MAX 100 mW Operating Temperature T OP -40 +85 oC Storage Temperature T ST -55 +150 oC

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 1.4V, Temperature = 25°C Parameter Symbol Conditions Min Typ Max Unit Operating Voltage V DD 1.10 5 V Current Consumption I DD VDD=1.4 V, Vin=0 µVrms VDD=1.4 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µVrms VDD=3.6 V, Vin=20 mVrms µA Stand-By Current I DDoff 0.1 µA Input Frequency Range f IN 40 100 kHz Minimum Input Voltage V IN min 0.4 1 µVrms Maximum Input Voltage V IN max 20 mVrms Receiver Input Resistance Receiver Input Capacitance RRFI CRFI f=40kHz..77.5 kHz 230 kΩ pF RFI2 Switch On Resistance RFI2 Switch Off Capacitance RON2 COFF2 VDD=1.4 V 3.8 Ω pF RFI3 Switch On Resistance RFI3 Switch Off Capacitance RON3 COFF3 VDD=1.4 V 2.4 119 Ω pF Input Levels |lIN|<0.5 µA VIL VIH

0.8 VDD

0.2 VDD V Output Current VOL<0.2 VDD;VOH >0.8 VDD |IOUT| 5 µA Output Pulse T 100ms 1 µVrms ≤ VIN ≤ 20 mVrms 50 140 ms T 200ms 1 µVrms ≤ VIN ≤ 20 mVrms 150 230 ms T 500ms 1 µVrms ≤ VIN ≤ 20 mVrms 400 500 600 ms T 800ms 1 µVrms ≤ VIN ≤ 20 mVrms 700 800 900 ms Startup Time T Start Fast Start-up, Vin=0.4 µVrms Fast Start-up, Vin=20 mVrms 1.3 3.5 s Output Delay Time T Delay 50 100 ms

6 (9) DA9179.002 +VBATTERY Receiver Output CAGC CDEC Power Down / Fast Startup / Frequency Selection Optional Control for AGC on/hold Ferrite Antenna CANT1 CANT3LANT CANT2 AGC Amplifier Power Supply/Biasing Demodulator Comparator RFIM RFI2 VDD VSS PDN1 AGC DEC OUT QO3 QI AONQO1QO2 RFI3 PDN2 RFIP Note 1 Note 2 Figure 1 Application circuit of tri band receiver MAS9179 +1.4 V Receiver Output CAGC 10 µF CDEC 47 nF Power Down / Fast Startup / Frequency Selection Optional Control for AGC on/hold 40.003 kHz 77.503kHz 60.003kHz Ferrite Antenna CANT1 1.2nF CANT3 0.91nF LANT 3.07mH CANT2 3nF AGC Amplifier Power Supply/Biasing Demodulator Comparator RFIM RFI2 VDD VSS PDN1 AGC DEC OUT QO3 QI AONQO1QO2 RFI3 PDN2 RFIP Figure 2 Example circuit of tri band receiver MAS9179 for DCF77/MSF/WWVB/JJY frequencies

The crystals as well as ferrite antenna frequencies are c hosen according to the time-signal system (Table 2). compensation capacitor CC of MAS9179. See Compensation Capacitance Options on table 3. each crystal is connected to common crystal input pin QI. Table 4 below presents some crystal manufacturers having suitable crystals for timesignal receiver application. Table 4. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application

8 (9) DA9179.002 MAS9179 SAMPLES IN SBDIL 20 PACKAGE NC 1 VDD 2 QO2 3 QO1 4 QO3 5 NC 6 QI 7 AGC 8 PDN2 9 OUT 10

20 VSS

19 RFI2

18 RFIM

17 RFIP

16 RFI3

14 PDN1

13 AON

12 DEC

XXXXX.X Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number z = Sample Version Number PIN DESCRIPTION Pin Name Pin Type Function Note NC 1 VDD 2 P Positive Power Supply QO2 3 AO Quartz Filter Output for Crystal 2 QO1 4 AO Quartz Filter Output for Crystal 1 QO3 5 AO Quartz Filter Output for Crystal 3 NC 6 1 QI 7 AI Quartz Filter Input for Crystal AGC 8 AO AGC Capacitor PDN2 9 DI Power Down/Frequency Selection Input 2 3 OUT 10 DO Receiver Output 2 NC 11 DEC 12 AO Demodulator Capacitor AON 13 DI AGC On Control 4 PDN1 14 DI Power Down/Frequency Selection Input 1 3 NC 15 RFI3 16 AI Receiver Input 3 (for Antenna Capacitor 3) RFIP 17 AI Positive Receiver Input 5 RFIM 18 AI Negative Receiver Input 5 RFI2 19 AI Receiver Input 2 (for Antenna Capacitor 2) VSS 20 G Power Supply Ground A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pin 6 between QO3 and QI must be connected to VSS to eliminate DIL package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |I OUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power up 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 5) Receiver inputs RFIP and RFIM have both 600 k Ω biasing MOSFET-transistors towards ground

9 (9) DA9179.002

ORDERING INFORMATION

Product Code Product Description Capacitance Option MAS9179A1TC00 Tri Band AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. CC = 0.75 pF MAS9179A2TC00 Tri Band AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. CC = 0.875 pF MAS9179A3TC00 Tri Band AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. CC = 1.25 pF MAS9179A4TC00 Tri Band AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. CC = 1.5 pF Contact Micro Analog Systems Oy for other wafer thickness options. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringem ent. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.