MAS9078 MAS | Alldatasheet

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Technical content

DA9078.003

28 January 2004

1 (10) MAS9078 AM Receiver IC

  • High Sensitivity
  • Very Low Power Consumption
  • Wide Supply Voltage Range
  • Power Down Control
  • Control for AGC On
  • High Selectivity by Crystal Filter
  • Fast Startup Feature

DESCRIPTION

The MAS9078 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. Unlike MAS1016A and MAS1016B, MAS9078 does not require AGC control procedure in WWVB and JJY systems. FEATURES APPLICATIONS

  • Highly Sensitive AM Receiver, 0.4 µVRMS typ.
  • Wide Supply Voltage Range from 1.1 V to 3.6 V
  • Very Low Power Consumption
  • Power Down Control
  • Fast Startup
  • Only a Few External Components Necessary
  • Control for AGC On
  • Wide Frequency Range from 40 kHz to 100 kHz
  • High Selectivity by Quartz Crystal Filter
  • Die and TSSOP-16 Package
  • Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany) and MSF (UK)
  • Receiver for ASK Modulated Data Signals BLOCK DIAGRAM AGC Amplifier Demodulator Comparator Power Supply/Biasing RFI OUT QIQO PDNVDD VSS AGC DEC AON (=AGC on)

DA9078.003 2 (10) PAD LAYOUT DIE size = 1.70 x 1.78 mm; PAD size = 100 x 100 µm Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is t he first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in the center of VDD pad Note: The on-chip product code 9078Bx identifies internal compensation capacitance option. x has values 1, 2, 3, 4 or 5 refering to capacitance option described in the Table 2 on page 4. Pin Description Name X-coordinate Y-coordinate Note Power Supply Voltage VDD 0 µm 0 µm Quarz Filter Output QO 306 µm 19 µm Quarz Filter Input QI 586 µm 19 µm AGC Capacitor AGC 866 µm 19 µm Receiver Output OUT 1109 µm 19 µm 1 Demodulator Capacitor DEC 1109 µm 1428 µm AGC On Control AON 866 µm 1428 µm 2 Power Down Input PDN 549 µm 1428 µm 3 Receiver Input RFI 306 µm 1428 µm Power Supply Ground VSS 16 µm 1407 µm Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |I OUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 3) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. MAS VDD QO QI AGC OUT VSS RFI PDN AON DEC 1702 µm 1778 µm 9078Bx

DA9078.003 3 (10) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Min Max Unit Supply Voltage V DD-VSS -0.3 5.0 V Input Voltage V IN V SS-0.3 V DD+0.3 V Power Dissipation P MAX 100 mW Operating Temperature T OP -20 70 oC Storage Temperature T ST -40 120 oC

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 1.4V, Temperature = 25°C Parameter Symbol Conditions Min Typ Max Unit Operating Voltage V DD 1.10 3.60 V Current Consumption I DD VDD=3.6 V, Vin=0 µV VDD=1.4 V, Vin=0 µV 56 76 95 µA Stand-By Current I DDoff 0.1 µA Input Frequency Range f IN 40 100 kHz Minimum Input Voltage V IN min 0.4 1 µVrms Maximum Input Voltage V IN max 20 mVrms Input Levels |lIN|<0.5 µA VIL VIH

0.8 VDD

0.2 V DD V

VOL<0.2 VDD;VOH >0.8 VDD |IOUT| 5 µA Output Pulse T 100ms 1 µVrms ≤ VIN ≤ 20 mVrms 50 140 ms T 200ms 1 µVrms ≤ VIN ≤ 20 mVrms 150 230 ms T 500ms 1 µVrms ≤ VIN ≤ 20 mVrms 400 500 600 ms T 800ms 1 µVrms ≤ VIN ≤ 20 mVrms 700 800 900 ms Startup Time T Start Fast Start-up Without Fast Start-up s min Output Delay Time T Delay 50 100 ms

DA9078.003 4 (10) TYPICAL APPLICATION Note 1: Crystal The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The crystal shunt capacitance C 0 should be matched as well as possible with the internal shunt capacitance compensation capacitance C C. MAS9078 has five compensation capac itance options. Capacitance values and suitable crystals are described in Table 2. See also Ordering Information (p.10). Time-Signal System Location Antenna Frequency Recommended Crystal Frequency DCF77 Germany 77.5 kHz 77.503 kHz MSF United Kingdom 60 kHz 60.003 kHz WWVB USA 60 kHz 60.003 kHz JJY Japan 40 kHz and 60 kHz 40.003 kHz and 60.003 kHz Table 1 Time-Signal System Frequencies Device C C Crystal Description MAS9078B1 0.75 pF For single low C 0 crystal (Nominal value) MAS9078B2 1.25 pF For single high C 0 crystal MAS9078B3 1.625 pF For two parallel low C 0 crystals (dual band receiver) MAS9078B4 2.5 pF For two parallel high C 0 crystals (dual band receiver) MAS9078B5 3.875 pF Any crystal with para llel external compensation capacitor Table 2 Compensation Capacitance Options Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage curr ents due to very small 40 nA signal currents through the capacitors. The insulation resistance of these capacitors should be higher than 70 M Ω. Also probes with at least 100 MΩ impedance should be used for voltage probing of AGC and DEC pins. Note 3: Power Down / Fast Startup Control Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if PDN = VDD and in power up (turned on) if PDN = VSS. Fa st startup is triggered by the falling edge of PDN signal, i.e., controlling device from power down to power up. The startup time without using the fast startup control can be several minutes but with fast startup it is shortened typically to 12 s. AGC Amplifier Demodulator Comparator Power Supply/Biasing RFI OUT QIQO VSS AGC DEC Receiver output Ferrite- Antenna Note 1 AON (=AGC on) VDD 1.4 V PDN Note 2 CAGC 10 uF CDEM 47 nF Note 3 Power Down / Fast Startup Control

DA9078.003 5 (10) SAMPLES IN SBDIL 20 PACKAGE PIN DESCRIPTION Pin Name Pin Type Function Note NC 1 VDD 2 P Positive Power Supply NC 3 QO 4 AO Quartz Filter Output NC 5 1 QI 6 AI Quartz Filter Input AGC 7 AO AGC Capacitor OUT 8 DO Receiver Output 2 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 DEC 15 AO Demodulator Capacitor AON 16 DI AGC On Control 3 PDN 17 AI Power Down Input 4 RFI 18 AI Receiver Input NC 19 VSS 20 G Power Supply Ground Notes: 1) Pin 5 between quartz crystal filter pins must be connected to VSS to eliminate DIL package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |I OUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. NC 1 VDD 2 NC 3 QO 4 NC 5 QI 6 AGC 7 OUT 8 NC 9 NC 10

20 VSS

18 RFI

17 PDN

16 AON

15 DEC

Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number MAS9078 YYWW XXXXX.X

DA9078.003 6 (10) PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE PIN DESCRIPTION Pin Name Pin Type Function Note VDD 1 P Positive Power Supply NC 2 QO 3 AO Quartz Filter Output NC 4 1 QI 5 AI Quartz Filter Input AGC 6 AO AGC Capacitor NC 7 OUT 8 DO Receiver Output 2 DEC 9 AO Demodulator Capacitor NC 10 AON 11 DI AGC On Control 3 PDN 12 AI Power Down Input 4 NC 13 RFI 14 AI Receiver Input NC 15 VSS 16 G Power Supply Ground Notes: 1) Pin 4 between quartz crystal filter pins must be c onnected to VSS to eliminate package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |I OUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up (to AGC on) with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. NC VDD QO NC QI AGC NC OUT RFI VSS NC NC PDN AON NC DEC 9078 YYWW Top Marking Definitions: YYWW = Year Week

DA9078.003 7 (10) PACKAGE (TSSOP16) OUTLINES Dimension Min Max Unit A 6.40 BSC mm B 4.30 4.50 mm C 5.00 BSC mm D 0.05 0.15 mm E 1.10 mm F 0.19 0.30 mm G 0.65 BSC mm H 0.18 0.28 mm I 0.09 0.20 mm I1 0.09 0.16 mm J 0.19 0.30 mm J1 0.19 0.25 mm K 0° 8 ° L 0.24 0.26 mm M (The length of a terminal for soldering to a substrate) 0.50 0.75 mm N 1.00 REF mm O 12° P 12° Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153. B A C Pin 1 D Seating Plane E HGF B BDetail A L K M N P O Detail A II 1 J J1Section B-B

DA9078.003 8 (10) SOLDERING INFORMATION Resistance to Soldering Heat According to RSH test IEC 68-2-58/20 2*220°C Maximum Temperature 240°C Maximum Number of Reflow Cycles 2 Reflow profile Thermal profile param eters stated in JESD22-A113 should not be exceeded. http://www.jedec.org Seating Plane Co-planarity max 0.08 mm Lead Finish Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% EMBOSSED TAPE SPECIFICATIONS Dimension Min Max Unit A0 6.50 6.70 mm B0 5.20 5.40 mm D0 1.50 +0.10 / -0.00 mm D1 1.50 mm E1 1.65 1.85 mm F1 7.20 7.30 mm K0 1.20 1.40 mm P 11.90 12.10 mm P0 4.0 mm P2 1.95 2.05 mm S1 0.6 mm T 0.25 0.35 mm W 11.70 12.30 mm P A A Section A - A W Tape Feed Direction T Tape Feed Direction Pin 1 Designator

DA9078.003 9 (10) REEL SPECIFICATIONS Dimension Min Max Unit A 330 mm B 1.5 mm C 12.80 13.50 mm D 20.2 mm N 50 mm (measured at hub) 12.4 14.4 mm (measured at hub) 18.4 mm Trailer 160 mm Leader 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm Weight 1500 g DA B C N Tape Slot for Tape Start ComponentsTrailer Leader Carrier Tape Cover Tape StartEnd

2000 Components on Each Reel

Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative

DA9078.003 10 (10)

ORDERING INFORMATION

Product Code Product Package Capacitance Option MAS9078BTB1 AM-Receiver IC EWS-tested wafer, Thickness 480 µm C C = 0.75 pF (Nominal) MAS9078BTB2 AM-Receiver IC EWS-tested wafer, Thickness 480 µm C C = 1.25 pF MAS9078BTB3 AM-Receiver IC EWS-tested wafer, Thickness 480 µm C C = 1.625 pF MAS9078BTB4 AM-Receiver IC EWS-tested wafer, Thickness 480 µm C C = 2.5 pF MAS9078BTB5 AM-Receiver IC EWS-tested wafer, Thickness 480 µm C C = 3.875 pF MAS9078BTC1 AM-Receiver IC EWS-tested wafer, Thickness 400 µm C C = 0.75 pF MAS9078BTC2 AM-Receiver IC EWS-tested wafer, Thickness 400 µm C C = 1.25 pF MAS9078BTC3 AM-Receiver IC EWS-tested wafer, Thickness 400 µm C C = 1.625 pF MAS9078BTC4 AM-Receiver IC EWS-tested wafer, Thickness 400 µm C C = 2.5 pF MAS9078BTC5 AM-Receiver IC EWS-tested wafer, Thickness 400 µm C C = 3.875 pF MAS9078BUA1-T AM-Receiver IC TSSOP-16, Tape & Reel C C = 0.75 pF (Nominal) Contact Micro Analog Systems Oy for other wafer thickness options. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringem ent. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.