MAS7838 MAS | Alldatasheet

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Technical content

DA7838.002

20 September, 2000

1 (9) /G48/G36/G54/G26/G27/G22/G27 /G54/G60/G49/G38/G43/G53/G50/G49/G50/G56/G54/G3/G55/G50/G3/G36/G54/G60/G49/G38/G43/G53/G50/G49/G50/G56/G54 /G38/G50/G49/G57/G40/G53/G55/G40/G53/G3/G54/G36/G38/G3/G38/G48/G50/G54

  • /G44/G81/G87/G72/G85/G73/G68/G70/G72/G86/G3/G68/G3/G71/G88/G83/G79/G72/G91/G3/G68/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G70/G75/G68/G81/G81/G72/G79 /G87/G82/G3/G68/G3/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G70/G75/G68/G81/G81/G72/G79
  • /G48/G82/G71/G72/G80/G3/G86/G92/G86/G87/G72/G80/G86/G3/G68/G87/G3/G86/G83/G72/G72/G71/G86/G3/G82/G73/G3/G25/G19/G19/G15/G3/G20/G17/G21/G78/G15 /G21/G17/G23/G78/G15/G3/G23/G17/G27/G78/G15/G3/G28/G17/G25/G78/G3/G68/G81/G71/G3/G20/G28/G17/G21/G78
  • /G38/G75/G68/G85/G68/G70/G87/G72/G85/G3/G79/G72/G81/G74/G87/G75/G3/G73/G85/G82/G80/G3/G27/G3/G87/G82/G3/G20/G20/G3/G69/G76/G87/G86 /G76/G81/G70/G79/G88/G71/G76/G81/G74/G3/G86/G87/G68/G85/G87/G3/G86/G87/G82/G83/G3/G68/G81/G71/G3/G83/G68/G85/G76/G87/G92/G3/G69/G76/G87/G86 /G39/G40/G54/G38/G53/G44/G51/G55/G44/G50/G49 The MAS7838 is a single chip duplex synchronous to asynchronous converter. It converts asynchronous start stop characters to synchronous character format, with stop bit deletion when required as defined in the CCITT recommendation V.14 (V.22). On the receiver channel the MAS7838 converts the incoming synchronous data to asynchronous start stop character format with stop bit insertion when required as defined in the CCITT recommendation V.14 (V.22).The MAS7838 implements the data modes for the synchronous interface as specified in the V.14 (V.22). The device can be configured to operate at any frequency to maximum device speed within the above mentioned modes. /G41/G40/G36/G55/G56/G53/G40/G54 /G36/G51/G51/G47/G44/G38/G36/G55/G44/G50/G49
  • Implements CCITT recommendations V.14 and V.22 chapters 4.1, 4.2 and 4.3
  • Operates in modes as defined in the CCITT recommendations V.22 (i), ii), iii), iv) and v)
  • Transmission rate up to 64 kbit/s
  • CMOS compatible interface
  • Low power consumption (typically 25 mW)
  • No additional circuitry required to perform the conversion
  • CMOS device
  • Single =5V supply
  • Adapts asynchronous terminals to synchronous modems
  • Full or half card PC modems using UART as a data source
  • Simplifying data multiplexing in a MUX/DEMUX system /G37/G47/G50/G38/G46/G3/G39/G44/G36/G42/G53/G36/G48 CL1 CL2 XESR TMG OSC TSL TXC TDO RXC RDI XASY XHST VSS VDD TDI RDO CONTROL O S C ASYNC TO SYNC SYNC TO ASYNC > 1_

DA7838.002 2 (9) /G51/G44/G49/G3/G38/G50/G49/G41/G44/G42/G56/G53/G36/G55/G44/G50/G49 Top marking: YYWW = Year Week, XXXXX.X = Lot Number, =ESD Indicator /G51/G44/G49/G3/G39/G40/G54/G38/G53/G44/G51/G55/G44/G50/G49 /G51/G76/G81/G3/G81/G68/G80/G72 /G51/G76/G81/G3/G81/G82/G17 /G44/G18/G50 /G41/G88/G81/G70/G87/G76/G82/G81 TSL 1 I Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG. 1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG. Max f=10 MHz. OSC 3 O Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3. TXC 4 I Transmitter timing. Synchronous square wave timing for transmitter. The transmitted data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC has to be 50% +/- 5%. CL1 5 I CL2 6 I Character length. The total character length including one start bit, one stop bit and possible parity bit is selected with the CL1 and CL2 signals. XESR 7 I Extended signalling rate. The tolerance of the synchronous bit rate can be: VSS 8 G Ground TDI 9 I Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal TDO 10 O Transmitter data output. The output data is synchronized to the synchronous timing signal TXC (pin 4). 1 = mark, 0 = space XASY 11 I Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous transmission. In synchronous transmission the converter is totally bypassed in both directions: TDI=TDO, RDI=RDO XHST 12 I Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing must be 1-2% higher than the normal bit rate in order to allow some overspeed in the asynchronous data. On the receiver side the RX buffer is deleted and the synchronous data RDI is directly connected to the asynchronous output RDO. RDO 13 O Receiver data output. RDO is the received data converted back to asynchronous mode. 1 = mark or stop bit, 0 = space, start or break signal RDI 14 I Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to the receiver timing RXC from the synchronous channel (pin 15). RXC 15 I Receiver timing. Receiver square wave timing from the synchronous channel. The received data RDI must be synchronized to the rising edge of RXC. VDD 16 P Power supply PDIP 16 TSL TMG OSC TXC CL1 CL2 XESR VSS 8 9

16 VDD

/c3/c3/c3/c3 /c3/c3/c3/c26/c27/c22/c27 /c59/c59 /c59/c59/c59/c17/c59 /c3/c3/c3/c60/c60 /c58 /c58 /c3/c3/c3/c3 /c3 /c3/c3 /c26/c27/c22/c27 /c59/c59 /c59/c59/c59/c17/c59 /c3/c3/c3/c60/c60 /c58 /c58

DA7838.002 3 (9) /G36/G37/G54/G50/G47/G56/G55/G40/G3/G48/G36/G59/G44/G48/G56/G48/G3/G53/G36/G55/G44/G49/G42/G54 (GND = 0V) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G48/G68/G91 /G56/G81/G76/G87 Supply Voltage VDD -0.5 5.5 V Storage Temperature Ts -55 +150 oC /G53/G40/G38/G50/G48/G48/G40/G39/G40/G39/G3/G50/G51/G40/G53/G36/G55/G44/G50/G49/G3/G38/G50/G49/G39/G44/G55/G44/G50/G49/G54 /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 Supply Voltage VDD 4.75 5 5.25 V Supply Current IDD 4 6 mA Operating Temperature Ta 0 +70 oC /G40/G47/G40/G38/G55/G53/G44/G38/G36/G47/G3/G38/G43/G36/G53/G36/G38/G55/G40/G53/G44/G54/G55/G44/G38/G54 /G117/G3/G44/G81/G83/G88/G87/G86 (test conditions: VDD = +5V, VSS = 0V, 0O C to 70O C) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 Input high voltage V IH 3.5 V Input low voltage V IL 1.1 V Input leakage current I IL -100 pA Input capacitance load C I 5p F Internal pull-up resistor for digital inputs R pull-up VIN = 0.4v VIN = 2.5v 350 850 k /c117 /G3/G50/G88/G87/G83/G88/G87/G86 (test conditions: VDD = +5V, VSS = 0V, 0O C to 70O C) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 Output low voltage V OL IOL = -0.6mA 0.4 V Output high voltage V OH IOH = 0.4mA 4.6 V /c117 /G3/G39/G68/G87/G68/G3/G55/G76/G80/G76/G81/G74 (test conditions: VDD = +5V, VSS = 0V, 0O C to 70O C) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 Low to high logic transition time tR CL = 10pF 20 ns High to low logic transition time tF CL = 10pF 20 ns (test conditions: TSL = 1) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 TDO delay time after TXC T1 50 T TXC /16+350 ns RDI set up time before RXC T2 1/4 T RXC ns RDI hold time after RXC T3 1/4 T RXC ns (test conditions: TSL = 0, TMG = 16xTXC) /G51/G68/G85/G68/G80/G72/G87/G72/G85 /G54/G92/G80/G69/G82/G79 /G38/G82/G81/G71/G76/G87/G76/G82/G81/G86 /G48/G76/G81 /G55/G92/G83 /G48/G68/G91 /G56/G81/G76/G87 TDO delay time after TXC T1 50 1/TMG+350 ns RDI set up time before RXC T2 1/4 T RXC ns RDI hold time after RXC T3 1/4 T RXC ns

DA7838.002 4 (9) /G40/G47/G40/G38/G55/G53/G44/G38/G36/G47/G3/G38/G43/G36/G53/G36/G38/G55/G40/G53/G44/G54/G55/G44/G38/G54 Timings between synchronous clocks and data are shown below. Note that absolute delays depend on the speed of the data transmission. If pin TSL = 1 (Automatic synchronous sampling timing) /G41/G56/G49/G38/G55/G44/G50/G49/G54 /G117/G3/G36/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G87/G82/G3/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G70/G82/G81/G89/G72/G85/G87/G72/G85 The synchronous start-stop character, TDI (transmitter data input), is read into the Tx buffer. When the character is available the data bits are transferred as TDO (transmitter data output) with the synchronous timing signal TXC (transmitter clock). The bit rate of TDI must be the same as the TDO rate within -2.5%...+1% (extended signalling rate) signal. The transmitter adds extra stop bits to the synchronous data stream, if TDI is slower than TDO. The over speed is handled by deleting one stop bit in every 8th character at maximum in the synchronous output data TDO. When extended signal rate (XESR = 0) is used 4th stop bit may be deleted. When the transmitter detects a break signal( at least M bits of start polarity, where M is length of character), it sends 2M + 3 bits of start - polarity to TDO. If the break is longer than 2M + 3 bits, then all bits are transferred to TDO. After a break signal, at least 2M bits of stop polarity must be transmitted before sending further data. /G117/G3/G54/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G87/G82/G3/G68/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G70/G82/G81/G89/G72/G85/G87/G72/G85 The synchronous RDI (receiver data input) is buffered to recognise the stop and start bits. If a missing stop bit is detected, it is added to the RDO (receiver data output). In this case the stop bits are shortened 12.5% (25% if XESR = 0) during each character. When the receiver gets at least 2M + 3 bits of start polarity, it does not add stop bits to RDO. This enables the break signal to go through the buffer. /G117 /c3 /G38/G82/G81/G89/G72/G85/G87/G76/G81/G74/G3/G90/G76/G87/G75/G3/G75/G76/G74/G75/G72/G85/G3/G86/G83/G72/G72/G71/G3/G87/G76/G80/G76/G81/G74 An alternative method to handle the over speed in asynchronous data is to boost synchronous timing TXC and RXC by 1-2%. In this mode XHST (higher speed timing) = 0. In this case there is no need to delete any stop bits in the transmitter buffer. The break signal goes through unchanged. On the receiver side the synchronous data, RDI, is transferred directly to the asynchronous output RDO with RXC. TRXC T2 T3 RXC RDI TXC TDO TTXC delayT1

DA7838.002 5 (9) /G41/G56/G49/G38/G55/G44/G50/G49/G54 /G117/G3/G55/G76/G80/G76/G81/G74/G3/G86/G72/G79/G72/G70/G87/G76/G82/G81 The MAS7838 requires clock signals in order to function properly. The synchronous data transfer always requires the TXC clock. The clock is used internally for: -shifting data out from the TX buffer (to pin TDO) -shifting data into the RX buffer (via pin RDI) -detection of the bit rate in order to adjust the internal baud rate generator (only if TSL = 1) The asynchronous data transfer (pins TDI, TDO) is accomplished by generating an internal timing signal for the asychronous circuits. This internal timing signal (16T) is 16 times the TXC bit rate in order to sample the asynchronous data stream (TDI) at the proper speed. /G36/G51/G51/G47/G44/G38/G36/G55/G44/G50/G49/G3/G44/G49/G41/G50/G53/G48/G36/G55/G44/G50/G49 /G117/G3/G54/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G80/G82/G71/G72/G80/G3/G90/G76/G87/G75/G3/G68/G86/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G76/G81/G87/G72/G85/G73/G68/G70/G72 The MAS7838 is intended for applications where an asynchronous and synchronous data source must be linked together. A typical case appears in a data modem where the terminal interface of the modem has been specified to be asynchronous but the modem data pump operates in a synchronous fashion. 16 x TXC TXC Timing Circuits MAS 7838 EXTERNALLY GENERATED 16T CLOCK MAS9138 TXD RXD TDI RDO INTERFACE RS232C MODEM CIRCUITS PHONE LINE TDO TXC RDI RXC

DA7838.002 6 (9) /G36/G51/G51/G47/G44/G38/G36/G55/G44/G50/G49/G3/G44/G49/G41/G50/G53/G48/G36/G55/G44/G50/G49 /G117 /G54/G92/G81/G70/G75/G85/G82/G81/G82/G88/G86/G3/G86/G72/G85/G76/G68/G79/G3/G76/G81/G87/G72/G85/G73/G68/G70/G72/G3/G90/G76/G87/G75/G3/G88/G51/G3/G76/G81/G87/G72/G85/G73/G68/G70/G72 Another application is a synchronous serial interface for uP which uses UART as a data source. The concept is illustrated below. /G117/G3/G39/G68/G87/G68/G3/G80/G88/G79/G87/G76/G83/G79/G72/G91/G72/G85 A third application is a data multiplexing/demultiplexing system. The system accepts data from several sources. These data lines are sampled and the samples are sent through a multiplexer to a demultiplexer. To accomplish this, either a very high sample rate is needed or first convert the data to synchronous mode, where synchronous multiplexing can be used and only one sample per data bit is needed. MAS7838 TDI RDO uP INTERFACE RS232C MODEM CIRCUITS PHONE LINE TDO TXC RDI RXC Sync Modem Data Pump MAS7838 MAS7838 2 2 N N TDI RDO MAS7838 MAS7838 TDI RDO TDO TDORDI RDI FORWARD BACKWARD MUX/ DEMUX MUX/ DEMUX TIMING CH 1 CH 2 CH N

DA7838.002 7 (9) /G36/G51/G51/G47/G44/G38/G36/G55/G44/G50/G49/G3/G44/G49/G41/G50/G53/G48/G36/G55/G44/G50/G49 TTL/V28 78189A TTL/V28 75189A RS232C TXD RXD Ext. Signal Rate Char. Length Char. Length ASY/SYN Select mode selection jumpers TSL XHST +5v -12v +12v *) Optional timing from the synchronous modem. In this case CR 1 can be eliminated. MAS7838 simplified application: V.28 interface for synchronous modem +5v

16 TDO TTL-Level

CR 1 9.8304MHz 22pF Modem Timing Circuit 16 x TXC*) TXC RXC MAS7838 Synchronous Modem 470pF 470pF TDI RDO +5v +5v 3 x 4.75k

DA7838.002 8 (9) /G51/G36/G38/G46/G36/G42/G40/G3/G50/G56/G55/G47/G44/G49/G40/G54 All dimensions are in accordance with JEDEC standard MS-001. All dimensions are in accordance with JEDEC standard MS-013.

1 PIN

18.93 21.33 6.10 7.11 7.62 BSC 5-7° 5.5 2.93 5.33 4.95 MAX 0.254 BSC 2.540.36 0.56 1.77 1.15 PLANE SEATING

0.63 TYPICAL

1.52

16 LEAD PDIP OUTLINE (300 MIL BODY)

1.12 0.10 2.36 0.30 2.64PLANE SEATING 5° TYP. 10.50 10.10 10.65 PIN 1 10.00 7.60 7.40 1.27 TYP. 0.36 0.48 0.94 5°TYP0.33 x 45° 0.86 TYP.

16 LEAD SO OUTLINE (300 MIL BODY)

0-0.13 RAD.5° TYP. 5° TYP. 5° TYP. 0.25 RAD. MIN.

DA7838.002 9 (9) /G50/G53/G39/G40/G53/G44/G49/G42/G3/G44/G49/G41/G50/G53/G48/G36/G55/G44/G50/G49 /G51/G85/G82/G71/G88/G70/G87/G3/G38/G82/G71/G72 /G51/G85/G82/G71/G88/G70/G87 /G51/G68/G70/G78/G68/G74/G72 /G38/G82/G80/G80/G72/G81/G87/G86 MAS7838N PDIP16 25 pcs/tube MAS7838S-T SO16 1000 pcs/reel MAS7838S SO16 47 pcs/tube MSB0091A Bake recommendation for surface mounted devices /G47/G50/G38/G36/G47/G3/G39/G44/G54/G55/G53/G44/G37/G56/G55/G50/G53 /G48/G44/G38/G53/G50/G3/G36/G49/G36/G47/G50/G42/G3/G54/G60/G54/G55/G40/G48/G54/G3/G50/G60/G3/G38/G50/G49/G55/G36/G38/G55/G54 Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 Espoo, FINLAND http:\\\\www.mas-oy.com Tel. (09) 80 521 Tel. Int. +358 9 80 521 Telefax +358 9 805 3213 E-m ail: info@ m as-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.