MAS6181B_14 MAS | Alldatasheet

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Technical content

1 (14) DA6181B.003

17 September, 2014

  • Dual Band Receiver IC
  • High Sensitivity
  • Very Low Power Consumption
  • Wide Supply Voltage Range
  • Power Down Control
  • Control for AGC On
  • High Selectivity by Crystal Filter
  • Fast Startup Feature

DESCRIPTION

The MAS6181 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiving. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data fr om the received signal. The control for AGC (automatic gai n control) can be used to switch AGC on or off if necessary. The MAS6181 supports receiving two different frequency signals by two selective crystal filters and an integrated switch to switch between two antenna frequencies. It has differential input for improved common mode disturbance rejection. FEATURES APPLICATIONS

  • Dual Band Receiver IC
  • Highly Sensitive AM Receiver
  • Wide Supply Voltage Range from 1.1 V to 3.6 V
  • Very Low Power Consumption
  • Power Down Control
  • Fast Startup
  • Only a Few External Components Necessary
  • Control for AGC On
  • Wide Frequency Range from 40 kHz to 100 kHz
  • High Selectivity by Quartz Crystal Filter
  • Differential Input
  • Multi Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HBG (Switzerland) and BPC (China) BLOCK DIAGRAM AGC Amplifier Power Supply/Biasing Demodulator Comparator RFIM RFI2 VDD VSS PDN1 AGC DEC OUT QI AON QO1 QO2 PDN2 RFIP VDD VDD

2 (14) DA6181B.003 1530 µµµµ m 1120 µµ µµ m MAS6181B1 VDD QO2 QO1 QI AGC PDN2 OUT VSS RFI2 RFIM RFIP PDN1 AON DEC 1st bond! RFIMB RFI2B Do not bond! DIE size = 1120 x 1530 µ m; rectangular PAD 80 µ m x 80 µ m Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pa d to be bonded. Pick-and-place and all component as sembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Name X-coordinate Y-coordinate N ote Power Supply Voltage VDD 126 µ m 1332 µ m Quartz Filter Output for Crystal 2 QO2 126 µ m 1132 µ m Quartz Filter Output for Crystal 1 QO1 126 µ m 962 µ m Quartz Filter Input for Crystals QI 126 µ m 788 µ m AGC Capacitor AGC 126 µ m 614 µ m Power Down/Frequency Selection Input 2 PDN2 126 µ m 440 µ m 1 Receiver Output OUT 126 µ m 263 µ m 2 Demodulator Capacitor DEC 994 µ m 266 µ m AGC On Control AON 994 µ m 450 µ m 3 Power Down/Frequency Selection Input 1 PDN1 994 µ m 618 µ m 1 Positive Receiver Input RFIP 994 µ m 807 µ m 4 Negative Receiver Input RFIM 994 µ m 985 µ m 4 Test pad RFIMB RFIMB 298 µ m 1025 µ m 5 Test pad RFI2B RFI2B 400 µ m 1025 µ m 5 Receiver Input 2 (for Antenna Capacitor 2) RFI2 994 µ m 1163 µ m Power Supply Ground VSS 994 µ m 1321 µ m Notes: 1) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is af ter power down controlled to power on 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - The output is a current source/sink with |I OUT | > 5 µ A - At power down the output is pulled to VSS (pull do wn switch) 3) AON = VSS means AGC off (hold current gain level ); AON = VDD means AGC on (normal operation) - Unused AON pad can be left unconnected due to inte rnal pull-up with current < 1 µ A. Pull up current is switched off at power down. 4) Receiver inputs RFIP and RFIM have both 1.4 M Ω biasing resistors towards VDD 5) RFIMB and RFI2B pads are left unconnected. They are only for wafer level testing purposes

3 (14) DA6181B.003 Parameter Symbol Conditions Min Max Unit Supply Voltage V DD -VSS -0.3 3.6 V Input Voltage V IN V SS -0.3 V DD +0.3 V Operating Temperature T OP -40 +85 oC Storage Temperature T ST -55 +150 oC Stresses beyond those listed may cause permanent da mage to the device. The device may not operate unde r these conditions, but it will not be destroyed.

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 1.5V, Temperature = 27°C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Operating Voltage V DD 1.10 1.5 3.6 V Current Consumption I DD VDD=1.5 V, Vin=0 µ Vrms VDD=1.5 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µ Vrms VDD=3.6 V, Vin=20 mVrms µ A Stand-By Current I DDoff 0.1 µ A Input Frequency Range f IN 40 100 kHz Minimum Input Voltage V IN min 0.4 1 µ Vrms Maximum Input Voltage V IN max 20 mVrms Receiver Input Resistance Receiver Input Capacitance R RFI CRFI f=40kHz...77.5 kHz 600 1.1 kΩ pF RFI2 Switch On Resistance RFI2 Switch Off Capacitance R ON2 COFF2 VDD=1.4 V 15 Ω pF Input Levels |l IN |<0.5 µ A VIL VIH VDD -0.35 0.35 V Output Current V OL <0.2 V DD ;V OH >0.8 V DD |I OUT | 5 µ A DCF77 Output Pulses T 100ms T 20 0ms 1 µ Vrms ≤ VIN ≤ 20 mVrms, see note below! 195 ms MSF Output Pulses T 100ms T 200ms T 300ms T 500ms 1 µ Vrms ≤ VIN ≤ 20 mVrms, see note below! 120 220 320 520 ms WWVB Output Pulses T 200ms T 500ms T 800ms 1 µ Vrms ≤ VIN ≤ 20 mVrms, see note below! 200 500 800 ms JJY60 Output Pulses T 200ms T 500ms T 800ms 1 µ Vrms ≤ VIN ≤ 20 mVrms, see note below! 210 505 800 ms JJY40 Output Pulses T 200ms T 500ms T 800ms 1 µ Vrms ≤ VIN ≤ 20 mVrms, see note below! 200 495 790 ms Startup Time T Start Fast Start-up, Vin=0.4 µ Vrms Fast Start-up, Vin=20 mVrms 1.3 3.5 s Output Delay Time T Delay 50 100 ms Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and GND respectively. Note: See Note 6: Time Signal Software’s Pulse Width Rec ognition Limits and Table 5 on page 9!

Table 1. Frequency selection and power down control frequency of the two selected frequencies. for the two tuning frequencies.

Figure 1. Application circuit of dual band receiver MAS6181 Figure 2. Example circuit of dual band receiver MAS6181 for JJY 60 kHz and 40 kHz frequencies

Figure 3. Application circuit of MAS6181 in tri band receiver configuration

The crystals as well as ferrite antenna frequencies are chosen according to the time signal system (Ta ble 2). lower than with load thus 77.503 kHz crystal resonates at 77.500 kHz when no loading capacitor is used. Table 2. Time Signal System Frequencies ideal filter characteristics and wide noise band-width. Effectively this means lower sensitivity performance. Table 3 below presents some crystal suppliers having suitable crystals for time signal receiver application. Table 3. Crystal Suppliers and Crystal Types in Alphabetical Order for Time Signal Receiver Application through the capacitors. The insulation resistance o f these capacitors should be at minimum several 100 M Ω . low leakage. The DEC capacitor can be low leakage chip capacitor since its capacitance value is small.

been high before moving from power down to power up to guarantee proper operation of fast startup circ uitry. AON control pin has internal pull up which turns AG C circuit on all the time if AON pin is left unconn ected. time released since due to leakage the AGC can still change slowly when in hold. determining receiver performance. Recommended antenna impedance at resonance is around 100 kΩ . signal-to-noise ratio is at maximum is achieved in between. extensive tuning accuracy requirements and possible tuning drifts by the temperature. is defined by ratio of resonance frequency f res and antenna bandwidth B (equation 2). Table 4 below presents some antenna suppliers for time signal application. Table 4. Antenna Suppliers and Antenna Types in for Time Signal Application

The typical output pulse width specifications are p resented in the electrical characteristics section on page 3. width tolerance limits for recognizing pulses of different time signals. Table 5. Recommended Software Pulse Width Recognition Limits for Different Time Signals

10 (14) DA6181B.003 PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE QO2 VDD QO1 QI AGC PDN2 OUT RFIM VSS RFI2 RFIP PDN1 AON DEC 6181Bz YYWW Top Marking Definitions: z = Version Number YYWW = Year Week PIN DESCRIPTION Pin Name Pin Type Function Note VDD 1 P Positive Power Supply QO2 2 AO Quartz Filter Output for Crystal 2 QO1 3 AO Quartz Filter Output for Crystal 1

4 NC 1

QI 5 AI Quartz Filter Input for Crystal and Externa l Compensation Capacitor AGC 6 AO AGC Capacitor PDN2 7 DI Power Down/Frequency Selection Input 2 2 OUT 8 DO Receiver Output 3 DEC 9 AO Demodulator Capacitor AON 10 DI AGC On Control 4 PDN1 11 DI Power Down/Frequency Selection Input 1 2

12 NC 1

RFIP 13 AI Positive Receiver Input 5 RFIM 14 AI Negative Receiver Input 5 RFI2 15 AI Receiver Input 2 (for Antenna Capacitor 2) VSS 16 G Power Supply Ground A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pin 4 between QOM and QI must be connected to IC ’s filtered VDD (pin 1) to eliminate TSSOP package lead frame parasitic capacitances disturbing the crystal filter performance and minimizing noise coupling. All other NC (Not Connected) type pins are recommended to be connected to VSS. 2) PDN1 = VDD and PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is af ter power down controlled to power on 3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - The output is a current source/sink with |I OUT | > 5 µ A - At power down the output is pulled to VSS (pull do wn switch) 4) AON = VSS means AGC off (hold current gain level ); AON = VDD means AGC on (normal operation) - Unused AON pad can be left unconnected due to inte rnal pull-up with current < 1 µ A. Pull up current is switched off at power down. 5) Receiver inputs RFIP and RFIM have both 1.4 M Ω biasing resistors towards VDD

11 (14) DA6181B.003 PACKAGE (TSSOP-16) OUTLINES Dimension Min Max Unit A 6.40 BSC mm B 4.30 4.50 mm C 5.00 BSC mm D 0.05 0.15 mm E 1.10 mm F 0.19 0.30 mm G 0.65 BSC mm H 0.18 0.28 mm I 0.09 0.20 mm I1 0.09 0.16 mm J 0.19 0.30 mm J1 0.19 0.25 mm K 0° 8 ° L 0.24 0.26 mm M (The length of a terminal for soldering to a substrate) 0.50 0.75 mm N 1.00 REF mm O 12 ° P 12 ° Dimensions do not include mold flash, protrusions, or gate burrs. All dimensions are in accordance with JEDEC standard MO-153. B A C Pin 1 D Seating Plane E HGF B BDetail A L K M N P O Detail A I I1 J J1 Section B-B

12 (14) DA6181B.003 N For Pb-Free, RoHS Compliant TSSOP-16 Resistance to Soldering Heat According to RSH test IEC 68-2-58/20 Maximum Temperature 260 °C Maximum Number of Reflow Cycles 3 Reflow profile Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org Seating Plane Co-planarity max 0.08 mm Lead Finish Solder plate 7.62 - 25.4 µm, material Matte Tin EMBOSSED TAPE SPECIFICATIONS Dimension Min Max Unit A0 6.50 6.70 mm B0 5.20 5.40 mm D0 1.50 +0.10 / -0.00 mm D1 1.50 mm E1 1.65 1.85 mm F1 7.20 7.30 mm K0 1.20 1.40 mm P 11.90 12.10 mm P0 4.0 mm P2 1.95 2.05 mm S1 0.6 mm T 0.25 0.35 mm W 11.70 12.30 mm P A A Section A - A W Tape Feed Direction T Tape Feed Direction Pin 1 Designator

13 (14) DA6181B.003 B 1.5 mm C 12.80 13.50 mm D 20.2 mm N 50 mm (measured at hub) 12.4 14.4 mm (measured at hub) 18.4 mm Trailer 160 mm Leader 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm Weight 1500 g DA B C N Tape Slot for Tape Start Components Trailer Leader Carrier Tape Cover Tape Start End

2000 Components on Each Reel

Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative

14 (14) DA6181B.003

ORDERING INFORMATION

Product Code Product Description MAS6181B1TC00 Dual Band AM-Receiver IC with Differential Input EWS-tested wafer, diameter 8”, thickness 395 µm ± 5%. MAS6181B1UC06 Dual Band AM-Receiver IC with Differential Input TSSOP-16, Pb-free, RoHS compliant, Tape & Reel Contact Micro Analog Systems Oy for other wafer thickness options. N The formation of product code An example for MAS6181B1TC00: MAS6181 B 1 TC 00 Product name Design version Capacitance option: C C = 0.75 pF Package type: TC = 400 µ m thick EWS tested wafer Delivery format: 00 = undiced wafer 05 = dies on tray 06 = tape & reel 08 = in tube LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kutomotie 16 FI-00380 Helsinki, FINLAND Tel. Int. +358 10 835 1100 Telefax +358 10 835 1119 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data shee t in order to improve the design or performance and to supply the best possible product s. Micro Analog Systems Oy assumes no responsibilit y for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specifi ed in this data sheet, and makes no claim that the circuits are free from patent infrin gement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.