MAD4868A

MAD4868A MICRONAS | Alldatasheet

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• 2 May 11, 2004; 6251-636-1PD Micronas

Edition May 11, 2004 6251-636-1PD PRELIMINARY DATA SHEET MICRONAS MICRONAS

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 3 Micronas Audio Delay 1. Introduction The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and consumer audio applica- tions. The IC is designed for synchronizing audio and video signals ensuring “Lip Sync” by delaying the audio signal with the same amount of time as the video signal is delayed in a TV’s video processing. For TV designs, independent signals for loudspeakers, headphones, and line-out or S/PDIF out must be pro- vided, resulting in the need to delay six independent audio channels. Especially modern flat panel TVs (LCD- or plasma- TVs) require “Lip Sync” because of their video deinter- lacing, processing, scaling, and pixel-oriented display. In battery-operated “wireless TVs” using digital trans- mission, the compression/ decompression also may delay video more than audio. Therefore, additional audio delay is necessary. Consumer audio applications such as A/V-Receivers or HTiB can also use MAD 4868A to offer “Lip Sync” as an additional feature to delay audio according to the video delay appearing in the TV, beamer, or monitor used in a home cinema setup. The MAD 4868A is equipped with all interfaces, as well as embedded RAM. This makes the IC easy to use and avoids RAM availability and pricing problems. In its PMQFP44-1 package with 0.8 mm pitch, the MAD 4868A requires only little PCB space but is suit- able for wave soldering and reflow soldering. 1.1. Features – 32 k audio samples RAM: Total delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate – 32/18-bit word width: 32-bit High-Resolution mode or 18-bit Standard mode – Sampling rates from 32 kHz to 48 kHz for serial 8-channel mode are supported – Sampling rates from 4 kHz to 192 kHz for parallel 2-channel mode are supported – Memory allocation: MAD 4868A’s memory can be allocated for 1…8 audio channels. Delay time can be programmed for each channel individually. 1.2. Interfaces – 8-channel Micronas I 2S input and output: In combination with Micronas ICs (serial mode) (e.g. MSP 44/46xyK, MAS 35xyH), eight audio channels can be routed through MAD 4868A by using four lines only. –4 ×2-channel standard I2S inputs and outputs (paral- lel mode) allow routing eight audio channels with sampling rates of 4…192 kHz through MAD 4868A 2C control for delay time programming – Address select to set one out of two available I 2C addresses 1.3. Miscellaneous – No crystal required: The MAD 4868A derives all internal clocks from the I2S clock. – Very few external components required – 5 V or 3.3 V single supply voltage – Very low power consumption – 5 kHz to 192 kHz sampling rates – Cascadable, extendable: Two MAD 4868As can be cascaded to extend the delay time, either in 8-channel (serial) mode using one data line or in 2-channel (parallel) mode using up to four data lines.

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Fig. 1–1: Block diagram of the MAD 4868A INPUTIN BUFFER OUTPUT BUFFER OUT CONTROLI2C RAM t1 t5t3 t4t2 t6 t7 t8 MAD 4868A

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 5 2. Functional Description 2.1. Block Diagram In Fig. 2–1, a simplified block diagram of the IC is given. Between 1 and 8 channels can be delayed indi- vidually by a programmable number of samples n The delay RAM offers, depending on the accumulated adjusted delay, a word width of 32 or 18 bits. The accumulated delay must not exceed 7FF0 hex (32752dec) samples (i.e. 682 ms @ 48 kHz F s). As the bit clock (I2S_DEL_CL) is limited to 12.288 MHz and the used I2S bus format has a fixed word length of 32 bit, the maximum sample rate f s is 192 kHz in parallel mode (2-channels per data line) and 48 kHz in serial mode (8-channels on I2S_DEL_IN1/OUT1). 2.2. I2S Bus Interface The MAD 4868A has four I2S data input lines and four I2S data output lines which together with I2S_DEL_WS and I2S_DEL_CL form one I 2S bus interface for vari- ous sample rates in serial (8-channel) or parallel (2- channel) mode. The I2S_DEL_CL, I2S_DEL_WS, and I2S_DEL_IN1...4 are inputs to the MAD 4868A (tristate) while I2S_DEL_OUT1...4 are outputs. Bit[1:0] of the CONTROL register set the output driver active or tristate and its strength to weak or strong (see Table 3–3 on page 10). The interface works only in synchronous slave mode and with a fixed wordlength of each audio sample of 32 bits. Two different opera- tional modes can be adjusted as described in the fol- lowing sections. Fig. 2–1: Simplified block diagram of the MAD 4868A Output Buffers Multiplexer / Mute DO 2..8 Input Buffers Demultiplexer [t1] [t2] [t3] [t6] [t8] [t7] [t5] [t4] not used 0ms 680ms@48kHz DI 2..8 CONTROL[9:2] CONTROL[1:0] Output Data Mute Output Driver Active Output Driver Strength Frame Clock (WS)

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2.2.1. Serial Mode - One Data Line The MAD 4868A is capable of receiving signals with up to eight audio samples in a fixed 8-channel I 2S for- mat on one data line (serial mode). The interface con- sists of the pins: – I2S_DEL_IN1: I 2S data input, with 8 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample – I2S_DEL_OUT1: I2S data output, with 8 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample – I2S_DEL_CL: I2S clock – I2S_DEL_WS: I2S word strobe signal defines the frame start at the sample rate. As the bit clock must not exceed 12.288 MHz, the maximum sample rate is limited to 48 kHz when the MAD 4868A is operated in this mode. This mode is used for the connection to the Delay Line Interface of the MSP 44/46xyK. In serial mode, the number of audio channels must be even and less or equal eight. A timing diagram is shown in Fig. 4–8 on page 21. In this mode, it is possible to mute each output channel individually by means of the CONTROL register bit[2:9.] Note: DVSUP2 drives the pins DA_IN_2...4 and DA_OUT_2...4. To avoid radiation from not con- nected pins, it is recommended not to connect DVSUP2 when MAD 4868A is to be used in Serial Mode. 2.2.2. Parallel Mode - Four Data Lines The MAD 4868A is capable of receiving stereo signals on up to four I2S data lines in Parallel Mode with a total of up to eight audio channels. The interface consists of the pins: – I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4: I 2S data input with 2 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample – I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4: I 2S data output with 2 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample – I2S_DEL_CL: I2S clock – I2S_DEL_WS: I2S word strobe signal defines the left and right sample at the sample rate. As the bit clock must not exceed 12.288 MHz, the sample rate can be a maximum of 192 kHz when MAD 4868A is operated in this mode. This mode is used for connection to e.g. the I 2S interface of the Mic- ronas MSP 34/44xyG or any other audio DSP .

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 7 2.3. Delay Line The MAD 4868A has a delay line of 32k Words of RAM built in. The RAM can be split up into portions of differ- ent length to delay between 1 and 8 channels of audio. This makes the MAD 4868A very flexible. All channels can be delayed individually. The maximum amount of adjusted delay must not exceed 7FF0 hex (32752 dec) samples. Equipped with a pointer unit and programmed with variable pointer offsets for the delay channels 1 to 8, the programming of the individual delay times is real- ized by means of its own control register for each delay channel (see Table 3–3 on page 10). The delay time depends on the used sample fre- quency on the I 2S-bus. Since, not the delay time, but the number of delayed samples is programmed, the corresponding number of samples is calculated using the follwing formula: In the pointer unit, the offsets are used as increments for the address pointer to receive the correct RAM address of the delayed sound samples. Note: Reprogramming the delay length of a channel affects the output of the channels with higher numbers. Due to the “linked list” principle of the RAM organisation, the upper channels read from “wrong memory” until it is filled up with new audio samples. Therefore, it is recommended to mute the output of the delay line for the max programmed delay time of all channels. 2.4. Word Width The audio sample word width inside the RAM of the MAD 4868A depends on the adjusted number of sam- ples for the delay. MAD 4868A automatically switches the word width to 32 bit if the total delay length is below 3FF8hex (16376 dec) i.e. half of the maximum length. Otherwise, the delay line is 18 bit wide. By means of bit[14] of the CONTROL register, a read out value is available in parallel mode which indicates the internally adjusted word width. 2.5. Output Data Mute The output data channel 1-8 can be muted by means of the CONTROL register bit[2:9]. In serial mode, each output data channel can be muted individually, while in parallel mode, all channels 1-8 have to be adjusted individually to the same value. It is recommended to mute the output data channels during the power-up sequence of the MAD 4868A, as well as during re- adjustment of the delay time during normal operation. To avoid any audible disturbances, the minimum mute time must be at least the maximum programmed delay time of all channels. 2.6. Reset The Reset is active low and resets the I 2S and I 2C- interfaces of the MAD 4868A. Since there is no RAM clear facility, the output of the MAD 4868A after reset is random, as long as no valid samples have been inserted and passed the delay line (e.g. after Reset, enable the I 2S bus output but keep Mute active until the maximum programmed delay time is passed). 2.7. RAM Clear A RAM Clear can be performed manually. It is recom- mended to apply a manual RAM Clear after the power- up of the MAD 4868A. Mute the output data channel 1- 8, apply a digital zero signal on all used channels. This can be achieved, for example, by selecting an I input with a prescaler setting to Mute in the MSP 44/ 46xyK for all used MAD 4868A input channels. The digital zero signal must be applied for at least the max- imum programmed delay time of all channels. nx = number of samples tms = time in milliseconds fs = sample rate nx tms x() fs×() 1 –=

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1. Control Interface 3.1. I2C Bus Interface The MAD 4868A is controlled via its I 2C bus slave interface. The IC is selected by transmitting an MAD 4868A device address. In order to allow two MAD 4868A ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high or low, the MAD 4868A responds to dif- ferent device addresses. A device address pair is defined as a write address and a read address. Writing is done by sending the write device address, followed by the subaddress byte and the data bytes. Reading is done by sending the write device address, followed by the subaddress byte. Without sending a stop condition, reading of the addressed data is com- pleted by sending the device read address and read- ing two bytes of data. See Table 3–1 for a list of available device addresses. See Table 3–2 for a list of available subaddresses. A general timing diagram of the I 2C bus is shown in Fig. 3–1 on page 9. Table 3–1: I2C Bus Device Addresses ADR_SEL Low (connected to DVSS) High (connected to DVSUP) Mode Write Read Write Read MAD 4868A device address 82 hex 83hex 84hex 85hex Table 3–2: I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Read / Write Write: Interface control Read: Status CH1_DELAY 0000 0001 01 Read / Write delay channel 1 CH2_DELAY 0000 0010 02 Read / Write delay channel 2 CH3_DELAY 0000 0011 03 Read / Write delay channel 3 CH4_DELAY 0000 0100 04 Read / Write delay channel 4 CH5_DELAY 0000 0101 05 Read / Write delay channel 5 CH6_DELAY 0000 0110 06 Read / Write delay channel 6 CH7_DELAY 0000 0111 07 Read / Write delay channel 7 CH8_DELAY 0000 1000 08 Read / Write delay channel 8

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 9 3.1.1. Protocol Description Write to CONTROL and CHX_DELAY Registers Read from CONTROL or CHX_DELAY Register Note: S = I 2C-Bus Start Condition from master P = I 2C-Bus Stop Condition from master ACK = Acknowledge-Bit: LOW on SDA from slave (= MAD, light gray) or master (= controller, dark gray) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MAD indicating internal error state Wait = I2C-Clock line is held low, while the MAD is processing the I2C command. This waiting time is max. 1 ms Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high) 3.1.2. Start-Up Sequence: Power-Up and I2C-Con- trolling After POWER-ON or RESET, the IC is in an inactive state. All registers are in their Reset position (see Table 3–3 on page 10), the Output Driver is set to tristate. The controller has to initialize the CONTROL and CHX_DELAY registers. 3.2. Description of User Interface Write and read registers are 16 bit wide, whereby the MSB is denoted bit[15]. Transmissions via I 2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All registers are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be accessed. S write device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P S write device address Wait ACK sub-addr ACK S read device address Wait ACK data-byte- high ACK data-byte low NAK P S P SDA SCL

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Table 3–3: User Interface Sub - Address (hex) Function Mode Reset Value (hex) Name 00hex Control bit[15] must be ignored bit[14]1) HighRes Flag (word width of delayed samples) 0 18 bit 1 32 bit (high resolution) bit[13:11] not used, must be set to 0 bit[10] WS_POL (word strobe polarity)

0 WS_POL = Low-High marks Framestart

e.g. MSP 44/46xyK I2S-5 Interface, all MSPs 8-channel mode

1 WS_POL = High-Low marks Framestart

e.g. MSP I2S_OUT (2-channel mode) bit[9] Output Data Mute channel 8 bit[8] Output Data Mute channel 7 bit[7] Output Data Mute channel 6 bit[6] Output Data Mute channel 5 bit[5] Output Data Mute channel 4 bit[4] Output Data Mute channel 3 bit[3] Output Data Mute channel 2 bit[2] Output Data Mute channel 1 0 muted 10 d B Output Data Mute channel 1-8 can be set individually in serial mode, in parallel mode, Output Data Mute channel 1-8 must all be set to the same value. bit[1] Output Driver Active 0 tristate 1a c t i v e bit[0] Output Driver Strength 0w e a k 1s t r o n g 1) bit[14] is read only 0000hex CONTROL

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 11 01hex... 08hex Channel Delay The delay time tms in milliseconds; Delay nx must be calculated and set as number of samples: n bit[15:0] n x number of delayed samples for channel x, x = 1...8 example: f s =f s =f s = f s = samples: n x 32 kHz 48 kHz 96 kHz 192 kHz min delay 0 31 µs 21 µs 10 µs 5 µs 1Fhex 1.00 ms 0.66 ms 0.33 ms 0.16 ms 2Fhex 1.50 ms 1.00 ms 0.50 ms 0.25 ms 5Fhex 3.00 ms 2.00 ms 1.00 ms 0.50 ms ... max delay1) 7FF0hex 1023 ms 682 ms 341 ms 170 ms 1) Since there are 32 KWords of RAM accessible, the SUM(n1:n8) must be less than 7FF0hex (e.g. in total a maximum delay of 682 ms at a 48 kHz sample rate must not be exceeded). 0000hex CH1_DELAY CH2_DELAY CH3_DELAY CH4_DELAY CH5_DELAY CH6_DELAY CH7_DELAY CH8_DELAY Table 3–3: User Interface, continued Sub - Address (hex) Function Mode Reset Value (hex) Name

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1. Specifications 4.1. Outline Dimensions Fig. 4–1: PMQFP44-1: Plastic Metric Quad Flat Package, 44 leads, 10 × 10 × 2 mm3 Ordering code: QG Weight approximately 0.5 g

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 13 4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram 4.3. Pin Descriptions I2C_CL – I2C Clock Input/Output (Fig. 4–3) Via this pin, the I 2C-bus clock signal has to be sup- plied. I2C_DA – I2C Data Input/Output (Fig. 4–3) Via this pin, the I2C-bus data is written to or read. I2S_DEL_WS – Word Strobe Input (Fig. 4–4) Word strobe line for the I 2S bus. An external word strobe has to be supplied. I2S_DEL_CL – Clock Input (Fig. 4–4) Clock line for the I 2S bus. An external clock has to be supplied. Pin No. Pin Name Type Connection Short Description PMQFP44-1 (If not used) 1...12 NC LV Not Connected

13 I2S_DEL_OUT2 OUT OBL I2S data output channel 3 + 4

14 I2S_DEL_OUT3 OUT OBL I 2S data output channel 5 + 6

15 I2S_DEL_OUT4 OUT OBL I 2S data output channel 7 + 8

16 DVSUP2 SUP DVSUP Digital Power Supply

17 DVSS2 SUP DVSS Digital Ground

18 I2S_DEL_IN2 IN OBL I

2S data input channel 3 + 4

19 I2S_DEL_IN3 IN OBL I 2S data input channel 5 + 6

20 I2S_DEL_IN4 IN OBL I 2S data input channel 7 + 8

21...33 NC LV Not Connected

34 RESETQ IN OBL Power-On Reset (active low)

35 TEST IN DVSS Test pin

36 DVSS1 SUP DVSS Digital Ground

37 DVSUP1 SUP DVSUP Digital Power Supply

38 I2S_DEL_WS IN OBL I

39 I2S_DEL_CL IN OBL I 2S clock input

40 I2S_DEL_IN1 IN OBL I 2S data input channel 1 + 2 or 1..8 41 I2S_DEL_OUT1 OUT OBL I 2S data output channel 1 + 2 or 1..8

42 ADR_SEL IN OBL I 2C bus address select

43 I2C_DA IN/OUT OBL I 2C Data

44 I2C_CL IN/OUT OBL I 2C Clock

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I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4 – Data Input (Fig. 4–4) Input of I2S data. I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 – Data Output (Fig. 4–5) Output of I2S bus. DVSUP1, DVSUP2 – Digital Supply Voltage Power supply must be connected to +5V o r + 3 . 3V power supply. DVSS1, DVSS2 – Digital Ground Ground connection. TEST – This pin enables factory test modes. For nor- mal operation, it must be connected to DVSS RESETQ – Reset Input (Fig. 4–4) In the steady state, high level is required. A low level resets the interfaces of MAD 4868A. ADR_SEL – I 2C Bus Address Select (Fig. 4–4) By means of this pin, one of two device addresses can be selected. The pin can be connected to DVSS (I 2C device addresses 82/83hex) or to DVSUP (84/85hex). NC – Pin not connected 4.4. Pin Configuration Fig. 4–2: PMQFP44-1 package 4.5. Pin Circuits Fig. 4–3: Input/Output Pins: I2C_CL, I2C_DA Fig. 4–4: Input Pins:I2S_DEL_CL, I2S_DEL_WS, I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4, ADR_SEL, RESETQ Fig. 4–5: Output Pins: I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 RESETQ TEST DVSS1 DVSUP1 I2S_DEL_WS I2S_DEL_CL I2S_DEL_IN1 I2S_DEL_OUT1 ADR_SEL I2C_DA I2C_CL NC NC I2S_DEL_IN4 I2S_DEL_IN3 I2S_DEL_IN2 DVSS2 DVSUP2 I2S_DEL_OUT4 I2S_DEL_OUT3 I2S_DEL_OUT2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC MAD 4868A 123456789 1 0 1 1 33 32 31 30 29 28 27 26 25 24 23 N GND DVSUP P N GND DVSUP P N GND

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 15 4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip 4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso- lute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (V SS = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Table 4–1: Absolute Maximum Ratings Symbol Parameter Pin Name Limit Values Unit Min. Max. TA 1) Ambient Temperature −− 10 70 °C TC Case Temperature −− 10 95 °C TS Storage Temperature −− 40 125 °C PMAX Maximum Power Dissipation 860 mW VSUP Supply Voltage DVSUP1, DVSUP2 −0.3 6.0 V VIdig Input Voltage, all Digital Inputs −0.3 V SUP2+0.3 V IIdig Input Current, all Digital Pins −− 20 +20 mA 1) Measured on standard board according to JESD 51 Standard with maximum power consumption allowed for this package.

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4.6.2. Recommended Operating Conditions Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteris- tics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSS = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power 4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Limit Values Unit Min. Typ. Max. TA Ambient Operating Temperature − 07 0 °C TC Case Operating Temperature − 07 0 °C PMAX Maximum Power Dissipation 50 mW VSUP Supply Voltage DVSUP1, DVSUP2 3.0 5.25 V

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 17 4.6.3. Characteristics For Min./Max. values: at T A = 0 to 70 °C VSUP = 3.15 to 3.45 V if VSUP = 3.3 V VSUP = 4.75 to 5.25 V if VSUP = 5 V For typical values: at T A = 60 °C VSUP = 3.3 V or VSUP = 5 V 4.6.3.1. General Characteristics 4.6.3.2. Digital Inputs, Digital Outputs 4.6.3.3. Reset Input and Power-Up Symbol Parameter Pin Name Limit Values Unit Test Conditions Min. Typ. Max. Supply ISUP Supply Current (active) (VSUP = 5 V) DVSUP1, DVSUP2 2.4 2.9 0.8 mA mA mA Serial mode f s = 48 kHz Parallel mode fs 192 kHz Parallel mode fs 48 kHz Supply Current (active) (VSUP = 3.3 V) 1.15 1.5 0.5 mA mA mA Serial mode f s = 48 kHz Parallel mode fs 192 kHz Parallel mode fs 48 kHz Symbol Parameter Pin Name Limit Values Unit Test Conditions Min. Typ. Max. Digital Input Levels VDIGIL Digital Input Low Voltage ADR_SEL 0.2 V SUP VDIGIH Digital Input High Voltage 0.5 VSUP ZDIGI Input Capacitance 5 pF Symbol Parameter Pin Name Limit Values Unit Test Conditions Min. Typ. Max. RESETQ Input Levels VRHL Reset High-Low Transition Voltage RESETQ 0.2 V SUP VRLH Reset Low-High Transition Voltage 0.5 VSUP ZRES Input Capacitance 5 pF

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4.6.3.4. I2C-Bus Characteristics Fig. 4–6: I2C bus timing diagram Symbol Parameter Pin Name Limit Values Unit Test Conditions Min. Typ. Max. VI2CIL I2C-Bus Input Low Voltage SCL, SDA

0.3 V SUP

VI2CIH I2C-Bus Input High Voltage 0.6 VSUP tI2C1 I2C Start Condition Setup Time 120 ns tI2C2 I2C Stop Condition Setup Time 120 ns tI2C5 I2C-Data Setup Time before Rising Edge of Clock 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns tI2C3 I2C-Clock Low Pulse Time SCL 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns fI2C I2C-BUS Frequency 1.0 MHz VI2COL I2C-Data Output Low Voltage SCL, SDA

0.4 V I I2COL = 3 mA

1.0 µAV I2COH = 5 V tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns f I2C = 1 MHz SCL SDA as input SDA as output TI2C1 TI2C5 TI2C6 TI2C2 TI2C4 TI2C3 1/FI2C TI2COL2 TI2COL1

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 19 4.6.3.5. I2S-Bus Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VIL Input Low Voltage I2S_DEL_CL I2S_DEL_WS I2S_DEL_IN1 I2S_DEL_IN2 I2S_DEL_IN3 I2S_DEL_IN4 0.2 V SUP VIH Input High Voltage 0.5 VSUP ZI Input Impedance 5 pF ILEAK Input Leakage Current −11 µA0 V < U INPUT< DVSUP VOL Output Low Voltage I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4

0.4 V I

OL = 1 mA VOH Output High Voltage VSUP − 0.3 VI OH = −1 mA I2S Interface Parallel Mode 2-channel ts_I2SDEL Input Setup Time before Rising Edge of Clock I2S_DEL_CL I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4 7 ns for details see Fig. 4–8 “I bus timing diagram, serial mode (8-channel)” t h_I2SDEL Input Hold Time after Rising Edge of Clock 10 ns t d_I2SDEL Output Delay Time after Falling Edge of Clock I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 15 ns C L=30 pF fI2SDEL_WS Word Strobe Input Frequency WS 4 192 kHz deviation = ±300 ppm fI2SDEL_CL Clock Input Frequency CL 0.256 12.288 MHz deviation = ±300 ppm RCL Clock Input Ratio 0.9 1.1 I2S Interface Serial Mode 8-channel ts_I2SDEL Input Setup Time before Rising Edge of Clock I2S_DEL_CL I2S_DEL_WS I2S_DEL_IN1 7 ns for details see Fig. 4–8 “I bus timing diagram, serial mode (8-channel)” t h_I2SDEL Input Hold Time after Rising Edge of Clock 10 ns t d_I2SDEL Output Delay Time after Falling Edge of Clock I2S_DEL_OUT1, 15 ns C L=30 pF fI2SDEL_WS Word Strobe Input Frequency I2S_DEL_WS 4 48 kHz fI2SDEL_CL Clock Input Frequency I2S_DEL_CL 1.024 12.288 MHz RCL Clock Input Ratio 0.9 1.1

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Fig. 4–7: I2S bus timing diagram, parallel mode (2-channel) I2S_DEL_WS(if Control[10] = 0) I2S_DEL_CL I2S_DEL_INx I2S_DEL_OUTx I2S_DEL_WS Detail A,B,C I2S_DEL_CL I2S_DEL_OUTx td_I2SDEL th_I2SDELts_I2SDEL I2S_DEL_INx channel xright with 32 bits Detail C Detail A Detail B LSBr MSBl channel xright with 32 bitschannel xleft with 32 bits channel xleft with 32 bits td_I2SDEL 1/FI2SDEL_WS LSBl MSBr LSBr MSBl LSBr MSBl LSBl MSBr LSBr MSBl I2S_DEL_WS(if Control[10] = 1)

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 21 Fig. 4–8: I2S bus timing diagram, serial mode (8-channel) I2S_DEL_WS(if Control[10] = 0) I2S_DEL_CL I2S_DEL_IN1 I2S_DEL_OUT1 I2S_DEL_WS Detail A I2S_DEL_CL I2S_DEL_OUT1 td_I2SDEL th_I2SDELts_I2SDEL I2S_DEL_IN1 4 channels with 32 bits Detail A LSB8 MSB1 4 channels with 32 bits4 channels with 32 bits 4 channels with 32 bits td_I2SDEL 1/FI2SDEL_WS LSB 1 MSB2 LSB4 MSB4 LSB8 MSB1 LSB8 MSB1 LSB1 MSB2 LSB4 MSB5 LSB8 MSB1 I2S_DEL_WS(if Control[10] = 1) Frame Start will be identified if I2S_DEL_WS is high for at least two clock cycles Frame Start will be identified if I2S_DEL_WS is low for at least two clock cycles

MAD 4868A PRELIMINARY DATA SHEET

22 May 11, 2004; 6251-636-1PD Micronas

1. Appendix A: Application Diagram (Exemplary) 220p470p1n5 10u/16V 2u2 GND 100n GND + 10u/16V+ 10u/16V GND GND 100n 470p 1n5 10u/16V 100u +8V + 3u3/16V 100n 10u/16V GND GND GND GND 470p 1n5 10u/16V 2u2 GND +5V 18.432MHz 3p3 3p3 GND GND GND SC2outR SC2outL SC1outL SC1outR SC1inR SC1inL SC2inR SC2inL SC3inR SC3inL SC4inR SC4inL 56p 56p 56p 470n 470n470n 470n470n470n 470n470n 470nGND GND GND +5V GND NC1 I2C_CL2 I2C_DA3 I2S_CL4 I2S_WS5 I2S_DA_OUT6 I2S_DA_IN17 I2S_DEL_IN8 I2S_DEL_OUT9 I2S_DEL_CL10 I2S_DEL_WS11 DVSUP12 DVSUP13 DVSS14 DVSS15 DVSS16 I2S_DA_IN217 NC18 I2S_CL319 I2S_WS320 RESETQ21 I2S_DA_IN322 I2S_DA_IN423 DACA_R24 DACA_L25 VREF226 DACM_R27 DACM_L28 DACM_C29 DACM_SUB30 DACM_SR31 DACM_SL32 SC2_OUT_R33 SC2_OUT_L34 VREF135 SC1_OUT_R36 SC1_OUT_L37 CAPL_A38 AHVSUP39 CAPL-M40 SC3_OUT_R 41SC3_OUT_L 42AHVSS 43AHVSS 44AGNDC 45NC 46SC4_IN_L 47SC4_IN_R 48ASG 49SC3_IN_L 50SC3_IN_R 51ASG 52SC2_IN_L 53SC2_IN_R 54ASG 55SC1_IN_L 56SC1_IN_R 57VREFTOP 58SC5_IN_L 59SC5_IN_R 60AVSS 61AVSS 62NC 63NC 64 AVSUP65 AVSUP66 ANA_IN1+67 ANA_IN-68 ANA_IN2+69 TESTEN70 XTAL_IN71 XTAL_OUT72 TP73 AUD_CL_OUT74 NC75 SPDIF_OUT76 D_CTR_I/O_177 D_CTR_I/O_078 ADR_SEL79 STANDBYQ80 MSP 44xyK 470n SC5inL SC3outR SC3outL SC3outR SC3outL SC5inR GND from IF from IF from IF SC2outR SC2outL SC1outR SC1outL 100R100R 22u/16V 22u/16V GND 100R100R 22u/16V 22u/16V GND 100R100R 22u/16V 22u/16V GND SC1inL GND470R 470R 330p 330p SC1inR SC2inL GND470R 470R 330p 330p SC2inR SC3inL GND470R 470R 330p 330p SC3inR SC4inL GND470R 470R 330p 330p SC4inR SC5inL GND470R 470R 330p 330p SC5inR to AMP to AMP to AMP to AMP to AMP to AMP to AMP to AMP 1n 1n 1n 1n 1n 1n 1n 1n GNDGNDGNDGNDGNDGNDGNDGND 3k3 1k10R BC847 1k180R 100n +5V 100n 100nSPDIFout GNDGND GND RESETQ from ResetCircuit SCL from µC SDA from/to µC GND 10n 10µ GND +5V 100n GND 2µ2 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 I2S_DEL_OUT213 I2S_DEL_OUT314 I2S_DEL_OUT415 DVSUP16 DVSS17 I2S_DEL_IN218 I2S_DEL_IN319 I2S_DEL_IN420 NC21 NC22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 NC 29 NC 30 NC 31 TEST 35 NC 32 DVSS 36 NC 33 DVSUP 37 RESETQ 34 I2S_DEL_WS 38I2S_DEL_CL 39I2S_DEL_IN1 40I2S_DEL_OUT1 41ADR_SEL 42I2C_DA 43I2C_CL 44 MAD4868A

PRELIMINARY DATA SHEET MAD 4868A Micronas May 11, 2004; 6251-636-1PD 23

All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. MAD 4868A PRELIMINARY DATA SHEET

24 May 11, 2004; 6251-636-1PD Micronas

D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-636-1PD 6. Data Sheet History 1. Preliminary Data Sheet: “MAD 4868A Micronas Audio Delay”, May 11, 2004, 6251-636-1PD. First release of the preliminary data sheet.