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M8061A 32 Gb/s Multiplexer with De-Emphasis Data Sheet Version 1.5
02 | Keysight | M8061A 32 Gb/s Multiplexer with De-Emphasis - Data Sheet
Description
R&D and test engineers who need to characterize serial interfaces of up to 32 Gb/s can use the M8061A 2:1 Multiplexer with optional de-emphasis to extend the rate of J-BERT M8020A and J-BERT N4903B pattern generator. For the most accurate receiver characterization results, the M8061A provides four calibrated de-emphasis taps, which can be extended to eight taps, built-in superposition of level interference and Clock/2 jitter injection. The N4877A 32G CDR and de-multiplexer can be used to complement the setup for the analyzer side. The M8061A is a 2-slot AXIe module that can be controlled via USB from the user interfaces of J-BERT M8020A as well as J-BERT N4903B. Typical applications that require testing at data rates up to 32 Gb/s are: – Optical transceiver such as 100GBASE-LR4, -SR4 and -ER4, 32G Fibre Channel – SERDES and chip-to-chip interfaces, such as OIF CEI – Backplanes, cables, repeaters, such as 100GBASE-KR4 – Thunderbolt 20G and active optical cables Key features – Extension for J-BERT M8020A for data rates up to 32 Gb/s – Expands data rate of J-BERT N4903B pattern generator up to 28.4 Gb/s – Integrated and calibrated 4-tap de-emphasis, expandable to 8 taps – Internal superposition of interference for common-mode and differential mode – Transparent to jitter generated by J-BERT, Clock/2 jitter can be added – Electrical idle – Control from J-BERT M8020A and N4903B user interface via USB
03 | Keysight | M8061A 32 Gb/s Multiplexer with De-Emphasis - Data Sheet
32 Gb/s BERT setup with J-BERT M8020A and M8061A
To characterize receivers that operate up to 32 Gb/s, the M8061A multiplexer can be used with J-BERT M8020A and N4877A as a 32 Gb/s high-performance BERT. It provides excellent intrinsic jitter performance, integrated and calibrated jitter injection capabilities to stress receivers under test, 4/8-tap de-emphasis to emulate transmitter de-emphasis and to compensate for losses in the channel and a tunable CDR to enable full sampling BER and jitter tolerance measurements up to 32 Gb/s. A powerful pattern sequencer allows generating algorithmic PRBS as well as memory pattern sequences. Up to two 32 Gb/s channels can be configured for crosstalk testing and PAM-4 pattern generation. Figure 1: The 32 Gb/s high-performance BERT configuration is based on J-BERT M8020A, M8061A and N4877A. Its perfectly suited to characterize receiver tolerance up to 32 Gb/s. It provides integrated jitter injection up to 1 UI for HF jitter and hundreds of UIs for LF jitter, 8-tap de-emphasis and tunable CDR capability for BER analysis and jitter tolerance testing. All parameters can be controlled from a common user interface. Figure 2: The 32G J-BERT M8020A configuration can be controlled from the M8070A system software. It allows adjusting all parameters of M8061A, M8020A and N4877A from one common user interface. The system view on the left side shows the block diagram of the 32G BERT with its synthesizer, pattern generation, jitter sources, interference, de-emphasis, output amplifier, the analyzer and CDR. At the right side you can adjust all related parameters.
Table 1. Specifications for data out over-programming up to 32.4 Gb/s. M8051A, M9505A and a second M8061A. See table 2 for max. output amplitude if offset is > 1.9 V and CMI/DMI are turned on. For offset > 1.3 V the termination voltage should be ± 0.5 V of offset. clock source, its intrinsic clock jitter applies. clock source without band pass filter. amplitude values in UI refer to the output of M8061A (sum of HF jitter is 1UI max). 4 ns typical + 60 ns ± 10 ns (reaction time from EIDLE input to data outputs starting to go into EIDL state).
- Measured with Oscilloscope with < 50 fs rms intrinsic jitter, such as 86108B with HBW and PTB.
- Measured at a data rate of 28.4 Gb/s, using the Keysight E8257D-520 as precision clock source.
The specifications below apply for use with J-BERT N4903B and J-BERT M8020A. Figure 10. Front panel of M8061A .
Table 6. Specifications for CMI in, DMI in, electrical idle in combiners and adjustable gain are built-into M8061A. Table 4. Specifications for data in Table 5. Specifications for clock out, aux clock in and clock in
Table 8. Remote control interface Interface to controlling PC USB 2.0 mini (requires AXIe chassis with USB option, e.g. See pre-requisites for M8020A. Table 7. General characteristics be in the same chassis as M8041A. the two M8061As in a second chassis.
11 | Keysight | M8061A 32 Gb/s Multiplexer with De-Emphasis - Data Sheet The M8061A module includes the following accessories by default: Two 50 Ω terminations, USB cable, getting started guide, commercial calibration report (“UK6”), ESD protection kit. For M8061As with S/N larger than DE53800200 one M8061A-803 band pass filter is included. For M8061A-BU2 and M8020A-BU2 some additional accessories for the AXIe chassis are provided, such as getting started guide, filler panel. Multiplexer 2:1 up to 28.4 Gb/s, 2-slot AXIe module M8061A-001 De-emphasis, 4 calibrated taps M8061A-004 De-emphasis, extension to 8 taps M8061A-008 M8061A bundles with AXIe chassis Bundle consisting of M9505A-U20 AXIe 5 slot chassis with USB option (requires external PC and M8070A software). Recommended for use with J-BERT M8020A. M8020A-BU2 Bundle consisting of M9502A-U20 AXIe 2 slot chassis with USB option. Recommended for use with J-BERT N4903B. M8061A-BU2 Software for M8061A For use with J-BERT M8020A the M8070A system software for the M8000 series is required: – Transportable, perpetual license – Network, perpetual license Note: for use with N4903B the M8061A is controlled from N4903B user interface via USB connection. M8070A-0TP M8070A-0NP Recommended accessories Cable kit for connecting M8061A with J-BERT M8020A, 3 x 3.5 mm, 0.6 m (required) M8061A-804 Matched cable kit for connecting M8061A with J-BERT N4903B (required) M8061A-801 Matched cable pair, 2.4 mm (m f) to 2.4 mm (m f) for data outputs N4910A Four SMA cables, unmatched 15442A Band pass filter 11.4 to 15.6 GHz, SMA (for use with M8020A and M8061A in clock path to minimize intrinsic RJ of M8061A for data rate of 25.78 Gb/s) M8061A-802 1 Band pass filter 11.1 to 17.5 GHz, SMA (for use with M8020A and M8061A in clock path to minimize intrinsic RJ of M8061A for data rates from 25.0 to 32.0 Gb/s) M8061A-803 1 6 dB attenuator, 50 GHz (when data outputs is driving into non- 50 Ω inputs and for over-voltage protection, e.g. for some high-performance oscilloscopes) 8490D DC block, 50 GHz (when data output drives into a single ended, AC coupled input, such as 81490A ref. transmitter) N9398F Rack-mount kit for AXIe 2-slot chassis M9502A Y1225A 5-slot AXIe chassis (alternatively to M8061A-BU2) with USB option M9505A-U20 Rack-mount kit for AXIe 5-slot chassis M9505A Y1226A External USB hub 6:1 with power supply non-Keysight Warranty, calibration and productivity services Extended 5 year warranty Return-to-Keysight R1280 Calibration services (3 and 5 years) R1282 Productivity assistance for N4903B Productivity assistance for M8020A R1380-N49xx R1380-M80xx Specification assumptions The specifications in this document describe the instruments warranted performance when used with J-BERT M8020A or N4903B. Non-warranted values are described as typical. All specifications are valid in the specified operating temperature range after the warm-up time and after auto-adjustment. If not otherwise stated all outputs need to be terminated with 50 Ω to GND. All specifications if not otherwise stated are valid using the recommended cable set N4910A (2.4 mm, 24” matched pair). Related Keysight literature J-BERT N4903B High-Performance Serial BERT - Data Sheet 5990-3217EN J-BERT M8020A High-Performance BERT - Data Sheet 5991-3647EN N4877A Clock Data Recovery and Demultiplexer 1:2, N1075A Optical Pick-Off/Converter, N1070A Optical Clock Recovery Solution, Data Sheet 5990-9949EN Error Detection Up to 28.4 Gb/s During Receiver Test with the Keysight J-BERT N4903B Using Under-Sampling Techniques, Application Note 5990-6239EN M9502A and M9505A 2- and 5-Slot AXIe Chassis, Data Sheet 5990-6584EN 2-Slot and 5-Slot AXIe Chassis M9502A, M9505A, Start-up Guide M9502-90001 Characterizing and verifying compliance of 100 Gb Ethernet components and systems, Application Note 5992-0019EN Ordering instructions
12 | Keysight | M8061A 32 Gb/s Multiplexer with De-Emphasis - Data Sheet Recommended J-BERT M8020A configuration for 1 channel 32 Gb/s BERT – J-BERT with 5-slot AXIe chassis, requires external PC with USB connection – M8000 System Software – J-BERT 16G Generator Analyzer Clock Module with options for second generator channel, second analyzer channel – 32G Mux 2:1 – 32G CDR and Demultiplexer 1:2 – Accessories: cable triplet for connecting M8061A with M8041A (also for connecting N4877A with M8041A), 2.4 mm matched cable pair for M8061A data outputs Optional: – Advanced jitter sources in M8041A – De-emphasis 4 tap – Extension to 8 tap de-emphasis – Optimized intrinsic RJ @25.78 Gb/s with band pass filter Note: De-emphasis on M8041A is not required for operation with M8061A. Equalization and interference sources of M8041A cannot be used for operation with M8061A/ N4877A. M8020A-BU2 M8070A-0TP M8041A-C16,-0G2,-0A2 M8061A-001 N4877A-232 M8061A-804, N4910A M8041A-0G3 M8061A-004 M8061A-008 M8061A-802 Recommended J-BERT N4903B configuration for 1 channel 28G BERT configuration N4903B with options -C13 (BERT 12.5 G), -002 (second channel), and -D14 (extension PG to 14.2 G). Optional: N4903B -J10 (jitter sources), -J20 (interference and ISI). Optional: N4877A-232 CDR and Demux 1:2, 32 Gb/s Optional: E8257D-520 (Precision Signal Generator 20 GHz as clean clock source) 1 below 25 Gb/s a band pass filter is not required. When M8061A is used with N4903B the band pass filters should not be used in the clock path. Ordering instructions (continued) Upgrade options for M8061A (note: upgrades are possible on-site via licenses for M8020A users.) Upgrade to de-emphasis, 4 calibrated taps M8061A-U04 Upgrade to de-emphasis extension to 8 taps M8061A-U08
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