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M8040A High-Performance BERT 64 GBaud Preliminary Data Sheet Version 0.9 Master your 400G design

The Keysight Technologies Inc. M8040A is a highly integrated BERT for physical layer characterization and compliance testing. With support for pulse amplitude modulation 4-level (PAM-4) and non-return-to-zero (NRZ) signals, and symbol rates up to 64 GBaud (corresponds to 128 Gbit/s) it covers all flavors of the emerging 400/200 GbE and CEI-56G standards. The M8040A BERT´ s true error analysis provides repeatable and accurate results, optimizing the performance margins of your devices. Key features – Data rates from 2 to 32 and 64 GBaud – PAM-4 and NRZ selectable from user interface – Built-in 4 tap de-emphasis to compensate loss – Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, and clk/2 jitter – Two pattern generator channels per module to emulate aggressor lane – Linearity tests with adjustable PAM-4 levels – Short connections to the DUT with remote heads for the pattern generator – True PAM-4 error detection in real-time for low BER levels – Graphical user interface and remote control via M8000 system software – Scalable and upgradeable with options and modules

Applications

The M8040A is designed for R&D and test engineers who characterize chips, devices, transceiver modules and sub-components, boards and systems with serial I/O ports operating with symbol rates up to 32 GBaud and 64 GBaud in the data center and communications industries. The M8040A can be used for receiver (input) testing for many popular interconnect standards, such as: – IEEE 802.3bs 400 and 200 Gigabit Ethernet (200GAUI, 200GBASE, 400GAUI, 400GBASE) – IEEE 802.3bj 100 Gigabit Ethernet – 50 Gigabit Ethernet – OIF CEI - 56G (NRZ and PAM-4 versions) – 64G/112G Fibre Channel – Infiniband-HDR – Proprietary interfaces for chip-to-chip, chip-to-module, backplanes, repeaters, and active optical cables, operating up to 64 GBaud. Introduction

Figure 1. The M8000 Series BER test solution is highly integrated and scalable to address the test challenges of the next generation of high-speed digital characterization, validation, and compliance testing.

generator output channel to emulate an aggressor lane. measure down to very low BER and SER. frequency of re-adjustments is reduced, resulting in a more efficient use of overall test time. Figure 2. The M8040A streamlines complex receiver test setups. Each of the 1 or 2 pattern generator channels provides need to split up the PAM-4 signal for multiple error detector channels.

53.125 Gbit/s NRZ * 8 lanes

53.125 GBaud PAM-4 * 4

Figure 7. M8040A supports data rates up to 32 Gb/s NRZ, 64 Gb/s NRZ, 32 GBaud PAM-4 and 64 GBaud PAM-4. The user interface allows selection of NRZ and PAM-4 without reconnecting the BERT test setup.

32 Gbit/s 32 Gb/s 16 GBaud

64 Gbit/s 64 Gb/s 32 GBaud

128 Gbit/s 128 Gb/s 64 GBaud

26.5625 Gbit/s NRZ * 16 lanes

26.5625 GBaud PAM-4 * 8 lanes

53.125 GBaud PAM-4 * 4 lanes

world should be tolerated by the receiver under test without exceeding the desired BER level.

0.67 A Max

Figure 8. PAM-4 eyes can show a level separation mismatch. Receivers must be able to detect the digital signal content properly within the given mismatch ratio. emulating the worst-case transmitter and channel conditions. translates just into one symbol error. Figure 9. Only a true PAM-4 error analyzer like M8040A, can provide a PAM-4 symbol error rate in real-time without QPRBS31-CEI patterns. Errored 0,1,2,3 and symbol errors can be counted separately for further debugging.

Figure 10. Front panel views of pattern generator module M8045A (top) as 2 and 1 channel (center) versions, remote the remote head is used. One remote head is needed for each of the pattern generator data outputs of M8045A.

64.8 GBaud) for M8045A Option -G64

Skew between normal and complement output 3 ps maximum at the end of the recommended cable pair. Fixed. Termination 50 Ω into GND or external termination voltage. Do not operate into open. Unused outputs must be terminated into termination voltage. M8045A without remote head is prohibited.

  1. At Tbd measured with DCA-X 86108B and clock pattern and in the middle of the eye.
  2. Measured with DCA-X 86118A.

Table 1. Data output characteristics for M8045A with remote head M8057A.

Table 2. Specifications for multi-tap de-emphasis (requires Option 0G4).

  1. Sum of all cursors absolute values may not exceed 1.0 |c0| +|c1| +|c2 |+|c3| ≤ 1. Also |c0|, |c1|, |c3| < |c2|.

Figure 11. The pattern generator of M8045A provides integrated de-emphasis to emulate TX equalization. The post- cursor c3 , main cursor c2 and two pre cursors c0 and c1 can be adjusted.

Termination 50 Ω into GND or external termination voltage. Do not operate into open. Table 3. Specifications for channel 1 clock output and channel 2 clock output.

has the same setting as HF jitter of data output of channel 1. Table 4. Clock output specifications.

  1. If Vterm is other than 0 V the following applies:
  2. For 8.1 to 16.2 GHz clocks.

Table 5. Clock modes.

  1. If Vterm is other than 0 V the following applies:

Table 6. Reference clock input specifications (M8045A only).

  1. Sequence block trigger with adjustable pulse width and offset
  2. PRBS sequence trigger with adjustable pulse width

Table 7. Trigger output specifications. Outputs a 10 and 100 MHz clock, 1 Vpp single ended into 50 Ω. Functionality of each input can be selected as: sequence trigger, error add and pattern capture event. Table 8. Control input specifications.

Outputs a pulse in case of an error. Generates a pulse or static high/low if used from sequencer. Table 9. Control output specifications.

  1. When terminated with 50 Ω into GND. Doubles into open.

These are control inputs to synchronize events for the pattern sequencer. Table 10. System input specifications. Generates a pulse or static high/low controlled by the pattern sequencer. A and B outputs are identical. Table 11. System output specifications.

  1. When terminated with 50 Ω into GND. Doubles into open.

For future use. See reference clock input for direct clock mode.

100 Hz 10 kHz 40 MHz Modulation frequency

0.0062 UI * symbol rate (in GBaud)

123.5 UI * symbol rate (in GBaud)

The M8045A has integrated and calibrated jitter sources. To use the jitter injection the M8045A Option –0G3 is required. Table 12. Specifications for low frequency periodic jitter (requires Option -0G3 advanced jitter sources).

100 Hz to 10 kHz

10 MHz

40 MHz

Table 13. System output specifications. Figure 12. Low frequency periodic jitter maximum depends on data rate and modulation frequency.

< 4 GBaud the max modulation frequency is symbol rate / 8. Table 14. Specifications for high frequency periodic jitter, random jitter, bounded uncorrelated jitter, clock /2 jitter (all require M8045A Option -0G3 advanced jitter sources).

  1. 1 UI is the maximum sum of RJ, HF-PJ1 and HF-PJ2, external delay modulation and BUJ.

Table 15. BUJ accuracy applies for these BUJ settings.

  1. Other settings are not calibrated and do not necessarily generate the desired jitter histograms for all data rates of the PRBS generator.

SSC (spread spectrum clock) Range 0 to 10,000 ppm (0 to 1%) peak-peak. Select center-spread, up-spread, and down-spread. Table 16. Specifications for spread spectrum clocking (SSC). Requires M8045A Option -0G3 advanced jitter sources.

An external modulation source can be used to modulate the delay of the M8045A data outputs, clock output and trigger output. This input can be used for delay modulation by an external source for each data output channel individually. Table 17. Specifications for external jitter modulation on data outputs.

  1. See HF jitter specifications for the maximum sum of RJ, HF-PJ1 and HF-PJ2 external delay modulation and BUJ.

Table 18. Specifications for external jitter modulation for clock and trigger.

  1. See HF jitter specification for the maximum sum of RJ, HF-PJ1 and HF-PJ2, external delay modulation and BUJ.

This input can be used for delay modulation of TRIG OUT and CLK OUT, the modulation always affects both outputs.

Table 19. Specifications for pattern, sequencer.

  1. Polarity is inverted compared to ParBERT and J-BERT N4903A/B and N49xx series.

Figure 13. The pattern editor in the M8070A software allows editing NRZ bits and PAM-4 symbols. The PAM-4 symbol to bit mapping can be selected as Gray coded or

Figure 14. Front panel of M8046A The M8046A supports symbol rates up to 32 GBaud, the default is NRZ format. Sampling point Manual and automatic. Finds optimum voltage threshold and delay of the sampling point.

1 UI – Tbd ps typical for clock pattern

1 UI - Tbd ps typical for clock pattern

Table 20. Specifications for analyzer/error detector.

  1. Measured with PRBS 2 31 – 1 at Tbd Gb/s, at BER of 10 –12, clean eye

Table 21. Specifications for clock input of analyzer. M8051A-801). Not needed if external clock is used. Functionality can be selected as: sequence trigger, pattern capture event. Table 22. Specifications for control inputs of analyzer. Outputs a pulse in case of an error. Generates a pulse or static high/low if used from sequencer. Table 23. Control output specifications (M8045A and M8055A). Table 24. Measurement capabilities.

  1. Contact factory for availability.

The M8070A system software for the M8000 Series of BER test solutions is required to control the M8040A BERT. Figure 15. The graphical user interface offers multiple views that can be defined by the user. This example shows the preliminary system view on the left side and the pattern generator data output with the PAM-4 coding and level linearity parameters at the right.

transportable, perpetual license (M8070A-0TP) and a network, perpetual license (M8070A-0NP). The network license is only recommended when using multiple M8040A setups within one company. embedded controller, choose options for Windows 7 or 8, 8 or 16 GB RAM, SSD. Scripting interface The built-in scripting engine is based on IronPython. It enables the control of the device under test as well as other test equipment. Table 25. User interface and remote control interface.

provides at least 50 mm of clearance at each side. See also start-up guide for M9505A chassis. Table 26. General characteristics for M8045A and M8046A modules.

Table 27. General characteristics for M8057A remote head. range after the warm-up time and after auto-adjustment. If not otherwise stated all outputs need to be terminated with 50 Ω to GND. All M8045A specifications if not otherwise stated are valid at the end of the cable M8045A-801.

27 | Keysight | M8040A High-Performance BERT 64 GBaud - Data Sheet M8045A module: Four 50 Ω resistors, ESD protection kit, certificate of calibration, license entitlement certificate, no signal cables, no blue sync cable M8046A module: ESD protection kit, certificate of calibration, license entitlement certificate, no signal cables M8057A remote head: includes cable connection to M8045A pattern generator module, one 50 Ω termination (2.4 mm) M8040A-BU1: M9505A AXIe chassis with embedded controller, USB cable, getting started guide, AXIe filler panel, power cord M8040A-BU2: M9505A AXIe chassis, USB cable, getting started guide, AXIe filler panel, power cord M8070A: CD-ROM with M8070A system software Recommended accessories Short cable, 1.85 mm (m) to 1.85 mm (m), 0.15 m, 699 ps delay ± 1 ps (two are recommended for each differential data output of M8057A) M8045A-801 Matched cable pair 2.4 mm (m) to (m) (recommended for data input of M8046A analyzer) N4910A Cable 2.92 mm (m) to 2.92 mm (m), 0.5 m (recommended for clock input of M8046A analyzer) M8046A-801 M8000 sync cable (when using the system clock of M8045A for M8046A) M8051A-801 Attenuator, 6 dB, 1.85 mm 8490G-006 DC block 2.4 mm N9398F Rack-mount kit for AXIe 5-slot chassis M9505A Y1226A Warranty, calibration and productivity services Extended 5 year warranty Return-to-Keysight R1280 (R-51B-001-5Z) Calibration services (3 and 5 years) R1282 (R50C-001-3/-5) Productivity assistance R1380-M8000 Related Keysight literature Data sheets and configuration guides J-BERT M8020A, Data Sheet 5991-3647EN M8030A Multi-channel BERT, Data Sheet 5992-1287EN M8062A 32 Gb/s Front-end, Data Sheet 5992-0987EN N4877A and N1075A CDR/Demux, Data Sheet 5990-9949EN M9505A AXIe Chassis 5-slot, Data Sheet 5990-6584EN M8196A 92 GSa/s AWG, Data Sheet 5992-0971EN N1085A PAM-4 Measurement Application for 86100D DCA-X Series, Data Sheet 5992-1248EN N1076A/N1077A Clock recovery, Data Sheet 5992-1620EN Application notes Characterizing and verifying compliance of 100Gb Ethernet components and systems, Application Note 5992-0019EN Default accessories included with shipment

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