M8020A KEYSIGHT | Alldatasheet
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J-BERT M8020A High-Performance BERT Data Sheet Version 3.0 Eye diagram measurements Bit recovery mode Add ISI and Jitter with AWG Master your next designs NEW
The high-performance Keysight Technologies, Inc. J-BERT M8020A enables fast and accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s. With today’s highest level of integration, the M8020A streamlines your test setup. In addition, automated in situ calibration of signal conditions ensures accurate and repeatable measurements. And, through interactive link training, it can behave like your DUT’s link partner. All in all, the J-BERT M8020A will accelerate insight into your design. Key features: – Data rates up to 8.5 and 16 Gb/s expandable to 32 Gb/s – 1 to 4 BERT channels in a 5-slot AXIe chassis – Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal level interference (common-mode and differential-mode), SSC (triangular and arbitrary, residual) and Clock/2 – 8 tap de-emphasis, positive and negative – Integrated and adjustable ISI – Interactive link training for PCI Express – Built-in clock recovery and equalization – All options and modules are upgradeable Applications: The J-BERT M8020A is designed for R&D and test engineers who characterize and verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s and 32 Gb/s in the consumer, computer, mobile computing, datacenter and communications industry. The J-BERT M8020A can be used to test popular serial bus standards, such as PCI Express ®, SATA/SAS, DisplayPort, USB Super Speed, MIPI ® M-PHY®, SD UHS-II, Fibre Channel, QPI, memory buses , backplanes, repeaters, active optical cables, Thunderbolt, 10/40 GbE/SFP+/QSFP, 100GbE/CFP2.
accelerate your insight into the performance margins of high-speed digital devices. Shift into high gear with the M8000 Series and take the design verification express lane. Figure 1. The M8000 Series BER Test Solution is highly integrated and scalable to address the test challenges of the next generation of high-speed digital receiver test.
16 Gb/s J-BERT M8020A
32 Gbaud, 4 channel
32 Gb/s J-BERT M8020A
adjustable loop bandwidth for the analyzer is built-in. Figure 2. J-BERT M8020A streamlines complex receiver test setups. The example shows a PCIe 3 (8 GT/s) mother board RX test (CEM spec) with J-BERT
Figure 9. The J-BERT M8020A can be configured as a complete 32 Gb/s BERT for accurate receiver user interface allows controlling all parameters of the 32 Gb/s pattern generator and analyzer.
Figure 10. The graphical user interface for J-BERT M8020A offers multiple views that can be defined by the user. This example shows the system view on left side and the pattern generator data output parameters at the right.
data signal on each channel individually. Figure 11. Multiple M8030A 10 channel module view
times, eye height and eye width, as just a few examples, are provided with this measurement tool. Figure 12. Eye diagam measurement with J-BERT M8020A Analyzer
Figure 17. Front panel view of M8041A module (bottom) and M8051A (top). Please refer to M8061A data sheet (5991-2506EN) for specification details. Please refer to M8062A data sheet (5992-0987EN) for specification details.
Table 1. Data output characteristics for M8041A and M8051A. addresses LVDS, CML, low-voltage CMOS, others. offset within 4 ns typical. Electrical idle can be controlled from sequencer. Termination 50 Ω into GND or external termination voltage. Do not operate into open. Unused outputs must be terminated into termination voltage.
- At 16.2 Gb/s PRBS 215-1, BER 10 -12, with internal clock.
- At 16 Gb/s and clock pattern.
- At 256 Mb/s measured with DCA-X 86108B and clock pattern and in the middle of the eye.
- Per output when differentially terminated into 100 Ω. Results in doubled swing when driving into open.
- Measured with DCA-X 86118A. For serial numbers below DE55300500 for M8041A or M8051A: 15 to 20 ps typical (20%-80%)
Figure 18. Definition of nominal output amplitude and de-emphasis. Table 2. Data output amplitude maximum (single ended) in presence of DMI, CMI, offset voltage.
- For DMI < 12.5 % of amplitude.
Table 3. Specifications for multi-tap de-emphasis (requires option 0G4).
- Sum of all cursors may not exceed Vpp max. The tap accuracy applies for PCIe 3 presets for pre-cursor 1 and post-cursor 1 at 8 Gb/s.
Table 4. Clock output specifications outputs must be terminated into termination voltage.
- If Vterm is other than 0 V the following applies:
- For 8.1 to 16.2 GHz clocks.
Table 5. Clock modes (M8041A only).
- Intended use with settings in Table 7 (other settings may be possible, contact factory)
internal oscillator. It also allows to use an external clock, see clock modes. Table 6. Reference clock input specifications (M8041A only). Table 7. Predefined settings for reference clock multiplier (M8041A with option 0G6 only).
100 MHz PCIe 4 16 Gb/s 160 2 MHz
100 MHz PCIe 3 8 Gb/s 80 5 MHz
100 MHz PCIe 2 5 Gb/s 50 5 MHz
26 MHz to 52 MHz SD UHS-II 390 Mb/s to 780 Mb/s 15 2 MHz
2 MHz
- Note: a minimal slew rate of 0.3 V/ns at the REF CLK IN signal is required to ensure a proper frequency measurement.
If this requirement can’t be met the input frequency should be set manually.
- Divided clock, dividers: 2 to 65535
- Sequence block trigger with adjustable pulse width and offset
- PRBS sequence trigger with adjustable pulse width
Table 8. Trigger output specifications (M8041A only).
- If Vterm is other than 0 V the following applies:
Outputs a 10 and 100 MHz clock, 1 Vpp single ended into 50 Ω. M8041A only. For future use. For M8041A only. See reference clock input for direct clock mode. Functionality of each input can be selected as: sequence trigger, error add and pattern capture event. Table 9. Control input specifications (M8041A and M8051A). Outputs a pulse in case of an error. Generates a pulse or static high/low if used from sequencer. Table 10. Control output specifications (M8041A and M8051A).
- When terminated with 50 Ω into GND. Doubles into open.
The Sync output on M8041A: clock output to synchronize multiple modules to a common clock. The Sync input is a clock input on M8051A module to synchronize additional modules to a common clock. A sync cable is delivered with each M8051A module by default. Control inputs to synchronize events for the pattern sequencer. Auxiliary input: for future use. For M8041A only. Table 11. System input and auxiliary input specifications (M8041A only) Generates a pulse or static high/low controlled by the pattern sequencer. Table 12. System output specifications (M8041A only).
- When terminated with 50 Ω into GND. Doubles into open.
Figure 19. This table shows typical values for X in unit intervals (UI) in order to calculate the delay between SYS Input and CTRL input to the data out - puts of M8041A and M8051A. The X depends on data rate and the selected coding (symbol width).
Figure 20. Low frequency periodic jitter maximum depends on data rate and modulation frequency.
123.5 UI * data rate [in Gb/s]
0.1235 UI * data rate [in Gb/s]
100 Hz 10 kHz 10 MHz
standards such as: PCIe, USB, MIPI, SATA, DisplayPort, CPU frontside buses, CEI, 10GbE, 100GbE, SFP+, QSFP, CFP2/4, etc. M8020A provides automated jitter tolerance measurements. A library of pre-defined compliance curves is provided. Table 13. Specifications for low frequency periodic jitter (requires option 0G3 advanced jitter sources).
Table 14. Specifications for high frequency periodic jitter, random jitter, spectrally distributed random jitter, bounded uncorrelated jitter, Clock/2 jitter (requires option 0G3 advanced jitter sources). spectral RJ, external delay modulation and BUJ. rate / 8. Two tone possible. Sweep. Clock/2 jitter Range ± 20 ps or ± 0.1 UI typical (whatever is less).
- 1 UI is the maximum sum of RJ, HF-PJ1 and HF-PJ2, spectral RJ, external delay modulation and BUJ.
- Spectrally distributed random jitter is mutually exclusive with RJ and BUJ.
Table 15. BUJ accuracy applies for these BUJ settings.
- Other settings are not calibrated and do not necessarily generate the desired jitter histograms for all data rates of the PRBS generator.
Table 16. Specifications for Spread Spectrum Clocking (SSC) (requires opt. 0G3: advanced jitter sources). center-spread, up-spread, and down-spread. Table 17. Specifications for external jitter modulation (DATA MOD IN 1 and 2, CLK MOD IN). M8041A allows individual jitter injection for data 1, data 2 and clock. M8051A for data 1 and data 2. The option 0G3 is not needed.
- 1 UI is the maximum sum of RJ, HF-PJ1 and HF-PJ2, spectral RJ, external delay modulation and BUJ.
Figure 21. The adjustable ISI can be controlled over a wide range. The chart on the left shows the range for 1 point control. The upper loss point P1 is fix, only the lower point P2 can be varied over a wide range within min and max slope. Table 18. Specifications for adjustable Intersymbol Interference (ISI). Adjustable ISI is offered for M8041A and M8051A and requires option 0G5 and serial number
- Within slope range and IL offset range. Frequency of lower point (P2) must be > frequency of upper point (P1).
Figure 22. J-BERT M8020A system view for 1 channel.
For detailed specifications see M8048A data sheet. superposition and gain adjust parameters. Table 19. Specifications for sinusoidal level interference (CMI, DMI) (requires option 0G7). CMI and DMI. See figure below.
- The maximum output amplitude decreases when CMI or DMI is enabled. See table 2.
- For each channel independently.
Figure 23. M8020A provides calibrated level interference sources for simultaneous injection of CMI (common mode interference) and DMI (differential mode interference).
Table 20. Specifications for pattern, sequencer and link training. upstream ports according to PCI Express Architecture PHY Test Specification.
2.3 Add-in Card Transmitter Initial Tx EQ Test for 8 GT/s
2.4 Add-in Card Transmitter Link Equalization Response Test for 8 GT/s
2.7 System Board Transmitter Link equalization Response Test for 8 GT/s
2.10 Add-in Card Receiver Link Equalization Test for 8 GT/s
2.11 System Board Receiver Link Equalization Test for 8 GT/s
- Note: polarity is inverted compared to ParBERT and J-BERT N4903A/B and N49xx models.
- For availability: contact factory. Free software update.
- Modified compliance pattern for PCIe3.
Figure 24. The J-BERT M8020A analyzer can capture up to 2 Gbit per channel. Capture events and depth can be defined. The captured pattern can be exported and loaded as generator pattern or as expected pattern for further error analysis. The example shows errored bits in red with navigation arrows.
Each M8041A/51A analyzer channel includes a clock recovery. – For 32 Gb/s setups the N4877A-232 CDR and Demultiplexer is required to use the M8020A analysis functions. Table 21. Specifications for analyzer / error detector (Option C08 or C16).
0.50 Vpp single ended @ high-sensitivity mode
Clock data recovery Yes for each input channel. See table 21 for more details. ± 0.5 V range from common mode voltage.
1 UI - 7 ps typical for clock pattern
- Measured with PRBS 2 31 - 1 at 16 Gb/s, AC coupling mode, BER of 10 -12, CTLE disabled.
- For availability please contact factory.
- Termination voltage must be within a window of DC common mode voltage ± 1.7 V.
- Eye height measured at input of reference cable M8041A-801 with DCA-X module 86117A. Applies for single ended and differential input signals.
Table 23. Measurement capabilities (Option C08 or C16). Filtering of filler symbols Automatic removal of filler symbols. See also the description above. Figure 27. CDR loop bandwidth range for a transition density of 50%
The M8070A system software for the M8000 Series of BER Test Solutions is required to control M8041A, M8051A, M8061A, and M8062A. Table 24. User interface and remote control interface. ordering M8020A-BU1 the M8070A-0TP license will be pre-installed on the embedded controller. Scripting interface The built-in scripting engine is based on IronPython. It enables the control of the device under test as well as other test equipment. Figure 28. The built-in scripting engine of J-BERT M8020A allows to communicate with the DUT or other instruments. The scripting language is Iron Python.
Table 25. General characteristics for M8041A and M8051A modules. vides at least 50 mm of clearance at each side. See also start-up guide for M9505A chassis.
Please refer to the J-BERT M8020A High-Performance BERT - Configuration Guide (5991-4032EN) for ordering details.
16 Gb/s High-performance BERT, 1-2 channel
16 Gb/s High-performance BERT, 3-4 channel
32 Gb/s High-performance BERT, 1 channel with M8061A/62A
(external PC not shown). Setup with M8061A requires N4877A as CDR/Demux. Figure 29. Overview of possible J-BERT M8020A configurations. M8041A module: eight 50 Ω terminations, commercial calibration report (“UK6”), certificate of calibration, ESD protection kit.
35 | Keysight | J-BERT M8020A High-Performance BERT - Data Sheet Recommended accessories: Matched cable pair, 2.92 mm (m) to 2.92 mm (m), 0.85 m (Recommended for each data output of M8041A/51A. M8041A-801 This 2.92 mm cable is compatible with 3.5 mm front panel connectors of M8041A/51A.) Bandpass filter 11.4 to 15.6 GHz, SMA (For use with M8061A in clock path to minimize intrinsic RJ of M8061A M8061A-802 for data rate of 25.78 Gb/s.) Bandpass filter 11.1 to 17.5 GHz, SMA (For use with M8061A in clock path to minimize intrinsic RJ of M8061A M8061A-803 for data rates from 25.0 to 32.0 Gb/s) Cable kit for connecting M8061A with M8020A, 3x 3.5 mm, 0.6 m M8061A-804 DC block, 26 GHz, 3.5 mm N9398C ISI channels, four short traces M8048A-001 ISI channels, four long traces M8048A-002 Short matched cable pair, SMA (m) to SMA (m) for cascading M8048A ISI channels M8048A-801 Four SMA cables, unmatched 15442A Rack-mount kit for AXIe 5-slot chassis M9505A Y1226A Test automation software with support of M8020A Test automation software for PCIe receiver test N5990A-101 Test automation software for USB receiver test N5990A-102 Test automation software for SATA receiver test N5990A-103 Test automation software for DisplayPort N5590A-155 Test automation software for MIPI M-PHY N5590A-165 USB link training suite N5990A-302 SATA link training suite N5990A-303 MIPI M-PHY frame generator N5590A-365 PCIe link training suite N5990A-301 PCIe link equalization tests N5990A-501 Test automation software, core N5990A-010 Warranty, calibration and productivity services: Extended 5 year warranty Return-to-Keysight R1280 (R-51B-001-5Z) Calibration services (3 and 5 years) R1282 Productivity assistance R1380-M8000 Related Keysight literature Data sheets and configuration guides: M8048A ISI Channels, Data Sheet 5991-3548EN M8061A Multiplexer with De-Emphasis, Data Sheet 5991-2506EN M8062A 32Gb/s BERT Front-End, Data Sheet 5992-0987EN M8030A Multi-channel BERT, Data Sheet 5992-1287EN J-BERT N4903B high-performance BERT, Data Sheet 5990-3217EN N4877A and N1075A CDR/Demux, Data Sheet 5990-9949EN M9505A AXIe Chassis 5-slot, Data Sheet 5990-6584EN J-BERT M8020A, Configuration Guide 5991-4032EN Application notes: Master your MIPI M-PHY receiver test using J-BERT M8020A , Application Brief 5991-3959EN How to pass receiver test according PCI Express CEM specification , Application Note 5990-9208EN Accurate calibration of PCIe 3.0 receiver stress signals, Application Note 5990-6599EN How to test a MIPI M-PHY high-speed receiver, Application Note 5991-2848EN Master your next PCIe3 receiver test using J-BERT M8020A, Application Note 5991-4190EN Master your next USB 3.x designs with J-BERT M8020A, Application Note 5991-4357EN Characterizing and verifying compliance of 100Gb Ethernet components and systems, 5992-0019EN Application Note
36 | Keysight | J-BERT M8020A High-Performance BERT - Data Sheet This information is subject to change without notice. © Keysight Technologies, 2014 - 2016 Published in USA, February 25, 2016 5991-3647EN www.keysight.com For more information on Keysight Technologies’ products, applications or services, please contact your local Keysight office. The complete list is available at: www.keysight.com/find/contactus Americas Canada (877) 894 4414 Brazil 55 11 3351 7010 Mexico 001 800 254 2440 United States (800) 829 4444 Asia Pacific Australia 1 800 629 485 China 800 810 0189 Hong Kong 800 938 693 India 1 800 11 2626 Japan 0120 (421) 345 Korea 080 769 0800 Malaysia 1 800 888 848 Singapore 1 800 375 8100 Taiwan 0800 047 866 Other AP Countries (65) 6375 8100 Europe & Middle East Austria 0800 001122 Belgium 0800 58580 Finland 0800 523252 France 0805 980333 Germany 0800 6270999 Ireland 1800 832700 Israel 1 809 343051 Italy 800 599100 Luxembourg +32 800 58580 Netherlands 0800 0233200 Russia 8800 5009286 Spain 800 000154 Sweden 0200 882255 Switzerland 0800 805353 Opt. 1 (DE) Opt. 2 (FR) Opt. 3 (IT) United Kingdom 0800 0260637 For other unlisted countries: www.keysight.com/find/contactus (BP-02-10-16) DEKRA Certified ISO9001 Quality Management System www.keysight.com/go/quality Keysight Technologies, Inc. DEKRA Certified ISO 9001:2015 Quality Management System myKeysight www.keysight.com/find/mykeysight A personalized view into the information most relevant to you. Three-Year Warranty www.keysight.com/find/ThreeYearWarranty Keysight’s committed to superior product quality and lower total cost of ownership. Keysight is the only test and measurement company with three-year warranty standard on all instruments, worldwide. And, we provide a one-year warranty on many accessories, calibration devices, systems and custom products. Keysight Assurance Plans www.keysight.com/find/AssurancePlans Up to ten years of protection and no budgetary surprises to ensure your instruments are operating to specification, so you can rely on accurate measurements. Keysight Infoline www.keysight.com/find/service Keysight’s insight to best in class information management. Free access to your Keysight equipment company reports and e-library. Keysight Channel Partners www.keysight.com/find/channelpartners Get the best of both worlds: Keysight’s measurement expertise and product breadth, combined with channel partner convenience. www.keysight.com/find/m8020a From Hewlett-Packard through Agilent to Keysight For more than 75 years, we‘ve been helping you unlock measurement insights. Our unique combination of hardware, software and people can help you reach your next breakthrough. Unlocking measurement insights since 1939.