M48T08 ARTSCHIP | Alldatasheet
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Technical content
WRITEs that can be performed. long- life lithium button cell in a single package. Figure 3. Logic Diagram Table 1. Signal Names
M48T08/18/08Y are integrated on one silicon chip. and also stores the clock calibration setting. any other location in the static memory array. Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
- See Table 11., page 20 for details.
Figure 7. READ Mode AC Waveforms Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Figure 8. WRITE Enable Controlled, WRITE AC Waveform
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
Table 4. WRITE Mode AC Characteristics
M48T08, M48T08Y, M48T18 Data Retention Mode With valid VCC applied, the M48T08/18/08Y oper- ates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will au- tomatically power-fail deselect, write protecting it- self when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high imped- ance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's con- tent. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T08/18/08Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which pre- serves data and powers the clock. The internal button cell will maintain data in the M48T08/18/ 08Y for an accumulated period of at least 10 years when VCC is less than VSO. Note: Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inad- vertent WRITE cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. Power-fail Interrupt Pin The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between 10µs and 40µs before automatically deselecting the M48T08/18/ 08Y. The INT pin is an open drain output and re- quires an external pull up resistor, even if the inter- rupt output function is not being used.
READ Bit, the seventh bit in the control register. Bit, halts updates to the TIMEKEEPER registers. Table 5. Register Map
M48T08, M48T08Y, M48T18 Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from STMi- croelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T08/18/08Y oscillator starts within one second. Note: To guarantee oscillator start-up after initial power-up, first write the STOP Bit (ST) to '1,' then reset to '0.' Calibrating the Clock The M48T08/18/08Y is driven by a quartz-con- trolled oscillator with a nominal frequency of 32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25°C without calibra- tion. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than +1/–2 ppm at 25°C. The oscillation rate of any crystal changes with temperature. Figure 10., page 15 shows the fre- quency error that can be expected at various tem- peratures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T08/18/ 08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in Figure 11., page 15. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the Sign Bit; '1' indicates pos- itive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibra- tion step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may re- quire. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the fi- nal product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manu- facturing environment, and involves the use of standard test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the Sec- onds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would in- dicate a +20 ppm oscillator frequency error, requir- ing a –10 (WR001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output fre- quency. The device must be selected and ad- dresses must be stable at Address 1FF9h when reading the 512 Hz on DQ0. The LSB of the Seconds Register is monitored by holding the M48T08/18/08Y in an extended READ of the Seconds Register, but without having the READ Bit set. The FT Bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the Appli- cation Note AN934, “TIMEKEEPER® Calibration.”
MBRS120T3 is recommended for surface mount. Figure 12. Supply Voltage Protection
Table 6. Absolute Maximum Ratings
- For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
- For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
tions when using the quoted parameters. Table 7. Operating and AC Measurement Conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 13. AC Testing Load Circuit Table 8. Capacitance Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
Table 9. DC Characteristics
- Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
- Negative spikes of –1V allowed for up to 10ns once per Cycle.
- The INT pin is Open Drain.
Figure 14. Power Down/Up Mode AC Waveforms Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. Table 10. Power Down/Up AC Characteristics
- VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
- VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power Down/Up Trip Points DC Characteristics Note: 1. All voltages referenced to VSS.
- At 55°C, VCC = 0V; tDR = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package.
Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline Note: Drawing is not to scale. Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline Note: Drawing is not to scale. Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data
Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
Table 16. Ordering Information Scheme Note: 1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
- The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part number
SOH28 (SNAPHAT) package only. Table 17. SNAPHAT Battery Table
M48T08, M48T08Y, M48T18
REVISION HISTORY
Table 18. Document Revision History
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