M48T02 ARTSCHIP | Alldatasheet
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Technical content
5.0V, 16 Kbit (2Kb x8) TIMEKEEPER® SRAM FEATURES SUMMARY ■ INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, AND POWER-FAIL CONTROL CIRCUIT ■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, AND SECONDS ■ TYPICAL CLOCK ACCURACY OF ±1 MINUTE A MONTH, AT 25°C ■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■ AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION ■ WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): – M48T02: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48T12: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V ■ SELF-CONTAINED BATTERY AND CRYSTAL IN THE CAPHAT™ DIP PACKAGE ■ PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 2K x8 SRAMs Figure 1. Package
Figure 4. Block Diagram
months are made automatically. also stores the clock calibration setting. any other location in the static memory array. operation until valid power returns. Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
- See Table 11., page 17 for details.
one of the 2,048 bytes of data is to be accessed. Figure 5. READ Mode AC Waveforms Note: WRITE Enable (W) = High. Table 3. READ Mode AC Characteristics
Table 4. WRITE Mode AC Characteristics
as a conventional BYTEWIDE™ static RAM. state, provided the VCC fall time is not less than tF. is set, the first WRITE attempted will be blocked. fer to the Application Note AN1012. Figure 8. Checking the BOK Flag Status
READ Bit, the seventh bit in the control register. Bit, halts updates to the TIMEKEEPER registers. low for normal TIMEKEEPER and RAM operation. Table 5. Register Map
M48T02, M48T12 Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T02/12 is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T02/12 oscillator starts within one second. Calibrating the Clock The M48T02/12 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T02/12 is accurate within 1 minute per month at 25°C without calibration. The devices are tested not to exceed ± 35 ppm (parts per mil- lion) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. The oscillation rate of any crystal changes with temperature. Figure 9., page 13 shows the fre- quency error that can be expected at various tem- peratures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T02/12 design, however, employs periodic counter cor- rection. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in Figure 10., page 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the Sign Bit; '1' indicates pos- itive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibra- tion step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T02/12 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his en- vironment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the Seconds Reg- ister will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For exam- ple, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a – 10 (WR001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output fre- quency. The device must be selected and ad- dresses must be stable at Address 7F9 when reading the 512 Hz on DQ0. The FT Bit must be set using the same method used to set the clock: using the WRITE Bit. The LSB of the Seconds Register is monitored by hold- ing the M48T02/12 in an extended READ of the Seconds Register, but without having the READ Bit set. The FT Bit MUST be reset to '0' for normal clock operations to resume. Note: It is not necessary to set the WRITE Bit when setting or resetting the Frequency Test Bit (FT) or the Stop Bit (ST). For more information on calibration, see the Appli- cation Note AN924, “TIMEKEEPER® Calibration.”
MBRS120T3 is recommended for surface mount. Figure 11. Supply Voltage Protection
Table 6. Absolute Maximum Ratings Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. tions when using the quoted parameters. Table 7. Operating and AC Measurement Conditions Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC Testing Load Circuit Table 8. Capacitance Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Table 9. DC Characteristics
- Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
- Negative spikes of –1V allowed for up to 10ns once per Cycle.
Figure 13. Power Down/Up Mode AC Waveforms power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. Table 10. Power Down/Up AC Characteristics
- VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
- VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power Down/Up Trip Points DC Characteristics Note: 1. All voltages referenced to VSS.
Figure 14. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Outline Note: Drawing is not to scale. Table 12. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
Table 13. Ordering Information Scheme
M48T02, M48T12
REVISION HISTORY
Table 14. Document Revision History
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