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July 2, 2020 Page 1 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Arm® Cortex® -M 32-bit Microcontroller NuMicro® Family M251/M252 Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com
July 2, 2020 Page 2 of 266 Rev 1.01 M251/M252 SERIES DATASHEET TABLE OF CONTENTS
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8.4.4 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) Characteristics
8.4.6 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristic s
July 2, 2020 Page 6 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.4.7 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
July 2, 2020 Page 9 of 266 Rev 1.01 M251/M252 SERIES DATASHEET List of Tables
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1 GENERAL DESCRIPTION
The NuMicro® M251/M252 series is a low -power microcontroller platform based on Arm ® Cortex® - M23 core for Armv8 -M architecture. It runs up to 48 MHz with 32 ~ 256 Kbytes embedded Flash memory and 8 ~ 32 Kbytes embedded SRAM, 4 Kbytes Flash loader memory (LD ROM) for In- System Programming (ISP) . The 32-bit low-power microcontrollers suppo rts wide supply voltage from 1.75V ~ 5.5V and operating temperature range from -40℃ ~ +105℃. Low-power Technology for IoT application The NuMicro ® M251/M252 series behaves low pow er consumption in Normal Run mode 138μA/MHz at 48MHz, Idle mode 60 μA/MHz, Power -down mode 2.5 μA (RTC on, RAM retention), Power-down mode 1.7 μA (RTC off, RAM retention) and Deep Power -down mode. The NuMicro® M251/M252 series integrates RTC with independe nt VBAT voltage source pin to support low power mode with main power off and V BAT only. Its low power, wide supply voltage and fast wake-up features make it suitable for battery-powered IoT applications. Programmable Serial Interface (PSIO) The NuMicro® M251/M252 series provides up to 8 -channel Nuvoton proprietary interface, named as “Programmable Serial I/O” (PSIO), which is capable of generating specific waveform to emulate arbitrary serial communication protocols to connect with specific peripherals by P SIO hardware engine. PSIO can be treated as extension of popular serial communication standard (UART, SPI , I 2C, etc.), niche serial communicat ion standard and proprietary protocol (SPI -like protocol for LED -lighting application , etc.). This PSIO hardware engine can simulate comprehensive serial communication protocol with low CPU loading, low control complexity and high timing precision at the same time. High elasticity and flexibility makes PSIO a powerful and useful tool while connecting to diverse peripherals. Voltage Adjustable Interface (VAI) - Support 2nd I/O voltage without level-shifter The NuMicro® M251/M252 series integrates Voltage Adjustable Interface (VAI), up to 6 I/O pins to support the 2nd I/O voltage from 1.65V ~ 5.5V to save level shifter components while connecting to external devices. These 6 I/O pins can be configured as UART/SPI/ I2C bus by software setting. eXecute-Only-Memory (XOM) - Protect the intelligent property of developers The NuMicro® M251/M252 series provides 1 -region programable eXecute-Only-Memory (XOM) to secure critical program code . A tamper detection pin is implemented to avoid malicious damage from hacker. The 96-bit Unique Identification (UID) and 128 -bit Unique Customer Ident ification (UCID) are used to enhance the product security. Crystal-less USB 2.0 full speed device interface Part numbers of the M252 series are all based on the M251. I t supports a crystal-less USB 2.0 full speed device that can generate precise frequency required by USB protocol without the need of external crystal to reduce the BOM cost and PCB size. Rich Pheripherals for comprehensive product application scenarios The NuMicro ® M251/M252 series is equipped with plenty of peripherals such as Timers, Watchdog Timers, RTC, PDMA, External Bus Interface (EBI), UART, Universal Serial Control Interface (USCI), QSPI, SPI/ I² S, I2C, ISO -7816-3, GPIOs, up to 24 channels of PWM, makes it highly suitable for connecting comprehensive external modules and LED lighting c ontrol. The NuMicro® M251/M252 series integrates high performance analog front -end circuit blocks, such as 16 channels of 12 -bit 880 kSPS ADC, 12 -bit 1 MSPS DAC, analog comparator, operational amplifier, temperature sensor, low voltage reset (LVR) and brow n-out detector (BOD) to enhance product performance, reduce external components and form factor simultaneously. The NuMicro ® M251/M252 series provides 28 product types. The package types of the M251/M252 series include TSSOP20 (4.4mm x 6.5mm) , TSSOP28 (4.4mmx9.7mm), QFN33 (5mm x 5mm) , LQFP48 (7mm x 7mm) , LQFP64 (7mm x 7mm) and LQFP128 (14mm x 14mm).
July 2, 2020 Page 13 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Pin-to-pin compatible in same package makes optimizing product features and performance eas y. Nuvoton NuMaker M251/M252 evaluation boards and Nu -Link debugg er are available for evaluation and product development. 3rd Party IDEs such as Keil MDK, IAR EWARM and Eclippse IDE with GNU GCC compilers, are also supported. Product Line UART I2C QSPI SPI/ I2S PSIO USCI Timer PWM PDMA EBI ADC DAC ACMP OPA USBD M251/M252 3 2 1 1 8 3 4 24 8 1 16 1 2 1 1 Table 1-1 NuMicro® M251/M252 Series Key Features Support Table The NuMicro® M251/M252 series is suitable for a wide range of applications such as: Smart Home / Smart Home Appliance Industrial Control / Industrial Automation Smart City IoT Device Security Alarm System Electronic Payments Communication Modules Portable Wireless Data Collector Smart Door lock Handheld Medical Device (GPS) Location Tracker Electronic Shelf Labels (ESL)
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2 FEATURES
2.1 M251/M252 Series Features
Arm® Cortex® -M23 without TrustZone® Arm® Cortex® -M23 processor, running up to 48 MHz when VDD = 1.75V ~ 5.5V Built-in PMSAv8 Memory Protection Unit (MPU) Built-in Nested Vectored Interrupt Controller (NVIC) 32-bit Single-cycle hardware multiplier and 32-bit 17-cycle hardware divider 24-bit system tick timer Supports Programmble and maskable interrupt Supports Low Power Sleep mode by WFI and WFE instructions Supports single cycle I/O access Supports XOM feature with 1 region Low power mode and current Low Power mode: – Idle mode Power-down mode (PD) – Fast Wake-up Power-down mode (FWPD) – Deep Power-down mode (DPD) Wake-up source and wakeup time USCI, RTC, WDT, I2C, Timer, UART, BOD, LVR, POR, GPIO, USBD, Tamper, ACMP, Debug interface, NMI and Reset pin from Power-down mode or Fast Wake-up Power-down mode RTC, Wake-up Timer, LVR, Wake-up pins, Tamper, from Deep Power-down mode Power supply and low voltage detect Built-in LDO for wide operating voltage from 1.75V to 5.5V Core power voltage: 1.5V Brown-out detector – Supports Brown-out Interrupt and Reset option Low Voltage Reset – Threshold voltage levels: 1.55V Cyclic Redundancy Calculation Unit Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 Programmable order reverse setting for input data and CRC checksum Programmable 1’s complement setting for input data and CRC
July 2, 2020 Page 15 of 266 Rev 1.01 M251/M252 SERIES DATASHEET checksum. Supports 8-/16-/32-bit of data width Programmable seed value 8-bit write mode: 1-AHB clock cycle operation 16-bit write mode: 2-AHB clock cycle operation 32-bit write mode: 4-AHB clock cycle operation Supports using PDMA to write data to perform CRC operation Voltage Adjustable Interface Supports up to 6 VAI pins User Configurable 1.65V ~ 5.5V I/O Interface with a dedicated power input (VDDIO) Supports UART0~1, SPI0~1, I2C0~1, USCI2 and SC0 interface Security 96-bit Unique ID (UID) 128-bit Unique Customer ID (UCID) Memories Flash Up to 256 KB application ROM (APROM) 4 KB Flash for user program loader (LDROM) Up to 48 MHz with zero wait state for consecutive address read access 12 bytes User Configuration Block to control system initiation. 512B page erase for all embedded Flash 32-bit and multi-word Flash programming function. Supports In-System-Programming (ISP), In-Application- Programming (IAP) update embedded Flash memory Supports CRC-32 checksum calculation function Supports Flash all one verification function (hardware can check page erase verify) Hardware external read protection of whole Flash memory by Security Lock Bit Supports XOM feature with 1 region SRAM Up to 32 KB embedded SRAM Supports byte-, half-word- and word-access Supports PDMA mode Peripheral DMA (PDMA) Up to 8 independent configurable channels for automatic data transfer between memories and peripherals Channel 0 to 5 support stride features
July 2, 2020 Page 16 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Channel 0, 1 support time-out function Basic and Scatter-Gather Transfer modes Each channel supports circular buffer management using Scatter- Gather Transfer mode Two types of priorities modes: Fixed-priority and Round-robin modes Transfer data width of 8, 16, and 32 bits Single and burst transfer type Source and destination address can be increment or fixed PDMA transfer count up to 65536 Request source form software, PSIO, SPI/I2S, UART, USCI, EADC, DAC, PWM capture event or TIMER Clocks Clock Source Built-in 4.032 MHz internal high speed RC oscillator (MIRC) for system operation Built-in 48 MHz internal high speed RC oscillator (HIRC) for system operation Built-in 38.4 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-up operation. Built-in 4~32 MHz external high speed crystal oscillator (HXT) for precise timing operation Built-in 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power system operation Supports one PLL up to 100 MHz for high performance system operation, sourced from HIRC and HXT Supports clock on-the-fly switch Supports clock failure detection for high/low speed external crystal oscillator HXT clock frequency accuracy detector Supports exception (NMI) generated once a clock failure detected Supports divided clock output Timers 32-bit Timer TIMER mode 4 sets of 32-bit timers with 24-bit up counters and 8-bit prescale counters Independent clock source for each timer One-shot, Periodic, Toggle and Continuous Counting operation modes Event counting function to count the event from external pin
July 2, 2020 Page 17 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Input capture function to capture or reset counter value External capture pin event for interval measurement. External capture pin event to reset 24-bit up counter. Chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated Timer interrupt flag or external capture interrupt flag to trigger BPWM, PWM, EADC, DAC and PDMA. Internal capture triggered source from ACMP output. Inter-Timer trigger capture mode PWM mode 16-bit compare register and period register Double buffer for period register and compare register Supports inverse in PWM output PWM interrupt wake-up from system Power-down mode BPWM Supports maximum clock frequency up to 96 MHz Each module provides 6 output channels Supports independent mode for BPWM output/Capture input channel Supports 12-bit prescaler from 1 to 4096 Supports 16-bit resolution BPWM counter, each module provides
1 BPWM counter
– Up, down or up/down counter operation type Supports mask function and tri-state enable for each BPWM pin Supports interrupt on the following events: – BPWM counter match 0, period value or compared value Supports trigger ADC on the following events: – BPWM counter match 0, period value or compared value Capture Function Features – Up to 6 capture input channels with 16-bit resolution – Supports rising or falling capture condition – Supports input rising/falling capture interrupt – Supports rising/falling capture with counter reload option PWM Supports maximum clock frequency up to 96 MHz Up to two PWM modules; each module provides 6 output channels. Supports independent mode for PWM output/Capture input channel
July 2, 2020 Page 18 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports complementary mode for 3 complementary paired PWM output channel – Dead-time insertion with 12-bit resolution – Two compared values during one period Supports 12-bit prescaler from 1 to 4096 Supports 16-bit resolution PWM counter – Up, down or up/down counter operation type Supports mask function and tri-state enable for each PWM pin Supports brake function – Brake source from pin and system safety events (clock failed, Brown-out detection and CPU lockup) – Noise filter for brake source from pin – Edge detect brake source to control brake state until brake interrupt cleared – Level detect brake source to auto recover function after brake condition removed Supports interrupt on the following events: – PWM counter match 0, period value or compared value – Brake condition happened Supports trigger ADC on the following events: – PWM counter match 0, period value or compared value Capture Function Features – Up to 12 capture input channels with 16-bit resolution – Supports rising or falling capture condition – Supports input rising/falling capture interrupt – Supports rising/falling capture with counter reload option – Supports PDMA transfer function for all PWM channels Watchdog 20-bit free running up counter for WDT time-out interval Clock sources from LIRC (default), HCLK/2048 or LXT 9 selectable time-out period from 488us ~ 32 sec Able to wake up from Power-down or Idle mode Interrupt or reset selectable on watchdog time-out Selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset delay period Force WDT enabled after chip power on or reset. WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT
July 2, 2020 Page 19 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Window Watchdog Clock sources from HCLK/2048 (default) or LIRC Window set by 6-bit down counter with 11-bit prescaler WWDT counter suspends in Idle/Power-down mode Supports Interrupt RTC Supports external power pin VBAT Software compensation by setting frequency compensate register (FCR),compensated clock accuracy reaches ±5ppm within 5 seconds RTC counter (second, minute, hour) and calendar counter (day, month, year) Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Day of the Week counter Daylight Saving Time software control Periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or 1 second 1 Hz clock output for RTC calibration Wake-up from idle mode and power down mode 32 kHz oscillator gain control RTC Time Tick and Alarm Match interrupt Tamper 20 bytes spare registers and 1 tamper pin to clear the content of these spare registers Selectable spare register erase function Supports Timestamp function Analog Interfaces EADC Conversion results held in 19 data registers with valid and overrun indicators. Analog input voltage: 0~VREF (Max to AVDD). Reference voltage from VREF pin, AVDD or internal VREF 12-bit resolution and 10-bit accuracy guaranteed Up to 16 single-end analog external input channels Supports 3 internal channels: – Band-gap VBG output or Internal voltage reference – Temperature sensor input – VBAT voltage measure (VBAT/4)
July 2, 2020 Page 20 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses. ADC clock frequency up to 16 MHz. Up to 880 kSPS conversion rate. Configurable ADC internal sampling time Up to 19 sample modules – Each of sample module 0~15 which is configurable for ADC converter channel – EADC_CH0~15 and trigger source. – Configurable PDMA – Configured resolution for 12-bit or 16-bit result – Supports Left-adjusted result – Averaging and oversampling (2n times, n=0~8) to support up to 16-bit result – Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT/4). – Configurable sampling time for each sample module. – Conversion results held in 19 data registers with valid and overrun indicators. Supports digital comparator to monitor conversion result that can be under or over the compare register setting Generate an interrupt when conversion result matches the compare register setting. Internal reference voltage source: An A/D conversion can be started by: – Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18) – External pin STADC – Timer0~3 overflow pulse triggers – ADINT0/1 interrupt EOC (End of conversion) pulse triggers – PWM triggers – BPWM triggers Supports PDMA transfer Auto turn on/off ADC power at power down or operation mode with wait state DAC Analog output voltage: 0~AVDD Supports 12-or 8-bit output mode Rail to rail settle time 6us
July 2, 2020 Page 21 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Up to one 12-bit, 1 MSPS voltage type DAC Reference voltage from internal reference voltage or VREF pin Conversion updating rate up to 1 MSPS Supports voltage output buffer mode and bypass voltage output buffer mode Supports software and hardware trigger, including Timer0~3 and external trigger pin to start DAC conversion Supports PDMA mode Analog Comparator (ACMP) Up to two rail-to-rail analog comparators 4 multiplexed I/O pins at positive node Negative node: – One I/O pin – Band-gap (VBG) – DAC0 output – Comparator Reference Voltage (CRV) Programmable propagation speed and low power consumption Interrupts generated when compare results change (Interrupt event condition programmable) Supports Power-down Wake-up Supports triggers for break events and cycle-by-cycle control for PWM Supports window compare mode and window latch mode Supports programmable hysteresis window: – 0 mV, 10 mV, 20 mV or 30 mV OPA Analog input voltage: 0~AVDD. Up to 1 operational amplifier Supports to use schmitt trigger buffer output for simple comparator function Supports schmitt trigger buffer output interrupts. Internal Reference Voltage Internal reference voltage select: 1.536V, 2.048V, 2.560V, 3.072V, 4.096V for EADC, DAC and CRV (comparator reference voltage) reference voltage Communication Interfaces UART Supports up to 3 UARTs: UART0, UART1 and UART2 UART clock source can be from LIRC UART baud rate clock from LXT(32.768 kHz) with 9600bps in Power-down mode
July 2, 2020 Page 22 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Baud rate up to 10 Mbps Full-duplex asynchronous communications Supports one-wire half-duplex communications Separates receive and transmit 16/16 bytes FIFO Programmable receiver buffer trigger level Hardware auto-flow control (CTS and RTS) IrDA (SIR) function – Supports 3/16 bit duration for normal mode RS-485 9-bit mode and direction control UART0 supports LIN function – LIN master/slave mode – Programmable break generation function for transmitter – Break detection function for receiver Programmable baud-rate generator up to 1/16 system clock 8-bit receiver FIFO time-out detection function Programmable transmitting data delay time between the last stop and the next start bit Auto-Baud Rate measurement and baud rate compensation function Break error, frame error, parity error and receive/transmit FIFO overflow detection function Supports RS-485 mode: – RS-485 9-bit mode – Hardware or software enables to program nRTS pin to control RS-485 transmission direction – nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function in Power-down mode. – Hardware or software enables to program nRTS pin to control RS-485 transmission direction Fully programmable serial-interface: – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports PDMA mode Smart Card Interface Smart card mode ISO 7816-3 T = 0, T = 1 compliant EMV2000 compliant
July 2, 2020 Page 23 of 266 Rev 1.01 M251/M252 SERIES DATASHEET One ISO 7816-3 port Separates receive/transmit 4 byte entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 267 ETU) One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times processing Supports auto direct / inverse convention function Supports transmitter and receiver error retry and error number limiting function Supports hardware activation sequence process, and the time between PWR on and CLK start is configurable Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when the card removal is detected UART mode Full duplex, asynchronous communications Separates receiving / transmitting 4 bytes entry FIFO for data payloads Supports programmable baud rate generator Supports programmable receiver buffer trigger level Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion Programmable even, odd or no parity bit generation and detection Programmable stop bit, 1- or 2- stop bit generation SPI Supports Master or Slave mode operation Master and slave mode up to 25 MHz (when chip works at VDD = 3.0 ~ 5.5V) Supports 2-bit Transfer mode Supports Dual and Quad I/O Transfer mode Configurable bit length of a transaction word from 8 to 32-bit Provides separate 8-level depth transmit and receive FIFO buffers Supports MSB first or LSB first transfer sequence Supports Byte Reorder function Supports Byte or Word Suspend mode Supports PDMA transfer Supports 3-Wire, no slave selection signal, bi-direction interface
July 2, 2020 Page 24 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports one data channel half-duplex transfer Supports receive-only mode I2C Up to 2 sets of I2C devices Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) 7-bit and 10-bit addressing mode Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows Programmable clocks allow versatile rate control Multiple address recognition (four slave address with mask option) Supports setup/hold time programmable Supports SMBus and PMBus Multi-address Power-down wake-up function Supports PDMA transfer SPI/I2S SPI Mode Up to 1 set of SPI controller Master or Slave mode operation Configurable bit length of a transfer word from 8 to 32-bit Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers which depended on SPI setting of data width MSB first or LSB first transfer sequence Supports byte reorder function Byte or Word Suspend mode Master and slave mode up to 25 MHz (VDD = 3.0V ~5.5V) Supports one data channel half-duplex transfer Supports receive-only mode Supports PDMA transfer I2S Mode
July 2, 2020 Page 25 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Up to 1 sets of I2S by SPI controllers Interface with external audio CODEC Supports Master and Slave mode Capable of handling 8-, 16-, 24- and 32-bit word sizes Mono and stereo audio data PCM mode A, PCM mode B, I2S and MSB justified data format Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Each supports two PDMA requests, one for transmitting and the other for receiving Universal Serial Control Interface (USCI) Up to 3 sets of USCI: USCI0, USCI1 and USCI2 Supports UART, SPI and I2C function Single byte TX and RX buffer mode USCI_UART One transmit buffer and two receive buffer for data payload Hardware auto flow control function and programmable flow control trigger level Programmable baud-rate generator Supports 9-bit data transfer Baud rate detection by built-in capture event of baud rate generator Supports Wake-up function (Data and nCTS Wakeup Only) Supports PDMA transfer USCI_SPI Master or Slave mode operation Configurable bit length of a transfer word from 4 to 16-bit One transmit buffer and two receive buffer for data payload MSB first or LSB first transfer sequence Word suspend function Supports PDMA transfer Supports 3-wire, no slave select signal, bi-direction interface Wake-up function: input slave select transition Supports one data channel half-duplex transfer USCI_I2C Full master and slave device capability
July 2, 2020 Page 26 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 7-bit/10-bit addressing mode Communication in Standard mode (100 kbps), Fast mode (up to 400 kbps) and Fast mode plus (1 Mbps) Multi-master bus One transmit buffer and two receive buffer for data payload 10-bit bus time out capability Supports Bus monitor mode Wake-up by data toggle or address match in Power-down mode Multiple address recognition Setup/hold time programmable External Bus Interface (EBI) Supports up to three memory banks Supports dedicated external chip select pin with polarity control for each bank Accessible space up to 1 Mbytes for each bank Byte write in 16-bit data width mode Address/Data multiplexed and separate mode Timing parameters individual adjustment for each memory block Supports LCD interface i80 mode Supports Continuous Data Access mode Supports PDMA mode GPIO Four I/O modes: – Quasi bi-direction – Push-Pull output – Open-Drain output – Input only with high impendence TTL/Schmitt trigger input selectable I/O pin configured as interrupt source with edge/level trigger setting Independent pull-up/pull-down control High driver and high sink current I/O (up to 16 mA at 5V, 25°C) Minimum I/O Speed – 25 MHz when VDD = 2.7 ~ 5.5 V (-40°C ~ +105°C, CL=35p, high skew rate enabled) – 10 MHz when VDD = 1.75 ~ 5.5 V (-40°C ~ +105°C, CL=35p, high skew rate enabled) Software selectable slew rate control
July 2, 2020 Page 27 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports wake-up function Supports I/O de-bounce with LIRC at power down I/O configurations of multi-function pin are controlled by module or MFOS register settings. PSIO Supports up to 8 PSIO pins, from PSIO pin0 to PSIO pin7 Supports 6 clock source selections: HXT, LXT, HIRC, LIRC, PLL, or PCLK1 Supports one clock divider, which can be divided from 1 to 255 Supports slot controller for timing sequence control – Supports 4 slot controllers, 8 slots in each slot controller – Supports counting from 1 PSIO clock to 15 PSIO clocks in each slot – Supports 3 slot repeat modes Normal repeat mode Normal repeat mode with infinity loops Whole repeat mode – Supports 4 slot trigger conditions Triggered by software Triggered by falling edge Triggered by rising edge Triggered by rising edge or falling edge Supports PSIO PIN for pin state control Supports 8 check points to connect with slots in each pin Supports 8 check point actions in each check point. Supports 7 kinds of check point action to setting – Output high – Output low – Output data – Output toggle – Input data – Input status – Input status update Supports 4 I/O modes: input, output, open-drain, and quasi Supports switch I/O mode in different check points Supports 4 kinds of Interrupt trigger conditions: – Two sets of configurable slot interrupt controllers – Mismatch interrupt when PSIO is enabled with PDMA
July 2, 2020 Page 28 of 266 Rev 1.01 M251/M252 SERIES DATASHEET – Transfer Error interrupt – Slot controller counting done interrupt Supports PDMA function Advanced Connectivity USB 2.0 Full Speed Compliant with USB 2.0 Full-Speed specification Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB and BUS) Suspend function when no bus activity exists for 3 ms Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 1024 bytes buffer size Provides remote wake-up capability Start of Frame (SOF) locked clock pulse generation Supports USB 2.0 Link Power Management (LPM) Supports Crystal-less function
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3 PARTS INFORMATION
3.1 Package Type
Part No. TSSOP20 TSSOP28 QFN33 LQFP48 LQFP64 LQFP128 M251xC M251FC2AE M251EC2AE M251ZC2AE M251LC2AE M251SC2AE M251xD M251ZD2AE M251LD2AE M251SD2AE M251xE M251LE3AE M251SE3AE M251KE3AE M251xG M251LG6AE M251SG6AE M251KG6AE M252xC M252FC2AE M252EC2AE M252ZC2AE M252LC2AE M252SC2AE M252xD M252ZD2AE M252LD2AE M252SD2AE M252xE M252LE3AE M252SE3AE M252KE3AE M252xG M252LG6AE M252SG6AE M252KG6AE
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3.2 M251/M252 Series Selection Guide
3.2.1 M251 Base Series (M251Fx / M0251Ex / M0251Zx)
Flash (KB) 32 32 32 64 SRAM (KB) 8 8 8 12 LDROM (KB) 4 PLL ( MHz) - - - 96 LXT - - √ √ I/O 15 23 26 26 32-bit Timer/PWM 4 PWM 9 11 12 12 BPWM - - - 12 WDT/WWDT √ RTC - - √ √ Connectivity USCI 1 1 1 2 UART 2 2 2 3 QSPI 1 SPI /I2S - - - 1 I2C 2 SC/UART 1 EBI - PSIO - - - 4 12-bit ADC 7 9 10 10 ACMP - - - 2 DAC - OPA - PDMA 5 Tamper - VAI - - √ √ VBAT pin - Internal VREF -
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3.2.2 M251 Base Series (M251Lx)
Flash (KB) 32 64 128 256 SRAM (KB) 8 12 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 41 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 2 2 3 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI - - √ √ PSIO 4 4 8 8 12-bit ADC 12 ACMP 2 DAC - - - 1 OPA - - - 1 PDMA 5 5 8 8 Tamper - VAI √ VBAT pin - Internal VREF -
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3.2.3 M251 Base Series (M251Sx)
Flash (KB) 32 64 128 256 SRAM (KB) 8 12 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 54 54 53 53 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 2 2 3 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI - - √ √ PSIO 4 4 8 8 12-bit ADC 16 ACMP 2 DAC - - - 1 OPA - - - 1 PDMA 5 5 8 8 Tamper √ VAI √ VBAT pin - - √ √ Internal VREF √
July 2, 2020 Page 34 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.4 M251 Base Series (M251Kx)
Flash (KB) 128 256 SRAM (KB) 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 85 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI √ PSIO 8 12-bit ADC 16 ACMP 2 DAC - 1 OPA - 1 PDMA 8 Tamper √ VAI √ VBAT pin √ Internal VREF √
July 2, 2020 Page 35 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.5 M252 USB Series (M252Fx / M0252Ex / M0252Zx)
Flash (KB) 32 32 32 64 SRAM (KB) 8 8 8 12 LDROM (KB) 4 PLL ( MHz) - - - 96 LXT - - √ √ I/O 11 19 22 22 32-bit Timer/PWM 4 PWM 7 11 12 12 BPWM - - - 8 WDT/WWDT √ RTC - - √ √ Connectivity USCI 1 1 1 2 UART 2 2 2 3 QSPI 1 SPI /I2S - - - 1 I2C 2 SC/UART 1 EBI - PSIO - - - 4 12-bit ADC 3 9 10 10 ACMP - - - 2 DAC - OPA - PDMA 5 Tamper - VAI - - √ √ VBAT pin - Internal VREF -
July 2, 2020 Page 36 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
July 2, 2020 Page 37 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.6 M252 USB Series (M252Lx)
Flash (KB) 32 64 128 256 SRAM (KB) 8 12 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 37 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 2 2 3 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI - - √ √ PSIO 4 4 8 8 12-bit ADC 12 ACMP 2 DAC - - - 1 OPA - - - 1 PDMA 5 5 8 8 Tamper - VAI √ VBAT pin - Internal VREF -
July 2, 2020 Page 38 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.7 M252 USB Series (M252Sx)
Flash (KB) 32 64 128 256 SRAM (KB) 8 12 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 50 50 49 49 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 2 2 3 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI - - √ √ PSIO 4 4 8 8 12-bit ADC 16 ACMP 2 DAC - - - 1 OPA - - - 1 PDMA 5 5 8 8 Tamper √ VAI √ VBAT pin - - √ √ Internal VREF √
July 2, 2020 Page 39 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.8 M252 USB Series (M252Kx)
Flash (KB) 128 256 SRAM (KB) 16 32 LDROM (KB) 4 PLL ( MHz) 96 LXT √ I/O 81 32-bit Timer/PWM 4 PWM 12 BPWM 12 WDT/WWDT √ RTC √ Connectivity USCI 3 UART 3 QSPI 1 SPI /I2S 1 I2C 2 SC/UART 1 EBI √ PSIO 8 12-bit ADC 16 ACMP 2 DAC - 1 OPA - 1 PDMA 8 Tamper √ VAI √ VBAT pin √ Internal VREF √
July 2, 2020 Page 40 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
3.2.9 Naming Rule
Core Line Package Flash SRAM Reserve Temperature Cortex®-M23 51: Control 52: USB F: TSSOP20 (4.4x6.5 mm) E: TSSOP28 (4.4x9.7 mm) Z: QFN33 (5x5 mm) L: LQFP48 (7x7 mm) S: LQFP64 (7x7 mm) K: LQFP128 (14x14 mm) C: 32 KB D: 64 KB E: 128 KB G: 256 KB 2: 8/12 KB 3: 16 KB 6: 32 KB E: -40℃ ~ +105℃
July 2, 2020 Page 41 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4 PIN CONFIGURATION
Users can find pin configuration information in chapter 4 or by using NuTool - PinConfig. The NuTool - PinConfigure contains all NuMicro ® Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1 M251 Series Pin Diagram
4.1.1.1 M251 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M251FC2AE TSSOP20 VSS LDO_CAP VDD PB.14 PB.13 PB.12 AVDD PB.5 PB.4 PB.3 PF.1 PF.0 nRESET PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 PB.2 Figure 4.1-1 M251 Series TSSOP 20-pin Diagram
4.1.1.2 M251 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M251EC2AE TSSOP28 PA.12 PA.13 PA.14 PA.15 VSS LDO_CAP VDD PB.14 PB.13 PB.12 AVDD PB.5 PB.4 PB.3 PC.0 PC.1 PF.1 PF.0 nRESET PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 PB.0 PB.1 PB.2 Figure 4.1-2 M251 Series TSSOP 28-pin Diagram
July 2, 2020 Page 42 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.1.3 M251 Series QFN 33-Pin Diagram
Corresponding Part Number: M251ZC2AE, M251ZD2AE QFN33
33 VSS
LDO_CAP VDD PB.15 PB.14 PB.13 PB.12 AVDD PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PF.5 PF.4 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 PA.15 PA.14 PA.13 PA.12 PC.0 PC.1 PF.1 PF.0 Top transparent view Figure 4.1-3 M251 Series QFN 33-pin Diagram
July 2, 2020 Page 43 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.1.4 M251 Series LQFP 48-Pin Diagram
Corresponding Part Number: M251LC2AE, M251LD2AE, M251LE3AE, M251LG6AE LQFP48 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.5 PF.4 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PA.6 PA.7 PF.2 PF.3 PA.15 PA.14 PA.13 PA.12 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD AVSS PB.7 PB.6 Figure 4.1-4 M251 Series LQFP 48-pin Diagram
July 2, 2020 Page 44 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.1.5 M251 Series LQFP 64-Pin Diagram
Corresponding Part Number: M251SC2AE, M251SD2AE, M251SE3AE, M251SG6AE LQFP64 PB.6 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.6 PF.14 PF.5 PF.4 PF.3 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PF.2 PA.15 PA.14 PA.13 PA.12 PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 Figure 4.1-5 M251 Series LQFP 64-pin Diagram without VBAT
July 2, 2020 Page 45 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M251SG6AE, M251SE3AE LQFP64 PB.6 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.6 VBAT PF.5 PF.4 PF.3 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PF.2 PA.15 PA.14 PA.13 PA.12 PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 Figure 4.1-6 M251 Series LQFP 64-pin Diagram with VBAT
July 2, 2020 Page 46 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.1.6 M251 Series LQFP 128-Pin Diagram
Corresponding Part Number: M251KE3AE, M251KG6AE LQFP128 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PB.5 PB.4 PB.3 PB.2 PC.12 PC.11 PC.10 PC.9 PB.1 PB.0 VSS VDD PA.11 PA.10 PA.9 PA.8 NC PD.12 PD.11 PD.10 NC NC NC NC NC NC NC PF.7 PF.6 VBAT PF.5 PF.4 nRESET PE.15 PE.14 VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PC.8 PE.13 PE.12 PE.11 PE.10 PE.9 PE.8 NC NC PF.2 PF.3 NC NC NC NC PA.15 PA.14 PA.13 PA.12 PD.13 PD.0 PD.1 PD.2 PD.3 PD.4 PD.5 PD.6 PD.7 NC NC NC NC NC NC NC VDD VSS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PD.8 PD.9 PF.1 PF.0 PE.7 PE.6 PE.5 PE.4 PE.3 PE.2 NC NC PE.1 PE.0 NC NC NC NC NC VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 PB.6 Figure 4.1-7 M251 Series LQFP 128-pin Diagram
July 2, 2020 Page 47 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.2 M251 Series Multi-function Pin Diagram
4.1.2.1 M251 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M251FC2AE M251FC2AE TSSOP20 VSS LDO_CAP VDD CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5 INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3 Figure 4.1-8 M251FC2AE Multi-function Pin Diagram Pin M251FC2AE Pin Function
1 VSS
2 LDO_CAP
3 VDD
4 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 5 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 6 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
7 AVDD
8 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0 9 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1 10 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2 11 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3 12 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 13 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT 14 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 15 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 16 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 17 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
July 2, 2020 Page 48 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Table 4.1-1 M251FC2AE Multi-function Pin Table
4.1.2.2 M251 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M251EC2AE M251EC2AE TSSOP28 I2C1_SCL / PA.12 I2C1_SDA / PA.13 UART0_TXD / PA.14 UART0_RXD / PA.15 VSS LDO_CAP VDD CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5 INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3 PC.0 / I2C0_SDA / PWM1_CH5 PC.1 / I2C0_SCL / PWM1_CH4 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN PB.0 / EADC0_CH0 / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 PB.1 / EADC0_CH1 / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3 Figure 4.1-9 M251EC2AE Multi-function Pin Diagram Pin M251EC2AE Pin Function 1 PA.12/I2C1_SCL 2 PA.13/I2C1_SDA 3 PA.14/UART0_TXD 4 PA.15/UART0_RXD
5 VSS
6 LDO_CAP
7 VDD
8 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 9 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 10 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
11 AVDD
12 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0 13 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1 14 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2 15 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3 16 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 17 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1 18 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 19 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
July 2, 2020 Page 49 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 20 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 21 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 22 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 23 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4 28 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5 Table 4.1-2 M251EC2AE Multi-function Pin Table
July 2, 2020 Page 50 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.2.3 M251 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M251ZC2AE M251ZC2AE QFN33 LDO_CAP VDD PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5 INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / UART1_RXD / I2C1_SDA / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / EADC0_CH0 / PB.0 EADC0_ST / X32_IN / PWM0_CH0 / PF.5 X32_OUT / PWM0_CH1 / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / QSPI0_MISO0 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / QSPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / QSPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN PA.15 / UART0_RXD PA.14 / UART0_TXD PA.13 / I2C1_SDA PA.12 / I2C1_SCL PC.0 / QSPI0_MOSI0 / I2C0_SDA / PWM1_CH5 PC.1 / QSPI0_MISO0 / I2C0_SCL / PWM1_CH4 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT Top transparent view Figure 4.1-10 M251ZC2AE Multi-function Pin Diagram Pin M251ZC2AE Pin Function 1 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0 2 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1 3 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
July 2, 2020 Page 51 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 5 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1 7 PF.5/PWM0_CH0/X32_IN/EADC0_ST 8 PF.4/PWM0_CH1/X32_OUT 9 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT 11 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 12 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 13 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 14 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
15 VDDIO
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 19 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4 20 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5 21 PA.12/I2C1_SCL 22 PA.13/I2C1_SDA 23 PA.14/UART0_TXD 24 PA.15/UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15/EADC0_CH15/USCI0_CTL1/UART0_nCTS/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 29 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 30 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 31 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
32 AVDD
Table 4.1-3 M251ZC2AE Multi-function Pin Table
July 2, 2020 Page 52 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M251ZD2AE QFN33 LDO_CAP VDD PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / I2C1_SDA / BPWM1_CH3 PA.12 / I2C1_SCL / BPWM1_CH2 PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT Top transparent view Figure 4.1-11 M251ZD2AE Function Pin Diagram Pin M251ZD2AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN 4 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 5 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
July 2, 2020 Page 53 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 7 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 8 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 9 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 11 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 12 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 13 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 14 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 19 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 20 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O 21 PA.12/I2C1_SCL/BPWM1_CH2 22 PA.13/I2C1_SDA/BPWM1_CH3 23 PA.14/UART0_TXD/BPWM1_CH4 24 PA.15/UART0_RXD/BPWM1_CH5 28 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 29 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 30 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 31 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT Table 4.1-4 M251ZD2AE Multi-function Pin Table
July 2, 2020 Page 54 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.2.4 M251 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M251LC2AE, M251LD2AE, M251LE3AE, M251LG6AE M251LC2AE / M251LD2AE LQFP48 INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / I2C1_SDA / BPWM1_CH3 PA.12 / I2C1_SCL / BPWM1_CH2 PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / PSIO0_CH3 PC.3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / PSIO0_CH2 PC.4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / PSIO0_CH1 PC.5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / UART1_TXD / USCI1_DAT0 / EADC0_CH7 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / UART1_RXD / USCI1_DAT1 / EADC0_CH6 / PB.6 Figure 4.1-12 M251LC2AE/M251LD2AE Multi-function Pin Diagram Pin M251LC2AE/M251LD2AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
July 2, 2020 Page 55 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 5 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE 7 PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT 9 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
23 VDDIO
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1 29 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2 30 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3 31 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 32 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O 33 PA.12/I2C1_SCL/BPWM1_CH2 34 PA.13/I2C1_SDA/BPWM1_CH3 35 PA.14/UART0_TXD/BPWM1_CH4
July 2, 2020 Page 56 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 36 PA.15/UART0_RXD/BPWM1_CH5
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1 41 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 42 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 44 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT
45 AVDD
46 AVSS
47 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O 48 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O Table 4.1-5 M251LC2AE/M251LD2AE Multi-function Pin Table
July 2, 2020 Page 57 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251LE3AE LQFP48 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-13 M251LE3AE Multi-function Pin Diagram Pin M251LE3AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH 7/TM3/INT3
July 2, 2020 Page 58 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 5 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 6 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1 7 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 9 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 33 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 34 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
July 2, 2020 Page 59 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 35 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 36 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 41 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 44 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT 47 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 48 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-6 M251LE3AE Multi-function Pin Table
July 2, 2020 Page 60 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251LG6AE LQFP48 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / Analog11 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-14 M251LG6AE Multi-function Pin Diagram Pin M251LG6AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P SIO0_CH7/TM3/INT3
July 2, 2020 Page 61 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 5 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 7 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 9 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 33 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 34 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
July 2, 2020 Page 62 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 35 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 36 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 41 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 44 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 47 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 48 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-7 M251LG6AE Multi-function Pin Table
July 2, 2020 Page 63 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.2.5 M251 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M251SC2AE, M251SD2AE, M251SE3AE, M251SG6AE M251SC2AE / M251SD2AE LQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / UART1_RXD / USCI1_DAT1 / EADC0_CH6 / PB.6 INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / PA.8 TAMPER0 / SPI0_MOSI / SC0_CLK / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PSIO0_CH3 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PA.15 / UART0_RXD / BPWM1_CH5 PA.14 / UART0_TXD / BPWM1_CH4 PA.13 / I2C1_SDA / BPWM1_CH3 PA.12 / I2C1_SCL / BPWM1_CH2 PD.0 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / USCI0_DAT0 / SPI0_MISO PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / PSIO0_CH3 PC.3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / PSIO0_CH2 PC.4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / PSIO0_CH1 PC.5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EADC0_CH11 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EADC0_CH10 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EADC0_CH9 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EADC0_CH8 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / UART1_TXD / USCI1_DAT0 / EADC0_CH7 / PB.7 Figure 4.1-15 M251SC2AE/M251SD2AE Multi-function Pin Diagram Pin M251SC2AE/M251SD2AE Pin Function 1 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
July 2, 2020 Page 64 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN 5 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 6 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 7 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE 8 PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT 10 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/SC0_CLK/SPI0_MOSI/TAMPER0 13 PF.14/PWM1_BRAKE0/PWM0_BRAKE0/PSIO0_CH3/PWM0_CH4/CLKO/TM3/INT5 14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
31 VDDIO
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020 Page 65 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 36 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1 37 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2 38 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3 39 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 40 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O 41 PD.3/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/USCI0_DAT0/SPI0_MISO 44 PD.0/USCI0_CLK/SPI0_MOSI/TM2 45 PA.12/I2C1_SCL/BPWM1_CH2 46 PA.13/I2C1_SDA/BPWM1_CH3 47 PA.14/UART0_TXD/BPWM1_CH4 48 PA.15/UART0_RXD/BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1 53 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 54 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 56 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O Table 4.1-8 M251SC2AE/M251SD2AE Multi-function Pin Table
July 2, 2020 Page 66 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251SE3AE LQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 Figure 4.1-16 M251SE3AE Multi-function Pin Diagram Pin M251SE3AE Pin Function 1 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 4 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020 Page 67 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PWM0_BRAKE0/TM2/INT2 5 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH 7/TM3/INT3 6 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 7 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1 8 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
13 VBAT
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020 Page 68 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 45 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 46 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3 47 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 48 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 53 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 56 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT 60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O Table 4.1-9 M251SE3AE Multi-function Pin Table
July 2, 2020 Page 69 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
July 2, 2020 Page 70 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251SG6AE LQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 Figure 4.1-17 M251SG6AE Multi-function Pin Diagram Pin M251SG6AE Pin Function 1 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 4 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020 Page 71 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PWM0_BRAKE0/TM2/INT2 5 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P SIO0_CH7/TM3/INT3 6 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 7 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 8 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020 Page 72 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 45 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 46 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3 47 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 48 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 53 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 56 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O Table 4.1-10 M251SG6AE Multi-function Pin Table
July 2, 2020 Page 73 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
July 2, 2020 Page 74 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.2.6 M251 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M251KE3AE, M251KG3AE M251KE3AE LQFP128 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 ACMP0_O / PWM1_CH0 / SC0_nCD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 PWM1_CH2 / EBI_ADR6 / PC.10 PWM1_CH3 / EBI_ADR7 / PC.9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 VSS VDD TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 NC INT5 / EADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART1_TXD / EBI_nCS1 / PD.11 UART1_RXD / EBI_nCS2 / PD.10 NC NC NC NC NC NC NC SPI0_MISO / SC0_DAT / EBI_ADR18 / PF.7 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET PE.15 / EBI_AD9 / UART2_RXD / PSIO0_CH1 PE.14 / EBI_AD8 / UART2_TXD / PSIO0_CH0 VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PC.8 / EBI_ADR16 / I2C0_SDA / UART1_RXD / PWM1_CH1 / BPWM1_CH4 PE.13 / EBI_ADR15 / I2C0_SCL / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 PE.10 / EBI_ADR12 / USCI1_DAT0 / PWM0_CH2 / PWM1_BRAKE0 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 NC NC PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 NC NC NC NC PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PD.13 / EBI_AD10 / SPI0_I2SMCLK / USCI2_CTL0 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 / PSIO0_CH7 PD.5 / I2C1_SCL / USCI1_DAT0 / PSIO0_CH6 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 / PSIO0_CH5 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK / PSIO0_CH4 NC NC NC NC NC NC NC VDD VSS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PD.8 / EBI_AD6 / UART2_nRTS / PSIO0_CH3 PD.9 / EBI_AD7 / UART2_nCTS / PSIO0_CH2 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT BPWM0_CH5 / PWM0_CH0 / PSIO0_CH0 / PE.7 BPWM0_CH4 / PWM0_CH1 / PSIO0_CH1 / USCI0_CTL0 / SC0_nCD / PE.6 BPWM0_CH3 / PWM0_CH2 / PSIO0_CH2 / USCI0_CTL1 / SC0_PWR / EBI_nRD / PE.5 BPWM0_CH2 / PWM0_CH3 / PSIO0_CH3 / USCI0_DAT1 / SC0_RST / EBI_nWR / PE.4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / SC0_DAT / EBI_MCLK / PE.3 BPWM0_CH0 / PWM0_CH5 / USCI2_CTL0 / USCI0_CLK / SC0_CLK / EBI_ALE / PE.2 NC NC USCI2_DAT1 / I2C1_SCL / QSPI0_MISO0 / EBI_AD10 / PE.1 USCI2_DAT0 / I2C1_SDA / QSPI0_MOSI0 / EBI_AD11 / PE.0 NC NC NC NC NC VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-18 M251KE3AE Multi-function Pin Diagram Pin M251KE3AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1
July 2, 2020 Page 75 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH 7/TM3/INT3 5 PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O 6 PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O 7 PC.10/EBI_ADR6/PWM1_CH2 8 PC.9/EBI_ADR7/PWM1_CH3 9 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 10 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1
11 VSS
12 VDD
13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 17 NC 18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5 19 PD.11/EBI_nCS1/UART1_TXD 20 PD.10/EBI_nCS2/UART1_RXD 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO 29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
30 VBAT
31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 33 NC 34 NC 35 NC 36 NC
July 2, 2020 Page 76 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 39 NC 40 NC 41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0 42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1 43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0 44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1 45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4 46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5 47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4 48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
52 VSS
53 VDD
54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 56 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 57 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 58 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 59 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 60 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5
61 VDDIO
62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0 63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
July 2, 2020 Page 77 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3 69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
75 VSS
76 VDD
84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4 85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5 86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6 87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7 88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0 93 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 94 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3 95 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 96 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5 98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4 99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3 100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2 101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1 102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0 103 NC
July 2, 2020 Page 78 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 104 NC 105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1 106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0 107 NC 108 NC 109 NC 110 NC 111 NC
112 VSS
113 LDO_CAP
114 VDD
115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 116 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 118 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 119 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 127 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 128 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-11 M251KE3AE Multi-function Pin Table
July 2, 2020 Page 79 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251KG6AE LQFP100 100 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 ACMP0_O / PWM1_CH0 / SC0_nCD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 PWM1_CH2 / EBI_ADR6 / PC.10 PWM1_CH3 / EBI_ADR7 / PC.9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / Analog5 / PB.0 VSS VDD TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 INT5 / EADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART1_TXD / EBI_nCS1 / PD.11 UART1_RXD / EBI_nCS2 / PD.10 SPI0_MISO / SC0_DAT / EBI_ADR18 / PF.7 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 nRESET PE.15 / EBI_AD9 / UART2_RXD / PSIO0_CH1 PE.14 / EBI_AD8 / UART2_TXD / PSIO0_CH0 VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PC.8 / EBI_ADR16 / I2C0_SDA / UART1_RXD / PWM1_CH1 / BPWM1_CH4 PE.13 / EBI_ADR15 / I2C0_SCL / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 PE.10 / EBI_ADR12 / USCI1_DAT0 / PWM0_CH2 / PWM1_BRAKE0 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PA.15 / UART0_RXD / USCI2_CTL1 / PSIO0_CH7 / BPWM1_CH5 PA.14 / UART0_TXD / USCI2_CLK / PSIO0_CH6 / BPWM1_CH4 PA.13 / I2C1_SDA / USCI2_DAT0 / PSIO0_CH5 / BPWM1_CH3 PA.12 / I2C1_SCL / USCI2_DAT1 / PSIO0_CH4 / BPWM1_CH2 PD.13 / EBI_AD10 / SPI0_I2SMCLK / USCI2_CTL0 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 / PSIO0_CH7 PD.5 / I2C1_SCL / USCI1_DAT0 / PSIO0_CH6 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 / PSIO0_CH5 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK / PSIO0_CH4 VDD VSS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PD.8 / EBI_AD6 / UART2_nRTS / PSIO0_CH3 PD.9 / EBI_AD7 / UART2_nCTS / PSIO0_CH2 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT BPWM0_CH5 / PWM0_CH0 / PSIO0_CH0 / PE.7 BPWM0_CH4 / PWM0_CH1 / PSIO0_CH1 / USCI0_CTL0 / SC0_nCD / PE.6 BPWM0_CH3 / PWM0_CH2 / PSIO0_CH2 / USCI0_CTL1 / SC0_PWR / EBI_nRD / PE.5 BPWM0_CH2 / PWM0_CH3 / PSIO0_CH3 / USCI0_DAT1 / SC0_RST / EBI_nWR / PE.4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / SC0_DAT / EBI_MCLK / PE.3 BPWM0_CH0 / PWM0_CH5 / USCI2_CTL0 / USCI0_CLK / SC0_CLK / EBI_ALE / PE.2 USCI2_DAT1 / I2C1_SCL / QSPI0_MISO0 / EBI_AD10 / PE.1 USCI2_DAT0 / I2C1_SDA / QSPI0_MOSI0 / EBI_AD11 / PE.0 VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-19 M251KG6AE Multi-function Pin Diagram Pin M251KG6AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
July 2, 2020 Page 80 of 266 Rev 1.01 M251/M252 SERIES DATASHEET SIO0_CH7/TM3/INT3 5 PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O 6 PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O 7 PC.10/EBI_ADR6/PWM1_CH2 8 PC.9/EBI_ADR7/PWM1_CH3 9 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 10 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 17 NC 18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5 19 PD.11/EBI_nCS1/UART1_TXD 20 PD.10/EBI_nCS2/UART1_RXD 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO 29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 33 NC 34 NC 35 NC 36 NC 37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
July 2, 2020 Page 81 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 39 NC 40 NC 41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0 42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1 43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0 44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1 45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4 46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5 47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4 48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 56 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 57 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 58 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 59 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 60 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST 62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0 63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2 68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3 69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020 Page 82 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4 85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5 86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6 87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7 88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0 93 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2 94 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3 95 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4 96 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5 97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5 98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4 99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3 100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2 101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1 102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0 103 NC 104 NC 105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1
July 2, 2020 Page 83 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0 107 NC 108 NC 109 NC 110 NC 111 NC 115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 116 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 118 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 119 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 127 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 128 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-12 M251KG6AE Multi-function Pin Table
July 2, 2020 Page 84 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.3 M252 Series Pin Diagram
4.1.3.1 M252 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M252FC2AE TSSOP20 USB_D- USB_D+ USB_VDD33_CAP VSS LDO_CAP VDD PB.14 PB.13 PB.12 AVDD USB_VBUS PF.1 PF.0 nRESET PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 Figure 4.1-20 M252 Series TSSOP 20-pin Diagram
4.1.3.2 M252 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M252EC2AE TSSOP28 USB_VBUS USB_D- USB_D+ USB_VDD33_CAP VSS LDO_CAP VDD PB.14 PB.13 PB.12 AVDD PB.5 PB.4 PB.3 PC.0 PC.1 PF.1 PF.0 nRESET PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 PB.0 PB.1 PB.2 Figure 4.1-21 M252 Series TSSOP 28-pin Diagram
July 2, 2020 Page 85 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.3.3 M252 Series QFN 33-Pin Diagram
Corresponding Part Number: M252ZD2AE, M252ZC2AE QFN33 LDO_CAP VDD PB.15 PB.14 PB.13 PB.12 AVDD PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PF.5 PF.4 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PF.2 PF.3 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 PC.1 PF.1 PF.0 Top transparent view Figure 4.1-22 M252 Series QFN 33-pin Diagram
July 2, 2020 Page 86 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.3.4 M252 Series LQFP 48-Pin Diagram
Corresponding Part Number: M252LG6AE, M252LE3AE, M252LD2AE, M252LC2AE LQFP48 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.5 PF.4 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PA.6 PA.7 PF.2 PF.3 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD AVSS PB.7 PB.6 Figure 4.1-23 M252 Series LQFP 48-pin Diagram
July 2, 2020 Page 87 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.3.5 M252 Series LQFP 64-Pin Diagram
Corresponding Part Number: M252SD2AE, M252SC2AE LQFP64 PB.6 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.6 PF.14 PF.5 PF.4 PF.3 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PF.2 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 Figure 4.1-24 M252 Series LQFP 64-pin Diagram without VBAT
July 2, 2020 Page 88 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M252SG6AE, M252SE3AE LQFP64 PB.6 PB.5 PB.4 PB.3 PB.2 PB.1 PB.0 PA.11 PA.10 PA.9 PA.8 PF.6 VBAT PF.5 PF.4 PF.3 nRESET VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PF.2 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 PD.1 PD.2 PD.3 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PF.1 PF.0 VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 Figure 4.1-25 M252 Series LQFP 64-pin Diagram with VBAT
July 2, 2020 Page 89 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.3.6 M252 Series LQFP 128-Pin Diagram
Corresponding Part Number: M252KG6AE, M252KE3AE ULQFP128 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PB.5 PB.4 PB.3 PB.2 PC.12 PC.11 PC.10 PC.9 PB.1 PB.0 VSS VDD PA.11 PA.10 PA.9 PA.8 NC PD.12 PD.11 PD.10 NC NC NC NC NC NC NC PF.7 PF.6 VBAT PF.5 PF.4 nRESET PE.15 PE.14 VDDIO PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PD.15 VDD VSS PA.6 PA.7 PC.6 PC.7 PC.8 PE.13 PE.12 PE.11 PE.10 PE.9 PE.8 NC NC PF.2 PF.3 NC NC NC NC USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.13 PD.0 PD.1 PD.2 PD.3 PD.4 PD.5 PD.6 PD.7 NC NC NC NC NC NC NC VDD VSS PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 PD.8 PD.9 PF.1 PF.0 PE.7 PE.6 PE.5 PE.4 PE.3 PE.2 NC NC PE.1 PE.0 NC NC NC NC NC VSS LDO_CAP VDD PC.14 PB.15 PB.14 PB.13 PB.12 AVDD VREF AVSS PB.11 PB.10 PB.9 PB.8 PB.7 PB.6 Figure 4.1-26 M252 Series LQFP 128-pin Diagram
July 2, 2020 Page 90 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.4 M252 Series Function Pin Diagram
4.1.4.1 M252 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M252FC2AE M252FC2AE TSSOP20 USB_D- USB_D+ USB_VDD33_CAP VSS LDO_CAP VDD CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD USB_VBUS PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN Figure 4.1-27 M252FC2AE Function Pin Diagram Pin M252FC2AE Pin Function
1 USB_D-
2 USB_D+
3 USB_VDD33_CAP
4 VSS
5 LDO_CAP
6 VDD
7 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 8 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 9 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
10 AVDD
11 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 12 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT 13 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 14 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 15 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 16 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
20 USB_VBUS
July 2, 2020 Page 91 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Table 4.1-13 M252FC2AE Multi-function Pin Table
4.1.4.2 M252 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M252EC2AE M252EC2AE TSSOP28 USB_VBUS USB_D- USB_D+ USB_VDD33_CAP VSS LDO_CAP VDD CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5 INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3 PC.0 / I2C0_SDA / PWM1_CH5 PC.1 / I2C0_SCL / PWM1_CH4 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT nRESET PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN PB.0 / EADC0_CH0 / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1 PB.1 / EADC0_CH1 / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0 PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3 Figure 4.1-28 M252EC2AE Function Pin Diagram Pin M252EC2AE Pin Function
1 USB_VBUS
2 USB_D-
3 USB_D+
4 USB_VDD33_CAP
8 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 9 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 10 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT 12 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0 13 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1 14 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2 15 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3 16 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 17 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1 18 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 19 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
July 2, 2020 Page 92 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 20 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 21 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 22 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 23 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4 28 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5 Table 4.1-14 M252EC2AE Multi-function Pin Table
July 2, 2020 Page 93 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.4.3 M252 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M252ZC2AE, M252ZD2AE M252ZC2AE QFN33 LDO_CAP VDD PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5 INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / UART1_RXD / I2C1_SDA / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / EADC0_CH0 / PB.0 EADC0_ST / X32_IN / PWM0_CH0 / PF.5 X32_OUT / PWM0_CH1 / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5 PA.1 / QSPI0_MISO0 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4 PA.2 / QSPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3 PA.3 / QSPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT PF.3 / UART0_TXD / I2C0_SCL / XT1_IN USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / I2C0_SDA / PWM1_CH5 PC.1 / QSPI0_MISO0 / I2C0_SCL / PWM1_CH4 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT Top transparent view Figure 4.1-29 M252ZC2AE Function Pin Diagram Pin M252ZC2AE Pin Function 1 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0 2 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1 3 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
July 2, 2020 Page 94 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3 5 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1 7 PF.5/PWM0_CH0/X32_IN/EADC0_ST 8 PF.4/PWM0_CH1/X32_OUT 9 PF.3/UART0_TXD/I2C0_SCL/XT1_IN 10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT 11 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1 12 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3 13 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4 14 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 19 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4 20 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5
21 USB_VBUS
22 USB_D-
23 USB_D+
24 USB_VDD33_CAP
28 PB.15/EADC0_CH15/USCI0_CTL1/UART0_nCTS/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 29 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO 30 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT 31 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT Table 4.1-15 M252ZC2AE Multi-function Pin Table
July 2, 2020 Page 95 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M252ZD2AE UQFN33 LDO_CAP VDD PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT Top transparent view Figure 4.1-30 M252ZD2A Function Pin Diagram Pin M252ZD2AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN 4 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 5 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
July 2, 2020 Page 96 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 7 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 8 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 9 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 11 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 12 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 13 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 14 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 19 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 20 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O 28 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 29 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 30 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 31 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT Table 4.1-16 M252ZD2AE Multi-function Pin Table
July 2, 2020 Page 97 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
July 2, 2020 Page 98 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.4.4 M252 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M252LC2AE, M252LD2AE, M252LE3AE, M252LG6AE M252LC2AE / M252LD2AE LQFP48 INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / PSIO0_CH3 PC.3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / PSIO0_CH2 PC.4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / PSIO0_CH1 PC.5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / UART1_TXD / USCI1_DAT0 / EADC0_CH7 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / UART1_RXD / USCI1_DAT1 / EADC0_CH6 / PB.6 Figure 4.1-31 M252LC2AE/M252LD2AE Function Pin Diagram Pin M252LC2AE/M252LD2AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
July 2, 2020 Page 99 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 5 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE 7 PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT 9 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1 29 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2 30 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3 31 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 32 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
33 USB_VBUS
34 USB_D-
35 USB_D+
July 2, 2020 Page 100 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
36 USB_VDD33_CAP
40 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1 41 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 42 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 44 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT 47 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O 48 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O Table 4.1-17 M252LC2AE/M252LD2AE Multi-function Pin Table
July 2, 2020 Page 101 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M252LE3AE M252LE3AE ULQFP48 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-32 M252LE3AE Function Pin Diagram Pin M252LE3AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
July 2, 2020 Page 102 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 7/TM3/INT3 5 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 6 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1 7 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 9 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
July 2, 2020 Page 103 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 41 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 44 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT 47 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 48 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-18 M252LE3AE Multi-function Pin Table
July 2, 2020 Page 104 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M252LG6AE M252LG6AE ULQFP48 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / Analog11 / PB.12 AVDD AVSS ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-33 M252LG6AE Function Pin Diagram Pin M252LG6AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2
July 2, 2020 Page 105 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P SIO0_CH7/TM3/INT3 5 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 6 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 7 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 8 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 9 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 19 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
July 2, 2020 Page 106 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 41 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 43 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 44 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 47 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 48 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-19 M252LG6AE Multi-function Pin Table
July 2, 2020 Page 107 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.4.5 M252 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M252SC2AE, M252SD2AE, M252SE3AE, M252SG6AE M252SC2AE / M252SD2AE LQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / UART1_RXD / USCI1_DAT1 / EADC0_CH6 / PB.6 INT0 / TM0 / UART2_TXD / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / ACMP0_P1 / EADC0_CH2 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EADC0_CH0 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / ACMP0_P0 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / PA.8 TAMPER0 / SPI0_MOSI / SC0_CLK / PF.6 INT5 / TM3 / CLKO / PWM0_CH4 / PSIO0_CH3 / PWM0_BRAKE0 / PWM1_BRAKE0 / PF.14 EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / USCI0_DAT0 / SPI0_MISO PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O PC.1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O PC.2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / PSIO0_CH3 PC.3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / PSIO0_CH2 PC.4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / PSIO0_CH1 PC.5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EADC0_CH11 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EADC0_CH10 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EADC0_CH9 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EADC0_CH8 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / UART1_TXD / USCI1_DAT0 / EADC0_CH7 / PB.7 Figure 4.1-34 M252SC2AE/M252SD2AE Function Pin Diagram Pin M252SC2AE/M252SD2AE Pin Function 1 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
July 2, 2020 Page 108 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN 5 PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3 6 PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0 7 PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE 8 PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT 10 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/SC0_CLK/SPI0_MOSI/TAMPER0 13 PF.14/PWM1_BRAKE0/PWM0_BRAKE0/PSIO0_CH3/PWM0_CH4/CLKO/TM3/INT5 14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 24 PD.15/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1 _BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020 Page 109 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 36 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1 37 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2 38 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3 39 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O 40 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O 41 PD.3/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/USCI0_DAT0/SPI0_MISO 44 PD.0/USCI0_CLK/SPI0_MOSI/TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
52 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1 53 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1 54 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_ EXT 56 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_ EXT 60 PB.11/EADC0_CH11/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O Table 4.1-20 M252SC2AE/M252SD2AE Multi-function Pin Table
July 2, 2020 Page 110 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M252SE3AE M252SE3AE ULQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 Figure 4.1-35 M252SE3AE Function Pin Diagram Pin M252SE3AE Pin Function 1 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 4 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020 Page 111 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PWM0_BRAKE0/TM2/INT2 5 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH 7/TM3/INT3 6 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 7 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1 8 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5 Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020 Page 112 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 53 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 56 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT 60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O Table 4.1-21 M252SE3AE Multi-function Pin Table
July 2, 2020 Page 113 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Corresponding Part Number: M252SG6AE M252SG6AE ULQFP64 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / Analog5 / PB.0 TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 BPWM1_CH0 / XT1_IN / I2C0_SCL / UART0_TXD / EBI_nCS0 / PF.3 nRESET VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 Figure 4.1-36 M252SG3AE Function Pin Diagram Pin M252SG6AE Pin Function 1 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O 2 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 3 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1
July 2, 2020 Page 114 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 5 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P SIO0_CH7/TM3/INT3 6 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 7 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 8 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 9 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 27 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. 33 PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
July 2, 2020 Page 115 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 53 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 55 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 56 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 64 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O Table 4.1-22 M252SG6AE Multi-function Pin Table
July 2, 2020 Page 116 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.1.4.6 M252 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M252KE3AE, M252KG6AE M252KE3AE LQFP128 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / Analog0 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / Analog1 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / Analog2 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / ACMP0_P1 / EADC0_CH2 / Analog3 / PB.2 ACMP0_O / PWM1_CH0 / SC0_nCD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 PWM1_CH2 / EBI_ADR6 / PC.10 PWM1_CH3 / EBI_ADR7 / PC.9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / EADC0_CH1 / Analog4 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / EADC0_CH0 / Analog5 / PB.0 VSS VDD TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / Analog6 / PA.11 TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / Analog7 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 NC INT5 / EADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART1_TXD / EBI_nCS1 / PD.11 UART1_RXD / EBI_nCS2 / PD.10 NC NC NC NC NC NC NC SPI0_MISO / SC0_DAT / EBI_ADR18 / PF.7 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET PE.15 / EBI_AD9 / UART2_RXD / PSIO0_CH1 PE.14 / EBI_AD8 / UART2_TXD / PSIO0_CH0 VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PC.8 / EBI_ADR16 / I2C0_SDA / UART1_RXD / PWM1_CH1 / BPWM1_CH4 PE.13 / EBI_ADR15 / I2C0_SCL / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 PE.10 / EBI_ADR12 / USCI1_DAT0 / PWM0_CH2 / PWM1_BRAKE0 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 NC NC PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 NC NC NC NC USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.13 / EBI_AD10 / SPI0_I2SMCLK / USCI2_CTL0 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 / PSIO0_CH7 PD.5 / I2C1_SCL / USCI1_DAT0 / PSIO0_CH6 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 / PSIO0_CH5 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK / PSIO0_CH4 NC NC NC NC NC NC NC VDD VSS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PD.8 / EBI_AD6 / UART2_nRTS / PSIO0_CH3 PD.9 / EBI_AD7 / UART2_nCTS / PSIO0_CH2 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT BPWM0_CH5 / PWM0_CH0 / PSIO0_CH0 / PE.7 BPWM0_CH4 / PWM0_CH1 / PSIO0_CH1 / USCI0_CTL0 / SC0_nCD / PE.6 BPWM0_CH3 / PWM0_CH2 / PSIO0_CH2 / USCI0_CTL1 / SC0_PWR / EBI_nRD / PE.5 BPWM0_CH2 / PWM0_CH3 / PSIO0_CH3 / USCI0_DAT1 / SC0_RST / EBI_nWR / PE.4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / SC0_DAT / EBI_MCLK / PE.3 BPWM0_CH0 / PWM0_CH5 / USCI2_CTL0 / USCI0_CLK / SC0_CLK / EBI_ALE / PE.2 NC NC USCI2_DAT1 / I2C1_SCL / QSPI0_MISO0 / EBI_AD10 / PE.1 USCI2_DAT0 / I2C1_SDA / QSPI0_MOSI0 / EBI_AD11 / PE.0 NC NC NC NC NC VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / Analog8 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / Analog9 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / Analog10 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / Analog11 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / Analog12 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / Analog13 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / Analog14 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / Analog15 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / Analog16 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / Analog17 / PB.6 Figure 4.1-37 M252KE3AE Function Pin Diagram Pin M252KE3AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1
July 2, 2020 Page 117 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH 7/TM3/INT3 5 PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O 6 PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O 7 PC.10/EBI_ADR6/PWM1_CH2 8 PC.9/EBI_ADR7/PWM1_CH3 9 PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_ BRAKE0 10 PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW M0_BRAKE1 13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT 15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 17 NC 18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5 19 PD.11/EBI_nCS1/UART1_TXD 20 PD.10/EBI_nCS2/UART1_RXD 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO 29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 33 NC 34 NC 35 NC 36 NC
July 2, 2020 Page 118 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 39 NC 40 NC 41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0 42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1 43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0 44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1 45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4 46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5 47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4 48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 56 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 57 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 58 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 59 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 60 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5 62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0 63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
July 2, 2020 Page 119 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3 69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1 71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4 85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5 86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6 87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7 88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5 98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4 99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3 100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2 101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1 102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0 103 NC
July 2, 2020 Page 120 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 104 NC 105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1 106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0 107 NC 108 NC 109 NC 110 NC 111 NC 115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 116 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 118 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 119 PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_ CH3/TM3_EXT 123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 127 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 128 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-23 M252KE3AE Multi-function Pin Table
July 2, 2020 Page 121 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M252KG6AE ULQFP128 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 INT0 / TM0 / UART2_TXD / PSIO0_CH4 / PWM0_CH0 / SC0_CLK / USCI1_CTL0 / I2C0_SCL / EBI_ADR0 / ACMP1_N / EADC0_CH5 / PB.5 INT1 / TM1 / UART2_RXD / PSIO0_CH5 / PWM0_CH1 / SC0_DAT / USCI1_CTL1 / I2C0_SDA / EBI_ADR1 / ACMP1_P1 / EADC0_CH4 / PB.4 INT2 / TM2 / PWM0_BRAKE0 / PSIO0_CH6 / PWM0_CH2 / SC0_RST / USCI1_DAT1 / UART1_TXD / I2C1_SCL / EBI_ADR2 / ACMP0_N / EADC0_CH3 / PB.3 INT3 / TM3 / PSIO0_CH7 / PWM0_CH3 / SC0_PWR / USCI1_DAT0 / UART1_RXD / I2C1_SDA / EBI_ADR3 / OPA0_O / ACMP0_P1 / EADC0_CH2 / PB.2 ACMP0_O / PWM1_CH0 / SC0_nCD / I2C0_SCL / UART0_TXD / EBI_ADR4 / PC.12 ACMP1_O / PWM1_CH1 / I2C0_SDA / UART0_RXD / EBI_ADR5 / PC.11 PWM1_CH2 / EBI_ADR6 / PC.10 PWM1_CH3 / EBI_ADR7 / PC.9 PWM0_BRAKE0 / PWM1_CH4 / PWM0_CH4 / QSPI0_MISO1 / I2C1_SCL / USCI1_CLK / UART2_TXD / EBI_ADR8 / OPA0_N / EADC0_CH1 / PB.1 PWM0_BRAKE1 / PWM1_CH5 / PWM0_CH5 / QSPI0_MOSI1 / I2C1_SDA / SPI0_I2SMCLK / UART2_RXD / EBI_ADR9 / OPA0_P / EADC0_CH0 / PB.0 VSS VDD TM0_EXT / BPWM0_CH0 / USCI0_CLK / EBI_nRD / ACMP0_P0 / PA.11 DAC0_ST / TM1_EXT / BPWM0_CH1 / USCI0_DAT0 / EBI_nWR / ACMP1_P0 / PA.10 TM2_EXT / BPWM0_CH2 / UART1_TXD / USCI0_DAT1 / EBI_MCLK / PA.9 INT4 / TM3_EXT / BPWM0_CH3 / UART1_RXD / USCI0_CTL1 / EBI_ALE / PA.8 NC INT5 / EADC0_ST / CLKO / BPWM0_CH5 / UART2_RXD / EBI_nCS0 / PD.12 UART1_TXD / EBI_nCS1 / PD.11 UART1_RXD / EBI_nCS2 / PD.10 NC NC NC NC NC NC NC SPI0_MISO / SC0_DAT / EBI_ADR18 / PF.7 TAMPER0 / EBI_nCS0 / SPI0_MOSI / SC0_CLK / EBI_ADR19 / PF.6 VBAT EADC0_ST / X32_IN / BPWM0_CH4 / PWM0_CH0 / UART2_nCTS / UART2_RXD / PF.5 X32_OUT / BPWM0_CH5 / PWM0_CH1 / UART2_nRTS / UART2_TXD / PF.4 nRESET PE.15 / EBI_AD9 / UART2_RXD / PSIO0_CH1 PE.14 / EBI_AD8 / UART2_TXD / PSIO0_CH0 VDDIO PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / PSIO0_CH7 / USCI2_DAT1 / BPWM0_CH0 / PWM0_CH5 / DAC0_ST PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / PSIO0_CH6 / USCI2_DAT0 / BPWM0_CH1 / PWM0_CH4 PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PSIO0_CH5 / USCI2_CLK / BPWM0_CH2 / PWM0_CH3 PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PSIO0_CH4 / USCI2_CTL0 / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / SC0_nCD / UART0_nRTS / UART0_RXD / I2C0_SDA / USCI2_CTL1 / BPWM0_CH4 / PWM0_CH1 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / BPWM0_CH5 / PWM0_CH0 PD.15 / PSIO0_CH7 / PWM0_CH5 / TM3 / INT1 VDD VSS PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1 PC.6 / EBI_AD8 / UART0_nRTS / I2C1_SMBSUS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2 PC.7 / EBI_AD9 / UART0_nCTS / I2C1_SMBAL / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3 PC.8 / EBI_ADR16 / I2C0_SDA / UART1_RXD / PWM1_CH1 / BPWM1_CH4 PE.13 / EBI_ADR15 / I2C0_SCL / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1 PE.10 / EBI_ADR12 / USCI1_DAT0 / PWM0_CH2 / PWM1_BRAKE0 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0 NC NC PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0 NC NC NC NC USB_VDD33_CAP USB_D+ USB_D- USB_VBUS PD.13 / EBI_AD10 / SPI0_I2SMCLK / USCI2_CTL0 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / USCI1_CTL0 / UART0_TXD PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1 / PSIO0_CH7 PD.5 / I2C1_SCL / USCI1_DAT0 / PSIO0_CH6 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1 / PSIO0_CH5 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK / PSIO0_CH4 NC NC NC NC NC NC NC VDD VSS PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / USCI2_DAT1 / ACMP1_O PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / USCI2_DAT0 / ACMP0_O PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / PWM1_CH3 / USCI2_CLK / PSIO0_CH3 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / PWM1_CH2 / USCI2_CTL0 / PSIO0_CH2 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / PWM1_CH1 / USCI2_CTL1 / PSIO0_CH1 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / PWM1_CH0 / PSIO0_CH0 PD.8 / EBI_AD6 / UART2_nRTS / PSIO0_CH3 PD.9 / EBI_AD7 / UART2_nCTS / PSIO0_CH2 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT BPWM0_CH5 / PWM0_CH0 / PSIO0_CH0 / PE.7 BPWM0_CH4 / PWM0_CH1 / PSIO0_CH1 / USCI0_CTL0 / SC0_nCD / PE.6 BPWM0_CH3 / PWM0_CH2 / PSIO0_CH2 / USCI0_CTL1 / SC0_PWR / EBI_nRD / PE.5 BPWM0_CH2 / PWM0_CH3 / PSIO0_CH3 / USCI0_DAT1 / SC0_RST / EBI_nWR / PE.4 BPWM0_CH1 / PWM0_CH4 / USCI0_DAT0 / SC0_DAT / EBI_MCLK / PE.3 BPWM0_CH0 / PWM0_CH5 / USCI2_CTL0 / USCI0_CLK / SC0_CLK / EBI_ALE / PE.2 NC NC USCI2_DAT1 / I2C1_SCL / QSPI0_MISO0 / EBI_AD10 / PE.1 USCI2_DAT0 / I2C1_SDA / QSPI0_MOSI0 / EBI_AD11 / PE.0 NC NC NC NC NC VSS LDO_CAP VDD TM1 / USCI2_CLK / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / EBI_AD11 / PC.14 PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EBI_AD12 / EADC0_CH15 / PB.15 CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EBI_AD13 / EADC0_CH14 / PB.14 TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / EBI_AD14 / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13 TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / EBI_AD15 / ACMP1_P2 / ACMP0_P2 / DAC0_OUT / EADC0_CH12 / PB.12 AVDD VREF AVSS BPWM1_CH0 / SPI0_I2SMCLK / I2C1_SCL / UART0_nCTS / EBI_ADR16 / EADC0_CH11 / PB.11 BPWM1_CH1 / I2C1_SDA / UART0_nRTS / USCI1_CTL0 / EBI_ADR17 / EADC0_CH10 / PB.10 BPWM1_CH2 / I2C1_SMBAL / UART1_nCTS / UART0_TXD / USCI1_CTL1 / EBI_ADR18 / EADC0_CH9 / PB.9 BPWM1_CH3 / I2C1_SMBSUS / UART1_nRTS / UART0_RXD / USCI1_CLK / EBI_ADR19 / EADC0_CH8 / PB.8 ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / BPWM1_CH4 / EBI_nCS0 / UART1_TXD / USCI1_DAT0 / EBI_nWRL / EADC0_CH7 / PB.7 ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / BPWM1_CH5 / EBI_nCS1 / UART1_RXD / USCI1_DAT1 / EBI_nWRH / EADC0_CH6 / PB.6 Figure 4.1-38 M252KG6AE Function Pin Diagram Pin M252KG6AE Pin Function 1 PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T M0/INT0 2 PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD /TM1/INT1 3 PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/ PWM0_BRAKE0/TM2/INT2 4 PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P SIO0_CH7/TM3/INT3
July 2, 2020 Page 122 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 5 PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O 6 PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O 7 PC.10/EBI_ADR6/PWM1_CH2 8 PC.9/EBI_ADR7/PWM1_CH3 9 PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH 4/PWM0_BRAKE0 10 PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_ CH5/PWM0_BRAKE1 13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT 14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST 15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT 16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4 17 NC 18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5 19 PD.11/EBI_nCS1/UART1_TXD 20 PD.10/EBI_nCS2/UART1_RXD 21 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO 29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0 31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST 32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT 33 NC 34 NC 35 NC 36 NC 37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0 38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1 39 NC
July 2, 2020 Page 123 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 40 NC 41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0 42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1 43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0 44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1 45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4 46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5 47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4 48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3 49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2 50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1 51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0 54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1 55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0 56 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P WM0_CH1 57 PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/ PWM0_CH2/CLKO/PWM1_BRAKE1 58 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C H2/PWM0_CH3 59 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW M0_CH4 60 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW M0_CH5/DAC0_ST 62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0 63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1 nRESET Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. 67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2 68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3 69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0 70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
July 2, 2020 Page 124 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2 72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3 73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O 74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O 84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4 85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5 86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6 87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7 88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD 89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD 90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO 91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2 92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0 97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5 98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4 99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3 100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2 101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1 102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0 103 NC 104 NC 105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1 106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0
July 2, 2020 Page 125 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 107 NC 108 NC 109 NC 110 NC 111 NC 115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1 116 PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B RAKE1 117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO 118 PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1 _CH2/TM2_EXT 119 PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_ CH3/PWM1_CH3/TM3_EXT 123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0 124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1 125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2 126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3 127 PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN T5/ACMP0_O 128 PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN T4/ACMP1_O Table 4.1-24 M252KG6AE Multi-function Pin Table
July 2, 2020 Page 126 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.2 Pin Mapping
Different part number with same package might has different function. Please refer to the selection guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfig. Corresponding Part Number: M251/M252 Series M251/M252 Series Pin Mapping M251 Series M252 Series Pin Name 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PB.5 8 12 1 1 2 1 12 1 1 2 1 PB.4 9 13 2 2 3 2 13 2 2 3 2 PB.3 10 14 3 3 4 3 14 3 3 4 3 PB.2 11 15 4 4 5 4 15 4 4 5 4 PC.12 5 5 PC.11 6 6 PC.10 7 7 PC.9 8 8 PB.1 16 5 5 6 9 16 5 5 6 9 PB.0 17 6 6 7 10 17 6 6 7 10 VSS 11 11 VDD 12 12 PA.11 7 8 13 7 8 13 PA.10 8 9 14 8 9 14 PA.9 9 10 15 9 10 15 PA.8 10 11 16 10 11 16 NC 17 17 PD.12 18 18 PD.11 19 19 PD.10 20 20 NC 21 21 NC 22 22 NC 23 23 NC 24 24 NC 25 25 NC 26 26 NC 27 27 PF.7 28 28 PF.6 12 29 12 29
July 2, 2020 Page 127 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251 Series M252 Series Pin Name 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PF.14 or VBAT 13 13 VBAT 30 30 PF.5 7 11 14 31 7 11 14 31 PF.4 8 12 15 32 8 12 15 32 NC 33 33 NC 34 34 NC 35 35 NC 36 36 PF.3 12 18 9 13 16 37 11 18 9 13 16 37 PF.2 13 19 10 14 17 38 12 19 10 14 17 38 NC 39 39 NC 40 40 PE.8 41 41 PE.9 42 42 PE.10 43 43 PE.11 44 44 PE.12 45 45 PE.13 46 46 PC.8 47 47 PC.7 18 48 18 48 PC.6 19 49 19 49 PA.7 15 20 50 15 20 50 PA.6 16 21 51 16 21 51 VSS 22 52 22 52 VDD 23 53 23 53 PD.15 24 54 24 54 PA.5 17 25 55 17 25 55 PA.4 18 26 56 18 26 56 PA.3 14 20 11 19 27 57 13 20 11 19 27 57 PA.2 15 21 12 20 28 58 14 21 12 20 28 58 PA.1 16 22 13 21 29 59 15 22 13 21 29 59 PA.0 17 23 14 22 30 60 16 23 14 22 30 60 VDDIO 15 23 31 61 15 23 31 61 PE.14 62 62
July 2, 2020 Page 128 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251 Series M252 Series Pin Name 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PE.15 63 63 nRESET 18 24 16 24 32 64 17 24 16 24 32 64 PF.0 19 25 17 25 33 65 18 25 17 25 33 65 ICE_DAT PF.1 20 26 18 26 34 66 19 26 18 26 34 66 ICE_CLK PD.9 67 67 PD.8 68 68 PC.5 27 35 69 27 35 69 PC.4 28 36 70 28 36 70 PC.3 29 37 71 29 37 71 PC.2 30 38 72 30 38 72 PC.1 27 19 31 39 73 27 19 31 39 73 PC.0 28 20 32 40 74 28 20 32 40 74 VSS 75 75 VDD 76 76 NC 77 77 NC 78 78 NC 79 79 NC 80 80 NC 81 81 NC 82 82 NC 83 83 PD.7 84 84 PD.6 85 85 PD.5 86 86 PD.4 87 87 PD.3 41 88 41 88 PD.2 42 89 42 89 PD.1 43 90 43 90 PD.0 44 91 44 91 PD.13 92 92 PA.12 1 21 33 45 93 PA.13 2 22 34 46 94
July 2, 2020 Page 129 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251 Series M252 Series Pin Name 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PA.14 3 23 35 47 95 PA.15 4 24 36 48 96 USB_VBUS 20 1 21 33 45 93 USB_D- 1 2 22 34 46 94 USB_D+ 2 3 23 35 47 95 USB_VDD33_CAP 3 4 24 36 48 96 PE.7 97 97 PE.6 98 98 PE.5 99 99 PE.4 100 100 PE.3 101 101 PE.2 102 102 NC 103 103 NC 104 104 PE.1 105 105 PE.0 106 106 NC 107 107 NC 108 108 NC 109 109 NC 110 110 NC 111 111 VSS 1 5 25 37 49 112 4 5 25 37 49 112 LDO_CAP 2 6 26 38 50 113 5 6 26 38 50 113 VDD 3 7 27 39 51 114 6 7 27 39 51 114 PC.14 40 52 115 40 52 115 PB.15 28 41 53 116 28 41 53 116 PB.14 4 8 29 42 54 117 7 8 29 42 54 117 PB.13 5 9 30 43 55 118 8 9 30 43 55 118 PB.12 6 10 31 44 56 119 9 10 31 44 56 119 AVDD 7 11 32 45 57 120 10 11 32 45 57 120 VREF 58 121 58 121 AVSS 46 59 122 46 59 122 PB.11 60 123 60 123 PB.10 61 124 61 124
July 2, 2020 Page 130 of 266 Rev 1.01 M251/M252 SERIES DATASHEET M251 Series M252 Series Pin Name 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin PB.9 62 125 62 125 PB.8 63 126 63 126 PB.7 47 64 127 47 64 127 PB.6 48 1 128 48 1 128
July 2, 2020 Page 131 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
4.3 Pin Function Description
Group Pin Name Type Description ACMP0 ACMP0_N A Analog comparator 0 negative input pin. ACMP0_O O Analog comparator 0 output pin. ACMP0_P0 A Analog comparator 0 positive input 0 pin. ACMP0_P1 A Analog comparator 0 positive input 1 pin. ACMP0_P2 A Analog comparator 0 positive input 2 pin. ACMP0_P3 A Analog comparator 0 positive input 3 pin. ACMP0_WLAT I Analog comparator 0 window latch input pin ACMP1 ACMP1_N A Analog comparator 1 negative input pin. ACMP1_O O Analog comparator 1 output pin. ACMP1_P0 A Analog comparator 1 positive input 0 pin. ACMP1_P1 A Analog comparator 1 positive input 1 pin. ACMP1_P2 A Analog comparator 1 positive input 2 pin. ACMP1_P3 A Analog comparator 1 positive input 3 pin. ACMP1_WLAT I Analog comparator 1 window latch input pin BPWM0 BPWM0_CH0 I/O BPWM0 channel 0 output/capture input. BPWM0_CH1 I/O BPWM0 channel 1 output/capture input. BPWM0_CH2 I/O BPWM0 channel 2 output/capture input. BPWM0_CH3 I/O BPWM0 channel 3 output/capture input. BPWM0_CH4 I/O BPWM0 channel 4 output/capture input. BPWM0_CH5 I/O BPWM0 channel 5 output/capture input. BPWM1 BPWM1_CH0 I/O BPWM1 channel 0 output/capture input. BPWM1_CH1 I/O BPWM1 channel 1 output/capture input. BPWM1_CH2 I/O BPWM1 channel 2 output/capture input. BPWM1_CH3 I/O BPWM1 channel 3 output/capture input. BPWM1_CH4 I/O BPWM1 channel 4 output/capture input. BPWM1_CH5 I/O BPWM1 channel 5 output/capture input. CLKO CLKO O Clock Out DAC0 DAC0_OUT A DAC0 channel analog output. DAC0_ST I DAC0 external trigger input. EADC0 EADC0_CH0 A EADC0 channel 0 analog input. EADC0_CH1 A EADC0 channel 1 analog input. EADC0_CH2 A EADC0 channel 2 analog input. EADC0_CH3 A EADC0 channel 3 analog input. EADC0_CH4 A EADC0 channel 4 analog input.
July 2, 2020 Page 132 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Group Pin Name Type Description EADC0_CH5 A EADC0 channel 5 analog input. EADC0_CH6 A EADC0 channel 6 analog input. EADC0_CH7 A EADC0 channel 7 analog input. EADC0_CH8 A EADC0 channel 8 analog input. EADC0_CH9 A EADC0 channel 9 analog input. EADC0_CH10 A EADC0 channel 10 analog input. EADC0_CH11 A EADC0 channel 11 analog input. EADC0_CH12 A EADC0 channel 12 analog input. EADC0_CH13 A EADC0 channel 13 analog input. EADC0_CH14 A EADC0 channel 14 analog input. EADC0_CH15 A EADC0 channel 15 analog input. EADC0_ST I EADC0 external trigger input. EBI EBI_AD0 I/O EBI address/data bus bit 0. EBI_AD1 I/O EBI address/data bus bit 1. EBI_AD2 I/O EBI address/data bus bit 2. EBI_AD3 I/O EBI address/data bus bit 3. EBI_AD4 I/O EBI address/data bus bit 4. EBI_AD5 I/O EBI address/data bus bit 5. EBI_AD6 I/O EBI address/data bus bit 6. EBI_AD7 I/O EBI address/data bus bit 7. EBI_AD8 I/O EBI address/data bus bit 8. EBI_AD9 I/O EBI address/data bus bit 9. EBI_AD10 I/O EBI address/data bus bit 10. EBI_AD11 I/O EBI address/data bus bit 11. EBI_AD12 I/O EBI address/data bus bit 12. EBI_AD13 I/O EBI address/data bus bit 13. EBI_AD14 I/O EBI address/data bus bit 14. EBI_AD15 I/O EBI address/data bus bit 15. EBI_ADR0 O EBI address bus bit 0. EBI_ADR1 O EBI address bus bit 1. EBI_ADR2 O EBI address bus bit 2. EBI_ADR3 O EBI address bus bit 3. EBI_ADR4 O EBI address bus bit 4. EBI_ADR5 O EBI address bus bit 5. EBI_ADR6 O EBI address bus bit 6.
July 2, 2020 Page 133 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Group Pin Name Type Description EBI_ADR7 O EBI address bus bit 7. EBI_ADR8 O EBI address bus bit 8. EBI_ADR9 O EBI address bus bit 9. EBI_ADR10 O EBI address bus bit 10. EBI_ADR11 O EBI address bus bit 11. EBI_ADR12 O EBI address bus bit 12. EBI_ADR13 O EBI address bus bit 13. EBI_ADR14 O EBI address bus bit 14. EBI_ADR15 O EBI address bus bit 15. EBI_ADR16 O EBI address bus bit 16. EBI_ADR17 O EBI address bus bit 17. EBI_ADR18 O EBI address bus bit 18. EBI_ADR19 O EBI address bus bit 19. EBI_ALE O EBI address latch enable output pin. EBI_MCLK O EBI external clock output pin. EBI_nCS0 O EBI chip select 0 output pin. EBI_nCS1 O EBI chip select 1 output pin. EBI_nCS2 O EBI chip select 2 output pin. EBI_nRD O EBI read enable output pin. EBI_nWR O EBI write enable output pin. EBI_nWRH O EBI high byte write enable output pin EBI_nWRL O EBI low byte write enable output pin. GPIO PA.x~PH.x I/O General purpose digital I/O pin. I2C0 I2C0_SCL I/O I2C0 clock pin. I2C0_SDA I/O I2C0 data input/output pin. I2C0_SMBAL O I2C0 SMBus SMBALTER pin I2C0_SMBSUS O I2C0 SMBus SMBSUS pin (PMBus CONTROL pin) I2C1 I2C1_SCL I/O I2C1 clock pin. I2C1_SDA I/O I2C1 data input/output pin. I2C1_SMBAL O I2C1 SMBus SMBALTER pin I2C1_SMBSUS O I2C1 SMBus SMBSUS pin (PMBus CONTROL pin) ICE ICE_CLK I/O Serial wired debugger clock pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. ICE_DAT I/O Serial wired debugger data pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. nRESET I External reset input: active LOW, with an internal pull -up. Set this pin low reset to initial state. Note: It is recommended to use 10 kΩ pull -up resistor and 10 uF capacitor on nRESET pin.
July 2, 2020 Page 134 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Group Pin Name Type Description INT0 INT0 I External interrupt 0 input pin. INT1 INT1 I External interrupt 1 input pin. INT3 INT3 I External interrupt 3 input pin. INT4 INT4 I External interrupt 4 input pin. INT5 INT5 I External interrupt 5 input pin. OPA0 OPA0_N A Operational amplifier 0 negative input pin. OPA0_O A Operational amplifier 0 output pin. OPA0_P A Operational amplifier 0 positive input pin. PSIO0 PSIO0_CH0 I/O PSIO 0 channel 0 input/output pin. PSIO1_CH0 I/O PSIO 0 channel 1 input/output pin. PSIO2_CH0 I/O PSIO 0 channel 2 input/output pin. PSIO3_CH0 I/O PSIO 0 channel 3 input/output pin. PSIO4_CH0 I/O PSIO 0 channel 4 input/output pin. PSIO5_CH0 I/O PSIO 0 channel 5 input/output pin. PSIO6_CH0 I/O PSIO 0 channel 6 input/output pin. PSIO7_CH0 I/O PSIO 0 channel 7 input/output pin. CLKO CLKO O Clock Out PWM0 PWM0_BRAKE0 I PWM0 Brake 0 input pin. PWM0_BRAKE1 I PWM0 Brake 1 input pin. PWM0_CH0 I/O PWM0 channel 0 output/capture input. PWM0_CH1 I/O PWM0 channel 1 output/capture input. PWM0_CH2 I/O PWM0 channel 2 output/capture input. PWM0_CH3 I/O PWM0 channel 3 output/capture input. PWM0_CH4 I/O PWM0 channel 4 output/capture input. PWM0_CH5 I/O PWM0 channel 5 output/capture input. PWM1 PWM1_BRAKE0 I PWM1 Brake 0 input pin. PWM1_BRAKE1 I PWM1 Brake 1 input pin. PWM1_CH0 I/O PWM1 channel 0 output/capture input. PWM1_CH1 I/O PWM1 channel 1 output/capture input. PWM1_CH2 I/O PWM1 channel 2 output/capture input. PWM1_CH3 I/O PWM1 channel 3 output/capture input. PWM1_CH4 I/O PWM1 channel 4 output/capture input. PWM1_CH5 I/O PWM1 channel 5 output/capture input. Power VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. VSS P Ground pin for digital circuit.
July 2, 2020 Page 135 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Group Pin Name Type Description VDDIO P Power supply for PA.0~PA.5. VBAT P Power supply by batteries for RTC. AVDD P Power supply for internal analog circuit. AVSS P Ground pin for analog circuit. VREF A ADC reference voltage input. Note: This pin needs to be connected with a 1uF capacitor. LDO_CAP A LDO output pin. Note: This pin needs to be connected with a 1uF capacitor. QSPI0 QSPI0_CLK I/O Quad SPI0 serial clock pin. QSPI0_MISO0 I/O Quad SPI0 MISO0 (Master In, Slave Out) pin. QSPI0_MISO1 I/O Quad SPI0 MISO1 (Master In, Slave Out) pin. QSPI0_MOSI0 I/O Quad SPI0 MOSI0 (Master Out, Slave In) pin. QSPI0_MOSI1 I/O Quad SPI0 MOSI1 (Master Out, Slave In) pin. QSPI0_SS I/O Quad SPI0 slave select pin. SC0 SC0_CLK O Smart Card 0 clock pin. SC0_DAT I/O Smart Card 0 data pin. SC0_PWR O Smart Card 0 power pin. SC0_RST O Smart Card 0 reset pin. SC0_nCD I Smart Card 0 card detect pin. SPI0 SPI0_CLK I/O SPI0 serial clock pin. SPI0_I2SMCLK I/O SPI0 I2S master clock output pin SPI0_MISO I/O SPI0 MISO (Master In, Slave Out) pin. SPI0_MOSI I/O SPI0 MOSI (Master Out, Slave In) pin. SPI0_SS I/O SPI0 slave select pin. TAMPER0 TAMPER0 I/O TAMPER detector loop pin 0. TM0 TM0 I/O Timer0 event counter input/toggle output pin. TM0_EXT I/O Timer0 external capture input/toggle output pin. TM1 TM1 I/O Timer1 event counter input/toggle output pin. TM1_EXT I/O Timer1 external capture input/toggle output pin. TM2 TM2 I/O Timer2 event counter input/toggle output pin. TM2_EXT I/O Timer2 external capture input/toggle output pin. TM3 TM3 I/O Timer3 event counter input/toggle output pin. TM3_EXT I/O Timer3 external capture input/toggle output pin. UART0 UART0_RXD I UART0 data receiver input pin. UART0_TXD O UART0 data transmitter output pin. UART0_nCTS I UART0 clear to Send input pin. UART0_nRTS O UART0 request to Send output pin.
July 2, 2020 Page 136 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Group Pin Name Type Description UART1 UART1_RXD I UART1 data receiver input pin. UART1_TXD O UART1 data transmitter output pin. UART1_nCTS I UART1 clear to Send input pin. UART1_nRTS O UART1 request to Send output pin. UART2 UART2_RXD I UART2 data receiver input pin. UART2_TXD O UART2 data transmitter output pin. UART2_nCTS I UART2 clear to Send input pin. UART2_nRTS O UART2 request to Send output pin. USB USB_VBUS P Power supply from USB host or HUB. USB_D- A USB differential signal D-. USB_D+ A USB differential signal D+. USB_VDD33_CAP A Internal power regulator output 3.3V decoupling pin. USCI0 USCI0_CLK I/O USCI0 clock pin. USCI0_CTL0 I/O USCI0 control 0 pin. USCI0_CTL1 I/O USCI0 control 1 pin. USCI0_DAT0 I/O USCI0 data 0 pin. USCI0_DAT1 I/O USCI0 data 1 pin. USCI1 USCI1_CLK I/O USCI1 clock pin. USCI1_CTL0 I/O USCI1 control 0 pin. USCI1_CTL1 I/O USCI1 control 1 pin. USCI1_DAT0 I/O USCI1 data 0 pin. USCI1_DAT1 I/O USCI1 data 1 pin. USCI2 USCI2_CLK I/O USCI2 clock pin. USCI2_CTL0 I/O USCI2 control 0 pin. USCI2_CTL1 I/O USCI2 control 1 pin. USCI2_DAT0 I/O USCI2 data 0 pin. USCI2_DAT1 I/O USCI2 data 1 pin. X32 X32_IN I External 32.768 kHz crystal input pin. X32_OUT O External 32.768 kHz crystal output pin. XT1 XT1_IN I External high speed crystal input pin. XT1_OUT O External high speed crystal output pin.
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5 BLOCK DIAGRAM
5.1 M251/M252 Block Diagram
USB* : Only supported in M252 series. Please refer to the selection guide in section 4.2 for detailed information. Figure 5.1-1 M251/M252 Block Diagram
July 2, 2020 Page 138 of 266 Rev 1.01 M251/M252 SERIES DATASHEET
6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M23 Core
The Cortex ® -M23 processor is a low gate count, two -stage, and highly energy efficient 32 -bit RISC processor, which has an AMBA AHB5 interface supporting Arm® TrustZone® technology, a debug access port supporting serial wire debug and single -cycle I/O ports. It has an NVIC component and MPU for memory -protection functionality. The processor also supports Security Extension. The NuMicro® M251/M252 series is embedded with Cortex ® -M23 processor. Figure 6.1-1 shows the functional controller of the processor. Cortex-M23 processor Embedded Trace Macrocell (ETM) Cross Trigger Interface (CTI) Micro Trace Buffer (MTB) Cortex-M23 processor core Nested Vectored Interrupt (NVIC) Memory Protection Secure Memory Protection Unit (MPU_S) Non-secure Memory Protection Unit (MPU_NS) Security Attribution Unit (SAU) Wakeup Interrupt Controller (WIC) Bus matrix MTB SRAM interface APBIRQ and power control interface Implementation Defined Attribution Unit (IDAU) ETM ATB interface Slave AHB interface Data Watchpoint and Trace (DWT) Single-cycle I/O port AHB Master MTB AHB Flash Patch and Breakpoint Unit (FPB)* Processor ROM table * Flash Patching is not supported in the Cortex-M23 processor. Configurable Optional Note: Security attribution unit, ETM, CTI and MTB functions are not supported in M251/M252. Figure 6.1-1 Cortex® -M23 Block Diagram
July 2, 2020 Page 139 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Cortex® -M23 processor features: Armv8-M Baseline architecture. Armv8-M Baseline Thumb® -2 instruction set that combines high code density with 32-bit performance. Support for single-cycle I/O access. Power control optimization of system components. Integrated sleep modes for low power consumption. Optimized code fetching for reduced Flash and ROM power consumption. A 32-bit Single cycle Hardware multiplier. A 32-bit Hardware divider. Deterministic, high-performance interrupt handling for time-critical applications. Deterministic instruction cycle timing. Support for system level debug authentication. Support for Arm® Debug Interface Architecture ADIv5.1 Serial Wire Debug (SWD). ETM for instruction trace. Separated privileged and unprivileged modes. Security Extension supporting a Secure and a Non-secure state. Protected Memory System Architecture (PMSAv8) Memory Protection Units (MPUs) for both Secure and Non-secure states. Security Attribution Unit (SAU). SysTick timers for both Secure and Non-secure states. A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor with up to 240 interrupts.
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6.2 System Manager
6.2.1 Overview
System management includes the following sections: System Reset System Power Distribution SRAM Memory Orginization System Timer (SysTick) Nested Vectored Interrupt Controller (NVIC) System Control register
6.2.2 System Reset
The system reset can be issued by one of the events listed below . These reset event flags can be read from SYS_RSTSTS register to determine the reset source . Hardware reset sourcces are from peripheral signals. Software reset can trigger reset through setting control registers. Hardware Reset Sources – Power-on Reset – Low level on the nRESET pin with glitch filter time 24us – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) – Brown-out Detector Reset (BOD Reset) – CPU Lockup Reset Software Reset Sources – CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0]) – MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing 1 to SYSRESETREQ (AIRCR[2]) – CPU Reset for Cortex® -M23 core Only by writing 1 to CPURST (SYS_IPRST0[1])
July 2, 2020 Page 141 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Low Voltage Reset Power-on Reset Brown-out Reset Reset Pulse Width ~3.2ms WDT/WWDT Reset System Reset ~50k ohm @3.3v Reset Pulse Width 2 system clocks nRESET VDD AVDD CHIP Reset CHIPRST(SYS_IPRST0[0]) CPU Reset CPURST(SYS_IPRST0[1]) CPU Lockup Reset MCU Reset SYSRSTREQ(AIRCR[2]) LVREN(SYS_BODCTL[7]) BODRSTEN(SYS_BODCTL[3]) POROFF(SYS_PORCTL[15:0]) Reset Pulse Width
64 WDT clocks
Figure 6.2-1 System Reset Sources There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset Cortex® -M23 only; the other reset sources will reset Cortex ® -M23 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6.2-1. Reset Sources Register POR NRESET WDT LVR BOD Lockup CHIP MCU CPU SYS_RSTSTS 0x001 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = CHIPRST (SYS_IPRST0[0]) BODEN (SYS_BODCTL[0]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 BODVL (SYS_BODCTL[2:1]) BODRSTEN (SYS_BODCTL[3]) HXTEN (CLK_PWRCTL[0]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 LXTEN (CLK_PWRCTL[1]) WDTCKEN (CLK_APBCLK0[0])
July 2, 2020 Page 142 of 266 Rev 1.01 M251/M252 SERIES DATASHEET HCLKSEL (CLK_CLKSEL0[2:0]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 WDTSEL (CLK_CLKSEL1[1:0]) HXTSTB (CLK_STATUS[0]) LXTSTB (CLK_STATUS[1]) PLLSTB (CLK_STATUS[2]) HIRCSTB (CLK_STATUS[4]) CLKSFAIL (CLK_STATUS[7]) RSTEN (WDT_CTL[1]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 - - WDTEN (WDT_CTL[7]) WDT_CTL except bit 1 and bit 7. 0x0800 0x0800 0x0800 0x0800 0x0800 - 0x0800 - - WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 - - WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CNT 0x3F 0x3F 0x3F 0x3F 0x3F - 0x3F - - BS (FMC_ISPCTL[1]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 - - BL (FMC_ISPCTL[16]) FMC_DFBA Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 - Reload from CONFIG1 - - CBS (FMC_ISPSTS[2:1)) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 - - VECMAP (FMC_ISPSTS[23:9]) Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 - Reload base on CONFIG0 - - Other Peripheral Registers Reset Value - FMC Registers Reset Value Note: ‘-‘ means that the value of register keeps original setting.
July 2, 2020 Page 143 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Table 6.2-1 Reset Value of Registers nRESET Reset 6.2.2.1 The nRESET reset means to generate a reset signal by pull ing low nRESET pin , which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 24 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V DD and the state keeps longer than 24 us ( glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Table 6.2-2 shows the nRESET reset waveform. nRESET
0.2 VDD
0.7 VDD
Figure 6.2-2 nRESET Reset Waveform Power-on Reset (POR) 6.2.2.2 The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows the power-on reset waveform. VDD VPOR Power-on Reset 0.1V Figure 6.2-3 Power-on Reset (POR) Waveform Low Voltage Reset (LVR) 6.2.2.3 If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN (SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AV DD during system oper ation. When the AV DD voltage is lower than V LVR and the state keeps longer than De -glitch time set by LVRDGSEL (SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above V LVR and the state keeps longer than De -glitch time set by LVRDGSEL
July 2, 2020 Page 144 of 266 Rev 1.01 M251/M252 SERIES DATASHEET (SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De -glitch function. Figure 6.2-4 shows the Low Voltage Reset waveform. AVDD VLVR Low Voltage Reset ( < LVRDGSEL) ( =LVRDGSEL) ( =LVRDGSEL) LVREN 200 us Delay for LVR stable Figure 6.2-4 Low Voltage Reset (LVR) Waveform Brown-out Detector Reset (BOD Reset) 6.2.2.4 If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bi t BODEN (SYS_BODCTL[0]), Brown -out Detector function will detect AV DD during system operation. When the AV DD voltage is lower than V BOD which is decided by BODEN and BODVL (SYS_BODCTL[18:16]) and the state keeps longer than De -glitch time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user configuration register CBODEN (CONFIG0 [ 19]), CBOV (CONFIG0 [2 3:21]) and CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
July 2, 2020 Page 145 of 266 Rev 1.01 M251/M252 SERIES DATASHEET AVDD VBODL BODOUT BODRSTEN Brown-out Reset (< BODDGSEL) (= BODDGSEL) (= BODDGSEL) Hysteresis VBODH Figure 6.2-5 Brown-out Detector (BOD) Waveform Watchdog Timer Reset (WDT) 6.2.2.5 In most industr ial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliabilit y. The watchdog timer(WDT) is widely used to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog time-out. User may decide to enable system reset during watchdog time -out to recover the system and take action for the system crash/out-of-control after reset. Software can check if the reset is caused by watchdog time -out to indicate the previous reset is a watchdog reset and handle the failure of MCU after watchdog time -out reset by checking WDTRF(SYS_RSTSTS[2]). CPU Lockup Reset 6.2.2.6 CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate indication of seriously errant kernel software. This is the result of the CPU being locked because of an unrecoverable exception followin g the activation of the processor’s built in system state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored. CPU Reset, CHIP Reset and MCU Reset 6.2.2.7 The CPU Reset means only Cortex ® -M23 core is reset and all other peripherals remain the same status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power -on Reset. The CPU and all peripherals are reset and BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG 0 setting. User can set the CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be reloaded from CONFIG 0 setting a nd keep its original software setting for booting from APROM or
July 2, 2020 Page 146 of 266 Rev 1.01 M251/M252 SERIES DATASHEET LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3 System Power Distribution
In this chip, power distribution is divided into four segments: Analog power from AVDD and AVSS provides the power for analog components operation. Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.5V power for digital operation and I/O pins. USB transceiver power from VBUS offers the power for operating the USB transceiver. RTC power from regulator uninterrupted power domain provides, the power for RTC and 20 bytes backup registers. Analog power (AV DD) should be the same voltage level of the digital power (V DD). Figure 6.2-6 shows the ower distribution of the M251/M252 series. AVDD AVSS VDD VSS SRAM PLL IO CellPOR33 4~32 MHz crystal oscillator 32.768 kHz crystal oscillator Digital Logic Flash Power On Control X32_OUT(PF.4) X32_IN(PF.5) VREF XT1_IN(PF.3) XT1_OUT(PF.2) GPIO except PF.4~PF.6 and PA.0~PA.5 1.5V M251/M252 Power Distribution VDDIOIO Cell LVDR (Low Voltage Reset, Brown-out Detector) 12-bit DAC 12-bit ADC Internal Reference Voltage Temp. Sensor Analog Comparator USB 1.1 PHY
48 MHz HIRC48
5V à 1.5V Regulator Power Management POR15 SW_DPD PA.0~PA.5 OPA 38.4 kHz LIRC Oscillator IO Cell PF.6
4 MHz
LDO_CAP RTC_LDO Vbat 1.5V Vbus RTC & 20 bytes backup register 1uF Figure 6.2-6 NuMicro® M251/M252 Power Distribution Diagram
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6.2.4 Power Modes and Wake-up Sources
The M251/M252 series has a power manager unit to support several operating modes for saving power. Table 6.2-2 lists all power modes in the M251/M252 series. Mode CPU Operating Maximum Speed ( MHz) LDO_CAP(V) Clock Disable Normal mode 48 1.5 All clocks are disabled by control register. Idle mode CPU enters Sleep mode 1.5 Only CPU clock is disabled. Power-down mode CPU enters Deep Sleep mode 1.5 Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Fast wake up Power- down mode (FWPD) CPU enters Sleep mode 1.5 Most clocks are disabled except LIRC/LXT, and only RTC/WDT/Timer/UART peripheral clocks still enable if their clock sources are selected as LIRC/LXT. Deep Power-down mode (DPD) Power off 1.5 Only LIRC/LXT still enable for RTC function and wake-up timer usage Table 6.2-2 Power Mode Table There are different power mode entry setting s. Each power mode has different entry setting and leaving condition. Table 6.2-3 shows the entry setting for each power mode. When chip power -on, chip is running ar normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PD EN (CLK_PWRCTL:[7]) and PDMSEL (CLK_PMUCTL[2:0]) and execute WFI instruction. Register/Instruction Mode SLEEPDEEP (SCR[2]) PDEN (CLK_PWRCTL[7]) PDMSEL (CLK_PMUCTL[2:0]) CPU Run WFI Instruction Normal mode 0 0 0 NO Idle mode (CPU enters Sleep mode) 0 0 0 YES Power-down mode (CPU enters Deep Sleep mode) 1 1 0 YES Fast wake up Power -down mode (FWPD) 1 1 2 YES Deep Power-down mode (CPU enters Sleep mode) 1 1 6 YES Table 6.2-3 Power Mode Difference Table There are several wake -up sources in Idle mode and Power-down mode. Table 6.2-4 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC. SRAM content retended. Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction. CPU sets sleep mode enable and power down enable and
July 2, 2020 Page 148 of 266 Rev 1.01 M251/M252 SERIES DATASHEET executes WFI instruction. Wake-up Sources N/A All interrupts RTC, WDT, I² C, Timer, UART, BOD, GPIO, EINT, USCI, USBD and ACMP Available Clocks All All except CPU clock LXT and LIRC After Wake-up N/A CPU back to normal mode CPU back to normal mode Table 6.2-4 Power Mode Difference Table Power Level 0 CPU Clock ON Fast wake up Power-down Mode CPU Clock OFF HXT, HIRC, HIRC48, PCLK OFF Flash Halt POR Reset nReset Pin WDT reset CHIP reset LVR BOD reset Lockup reset System reset CPU executes WFI Interrupts occur Idle Mode (PL0) CPU Clock OFF Flash Halt LXT, LIRC ON HXT, MIRC, HIRC48, PCLK ON LXT, LIRC ON HXT, MIRC, HIRC48, LXT, LIRC, HCLK, PCLK ON Flash ON Power Level 3 CPU Clock ON LXT, LIRC, HCLK and PCLK ON Flash ON CPU executes WFI Interrupts occur Idle Mode (PL3) CPU Clock OFF Flash Halt LXT, LIRC and PCLK ON Power-down Mode CPU Clock OFF HXT, HIRC, HIRC48, PCLK OFF Flash Halt LXT, LIRC ON Deep Power-down Mode CPU Clock OFF HXT, HIRC, HIRC48, PCLK OFF Flash Halt LXT, LIRC ON Figure 6.2-7 Power Mode State Machine 1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode. 2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode. 3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on. 4. If WDT clock source is selected as LIRC and LIRC is on. 5. If RTC clock source is selected as LXT and LXT is on. 6. If UART clock source is selected as LXT and LXT is on. Normal Mode Idle Mode Power-Down Mode PD DPD HXT (4~32 MHz XTL) ON ON Halt Halt MIRC (4 MHz OSC) ON ON Halt Halt HIRC48 (48 MHz OSC) ON ON Halt Halt LXT (32768 Hz XTL) ON ON ON/OFF1 ON/OFF1 LIRC (38.4 kHz OSC) ON ON ON/OFF2 ON/OFF2 PLL ON/OFF ON/OFF Halt Halt
July 2, 2020 Page 149 of 266 Rev 1.01 M251/M252 SERIES DATASHEET LDO ON ON ON OFF CPU ON Halt Halt Halt HCLK/PCLK ON ON Halt Halt SRAM retention ON ON ON OFF FLASH ON ON Halt Halt GPIO ON ON Halt Halt PDMA ON ON Halt Halt TIMER ON ON ON/OFF3 Halt PWM ON ON Halt Halt WDT ON ON ON/OFF4 Halt WWDT ON ON Halt Halt RTC ON ON ON/OFF5 ON/OFF5 UART ON ON ON/OFF6 Halt SC ON ON Halt Halt USCI ON ON Halt Halt I2C ON ON Halt Halt SPI ON ON Halt Halt USBD ON ON Halt Halt ADC ON ON Halt Halt ACMP ON ON Halt Halt Table 6.2-5 Clocks in Power Modes Wake-up sources in Power-down mode: RTC, WDT, I² C, Timer, UART, USCI, BOD, GPIO, USBD, and ACMP. After chip enters power down, the following wake -up sources can wake chip up to normal mode. Table 6.2-5 lists the condition about how to enter Power-down mode again for each peripheral. *User needs to wait this condition before setting PDEN( CLK_PWRCTL[7]) and execute WFI to enter Power-down mode. Wake-Up Source Wake-Up Condition Power-Down Mode System Can Enter Power-Down Mode Again Condition* PD FWKPD DPD BOD Brown-Out Detector Interrupt Y N After software writes 1 to clear BODIF (SYS_BODCTL[4]). LVR LVR Reset Y N After software writes 1 to clear LVRF (SYS_RSTSTS[3]) N Y After software writes 1 to clear LVRWK (CLK_PMUSTS[12]) when DPD mode is entered. INT External Interrupt Y N After software write 1 to clear the Px_INTSRC[n] bit.
July 2, 2020 Page 150 of 266 Rev 1.01 M251/M252 SERIES DATASHEET GPIO GPIO Interrupt Y N After software write 1 to clear the Px_INTSRC[n] bit. GPIO(PC.0) Wake-up pin Rising or falling edge event, 1-pin N Y PINWK(CLK_PMUSTS[0]) is cleared when DPD mode is entered. GPIO(PB.0) Wake-up pin Rising or falling edge event, 1-pin N Y PINWK(CLK_PMUSTS[3]) is cleared when DPD mode is entered. GPIO(PB.2) Wake-up pin Rising or falling edge event, 1-pin N Y PINWK(CLK_PMUSTS[4]) is cleared when DPD mode is entered. GPIO(PB.12) Wake-up pin Rising or falling edge event, 1-pin N Y PINWK(CLK_PMUSTS[5]) is cleared when DPD mode is entered. GPIO(PF.6) Wake-up pin Rising or falling edge event, 1-pin N Y PINWK(CLK_PMUSTS[6]) is cleared when DPD mode is entered. TIMER Timer Interrupt Y N After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]). Wakeup timer Wakeup by wake-up timer time-out N Y DPD_TMRWK (CLK_PMUSTS[2]) or DPD_TMRWK (CLK_PMUSTS[6]) is cleared when SPD or DPD mode is entered. WDT WDT Interrupt Y N After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect). RTC Alarm Interrupt Y N After software writes 1 to clear ALMIF (RTC_INTSTS[0]). Time Tick Interrupt Y N After software writes 1 to clear TICKIF (RTC_INTSTS[1]). RTC Wakeup by RTC alarm N Y RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is entered. Wakeup by RTC tick time N Y RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is entered. Wakeup by tamper event N Y RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is entered. UART nCTS wake-up Y N After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]). Incoming Data wake-up Y N After software writes 1 to clear DATWKF (UARTx_WKSTS[1]). Received FIFO Threshold Wake-up Y N After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]). RS-485 AAD Mode Wake-up Y N After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]). Received FIFO Threshold Time-out Wake-up Y N After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]). USCI UART CTS Toggle Y N After software writes 1 to clear WKF (UUART_WKSTS[0]). Data Toggle Y N After software writes 1 to clear WKF (UUART_WKSTS[0]). USCI I2C Data toggle Y N After software writes 1 to clear WKF (UI2C_WKSTS[0]). Address match Y N After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], and t hen writes 1 to clear WKF (UI2C_WKSTS[0]). USCI SPI SS Toggle Y N After software writes 1 to clear WKF (USPI_WKSTS[0]). I2C Address match wake-up Y N After software writes 1 to clear WKAKDONE (I2C_WKSTS[1]). Then software writes 1 to clear WKIF(I2C_WKSTS[0]). USBD Remote Wake-up Y N After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
July 2, 2020 Page 151 of 266 Rev 1.01 M251/M252 SERIES DATASHEET ACMP Comparator Power- Down Wake-Up Interrupt Y N After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1 (ACMP_STATUS[9]). Table 6.2-6 Condition of Entering Power-down Mode Again
6.2.5 Chip Bus Matrix
The M251/M252 series provides 4G -byte addressing space. The memory locations assigned to each on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and programming will be described in the following sections for each on -chip peripheral. The M251/M252 series only supports little-endian data format.
6.2.6 System Memory Map
The M251/M252 series provides 4G -byte addressing space. The memory locations as signed to each on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and programming will be described in the following sections for each on -chip peripheral. The M251/M252 series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 – 0x0003_FFFF FLASH_BA FLASH Memory Space (256 Kbytes) 0x2000_0000 – 0x2000_7FFF SRAM0_BA SRAM Memory Space (32 Kbytes) 0x6000_0000 – 0x6FFF_FFFF EXTMEM_BA External Memory Space (256 Mbytes) Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF) 0x4000_0000 – 0x4000_01FF SYS_BA System Control Registers 0x4000_0200 – 0x4000_02FF CLK_BA Clock Control Registers 0x4000_0300 – 0x4000_03FF NMI_BA NMI Control Registers 0x4000_4000 – 0x4000_4FFF GPIO_BA GPIO Control Registers 0x4000_8000 – 0x4000_8FFF PDMA_BA Peripheral DMA Control Registers 0x4000_C000 – 0x4000_CFFF FMC_BA Flash Memory Control Registers 0x4001_0000 – 0x4001_0FFF EBI_BA External Bus Interface Control Registers 0x4003_1000 – 0x4003_1FFF CRC_BA CRC Generator Registers APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4004_0000 – 0x4004_0FFF WDT_BA Watchdog Timer Control Registers 0x4004_1000 – 0x4004_1FFF RTC_BA Real Time Clock (RTC) Control Register 0x4004_3000 – 0x4004_3FFF EADC_BA Enhanced Analog-Digital-Converter (EADC) Control Registers 0x4004_5000 – 0x4004_5FFF ACMP01_BA Analog Comparator 0/ 1 Control Registers 0x4004_6000 – 0x4004_6FFF OPA_BA OP Amplifier Control Registers 0x4004_7000 – 0x4004_7FFF DAC_BA DAC Control Registers 0x4005_0000 – 0x4005_0FFF TMR01_BA Timer0/Timer1 Control Registers 0x4005_1000 – 0x4005_1FFF TMR23_BA Timer2/Timer3 Control Registers 0x4005_8000 – 0x4005_8FFF PWM0_BA PWM0 Control Registers
July 2, 2020 Page 152 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 0x4005_9000 – 0x4005_9FFF PWM1_BA PWM1 Control Registers 0x4005_A000 – 0x4005_AFFF BPWM0_BA BPWM0 Control Registers 0x4005_B000 – 0x4005_BFFF BPWM1_BA BPWM1 Control Registers 0x4006_0000 – 0x4006_0FFF QSPI0_BA QSPI0 Control Registers 0x4006_1000 – 0x4006_1FFF SPI0_BA SPI0 Control Registers 0x4007_0000 – 0x4007_0FFF UART0_BA UART0 Control Registers 0x4007_1000 – 0x4007_1FFF UART1_BA UART1 Control Registers 0x4007_2000 – 0x4007_2FFF UART2_BA UART2 Control Registers 0x4008_0000 – 0x4008_0FFF I2C0_BA I2C0 Control Registers 0x4008_1000 – 0x4008_1FFF I2C1_BA I2C1 Control Registers 0x4009_0000 – 0x4009_0FFF SC0_BA Smartcard Host 0 Control Registers 0x400C_0000 – 0x400C_0FFF USBD_BA USB Device Control Register 0x400C_3000 – 0x400C_3FFF PSIO_BA PSIO Control Register 0x400D_0000 – 0x400D_0FFF USCI0_BA USCI0 Control Registers 0x400D_1000 – 0x400D_1FFF USCI1_BA USCI1 Control Registers 0x400D_2000 – 0x400D_2FFF USCI2_BA USCI2 Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.2-7 Address Space Assignments for On-Chip Controllers
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6.2.7 SRAM Memory Orginization
The M251/M252 series supports embedded SRAM with up to 32 Kbytes size. Supports up to 32 Kbytes SRAM Supports byte /half word /word write Supports oversize response error Table 6.2-9 shows the M251/M252 series SRAM organization. The address between 0x200 0_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses. 512MB 16K byte SRAM bank0 0x2000_0000 Reserved 0x3FFF_FFFF 16K byte device 0x2000_2000 0x2000_1000 8K byte SRAM bank0 Reserved 8K byte device 4K byte SRAM bank0 Reserved 4K byte device 32K byte SRAM bank0 Reserved 32K byte device 0x2000_4000 0x2000_8000 Figure 6.2-8 SRAM Memory Organization
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6.2.8 IRC Auto Trim
This chip supports auto -trim function: the HIRC trim (48 MHz RC oscillator) and MIRC trim (4 .032 RC oscillator), according to the accurate LXT (32.768 kHz crystal oscillator) or internal USB synchronous mode, automatically gets accurate output frequency, 0.25 % deviation within all temperature ranges. For instance, the system needs an accurate 4 .032 MHz clock. In such case, if neither using use PLL as the system clock source nor soldering 32.768 kHz crystal in system, us er has to set REFCKSEL (SYS_MIRCTRIMCTL[10] reference clock selectio n) to “1”, set FREQSEL (SYS_MIR CTRIMCTL[1:0] trim frequency sele ction) to “10”, and the auto -trim function will be enabled. Interru pt status bit FREQLOCK (SYS_MIR CTRIMSTS[0] MIRC frequency lock status) “1” indicates the MIRC output frequency is accurate within 0.25% deviation. In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as the system clock source nor soldering 32.768 kHz crystal in system, us er has to set REFCKSEL (SYS_HIRCTRIMCTL[10] reference clock selectio n) to “1”, set FREQSEL (SYS_HIR CTRIMCTL[1:0] trim frequency s election) to “10”, and the auto -trim function will be enabled. Interrupt status bit FREQLOCK (SYS_HIRCT RIMSTS[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate within 0.25% deviation. HIRC trim and MIRC trim only can work properly when the clock sources are stable. When the RC clock or the reference clock are not stable or the system go into power down, HIRC trim and MIRC trim need to wait until the clock are stable or system wake up, t hen it can be enable or it will get a clock error flag.
6.2.9 UART0_TXD/USCI0_DAT0 Modulation with PWM
This chip supports UART0_TXD/USCI_DAT0 to modulate with PWM channel. User can set MODPWMSEL(SYS_MODCTL[7:4]) to select which PWM0 channel to modulate with UART0_TXD/USCI0_DAT0 and set MODEN(SYS_MODCTL[0]) to enable modulation function. PWM0_CHx UART0_TXD/USCI0_DAT0 MODH=0 MODH=1 Figure 6.2-11 UART0_TXD/USCI0_DAT0 Modulated with PWM Channel
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6.2.10 System Timer (SysTick)
The Cortex® -M23 includes an integrated system timer, SysTick, which provides a simple, 24 -bit clear- on-write, decrementing, wrap -on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple co unter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_ LOAD value rather than an arbitrary value when it is enabled. If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ Arm® Cortex® -M23 Technical Reference Manual” and “Arm v8-M Architecture Reference Manual”.
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6.2.11 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail -chaining of interr upts. You can only fully access the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable the Configuration and Control Register. Any other user mode access causes a bus fault. You can access all NVIC r egisters using byte, halfword, and word accesses unless otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC registers and system debug registers are little-endian regardless of the endianness state of the processor. The NVIC supports: An implementation-defined number of interrupts, in the range 1-64 interrupts. A programmable priority level of 0-3 for each interrupt; a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Level and pulse detection of interrupt signals. Dynamic reprioritization of interrupts. Grouping of priority values into group priority and subpriority fields. Interrupt tail-chaining. An external Non Maskable Interrupt (NMI) WIC with Ultra-low Power Sleep mode support The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. Exception Model and System Interrupt Map 6.2.11.1 Table 6.2-8 lists the exception model supported by the M251/M252 series. Software can set 4 levels of priority on some of these exceptions as well as on all interrupts. The highest user -configurable priority is denoted as “0x00” and the lowest priority is denoted as “0x C0” (The 6-LSB always 0). The default priority of all the user -configurable i nterrupts is “0x00”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Exception Type Vector Number Vector Address Priority Reset 1 0x00000004 -3 NMI 2 0x00000008 -2 Hard Fault 3 0x0000000C -1 Reserved 4~ 10 Reserved SVCall 11 0x0000002C Configurable Reserved 12~13 Reserved PendSV 14 0x00000038 Configurable
July 2, 2020 Page 157 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Table 6.2-8 Exception Model Vector Number Interrupt Number (Bit In Interrupt Registers) Interrupt Name Interrupt Description 0 ~ 15 - - System exceptions 16 0 BODOUT Brown-Out low voltage detected interrupt 17 1 IRC_INT IRC TRIM interrupt 18 2 PWRWU_INT Clock controller interrupt for chip wake-up from power-down state 19 3 Reserved Reserved 20 4 CLKFAIL Clock fail detected interrupt 21 5 Reserved Reserved 22 6 RTC_INT Real time clock interrupt 23 7 TAMPER_INT Backup register tamper interrupt 24 8 WDT_INT Watchdog Timer interrupt 25 9 WWDT_INT Window Watchdog Timer interrupt 26 10 EINT0 External interrupt from PA.0, PD.2 or PE.4 pins 27 11 EINT1 External interrupt from PB.0, PD.3 or PE.5 pins 28 12 EINT2 External interrupt from PC.0 pin 29 13 EINT3 External interrupt from PD.0 pin 30 14 EINT4 External interrupt from PE.0 pin 31 15 EINT5 External interrupt from PF.0 pin 32 16 GPA_INT External interrupt from PA[15:0] pin 33 17 GPB_INT External interrupt from PB[15:0] pin 34 18 GPC_INT External interrupt from PC[15:0] pin 35 19 GPD_INT External interrupt from PD[15:0] pin 36 20 GPE_INT External interrupt from PE[15:0] pin 37 21 GPF_INT External interrupt from PF[15:0] pin 38 22 QSPI0_INT QSPI0 interrupt 39 23 SPI0_INT SPI0 interrupt 40 24 BRAKE0_INT PWM0 brake interrupt 41 25 PWM0_P0_INT PWM0 pair 0 interrupt 42 26 PWM0_P1_INT PWM0 pair 1 interrupt SysTick 15 0x0000003C Configurable Interrupt (IRQ0 ~ IRQ63) 16 ~ 63 0x00000000 + (Vector Number)*4 Configurable
July 2, 2020 Page 158 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 43 27 PWM0_P2_INT PWM0 pair 2 interrupt 44 28 BRAKE1_INT PWM1 brake interrupt 45 29 PWM1_P0_INT PWM1 pair 0 interrupt 46 30 PWM1_P1_INT PWM1 pair 1 interrupt 47 31 PWM1_P2_INT PWM1 pair 2 interrupt 48 32 TMR0_INT Timer 0 interrupt 49 33 TMR1_INT Timer 1 interrupt 50 34 TMR2_INT Timer 2 interrupt 51 35 TMR3_INT Timer 3 interrupt 52 36 UART0_INT UART0 interrupt 53 37 UART1_INT UART1 interrupt 54 38 I2C0_INT I2C0 interrupt 55 39 I2C1_INT I2C1 interrupt 56 40 PDMA_INT PDMA interrupt 57 41 DAC_INT DAC interrupt 58 42 EADC_INT EADC interrupt source 0 59 43 EADC1_INT EADC interrupt source 1 60 44 ACMP01_INT ACMP0 and ACMP1 interrupt 61 45 BPWM0 BPWM0 interrupt 62 46 EADC_INT2 EADC interrupt source 2 63 47 EADC_INT EADC interrupt source 3 64 48 UART2_INT UART2 interrupt 65 49 Reserved Reserved 66 50 USCI0 USCI0 interrupt 67 51 Reserved Reserved 68 52 USCI1 USCI1 interrupt 69 53 USBD_INT USB device interrupt 70 54 BPWM1 BPWM1 71 55 Reserved Reserved 72 56 Reserved Reserved 73 57 Reserved Reserved 74 58 SC0_INT Smart card host 0 interrupt 75 59 RTCLVR_INT RTC LVR interrupt 76 60 USCI2 USCI2 interrupt 77 61 Reserved Reserved
July 2, 2020 Page 159 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 78 62 OPA0 OPA0 interrupt 79 63 Reserved Reserved Table 6.2-9 Interrupt Number Table Operation Description 6.2.11.2 NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear -Enable register bit -field. The registers use a write -1-to-enable and write -1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt asse rtion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new ac tivations of the associated interrupt. NVIC interrupts can be pended/un -pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set -Pending Register and Clear -Pending Register respectively. The registers use a write-1-to-enable and write -1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear -Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8 -bit field within a 32 -bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M23 core executes the WFI instruction. After that, chip enters Power-down mode and wait for wake -up interrupt source triggered to leave Power-down mode . In Power-down mode , the clock controller turns off the 4~32 MHz external high speed crystal (HXT) , 48 MHz internal high speed RC oscillator (HIRC) and 4 MHz internal median speed RC oscillator (MIRC) to reduce the overall system power consumption Figure 6.3-1 shows the clock generator and the overview of the clock source control.
July 2, 2020 Page 161 of 266 Rev 1.01 M251/M252 SERIES DATASHEET PLL PLL LXT USCI0~2 ACMP0~1 Module in AHB or Bus matrix USB1.1 Device Controller PLL Peripheral Clock Tree Analog Module USB Clock Tree USB1.1 PHY HIRC 48MHz HIRC HXT LIRC NOTE: 1. PCLK0 for OPA0~2, 2. PCLK1 for DAC0, ACMP0~1,EADC0 SPI0 SPI0 FMC(Read) ISP PDMA EBI CRC GPIOA~F AHBCL K CLKDIV x SRAM APBCL Kx 48MHz PLL HIRC HXT PCLKx One per module APBCL Kx One per module APBCL Kx One per UART module APBCL Kx One per module APBCL Kx One per module APBCL Kx One per TMR module APBCLK x OPA0~2 APBCLK x HCLKDIV /1 ~ 16 CLKDI Vx PCLK0 PCLK0SEL /1,2,4,8,16 CLKSE Lx PCLK1SEL /1,2,4,8,16 CLKSE Lx PCLK1 SC0DIV /1 ~ 256 CLKDI Vx SC0 SC0 UART0DIV /1 ~ 16 CLKDI Vx
3 UART0
UART0~2 TMR0 TMR0~3 xxxx NOTE: : xxxx is register name AHBCLK e.g. : AHBCLK register settings CLKDIVx : CLKDIV0 ~ 4 register settings LXT RTC w/ Tamper detection HCLK for APB0 Peripheral Clock for APB1 Peripheral Clock APBCLK x WDT APBCLK x /2048HCLK WWDT APBCL Kx HIRC HCLK LXT HXT CLKO RTC, WDT, WWDT CLKO HCLK T0~T3 NOTE: T0 for TMR0, T1 for TMR1, T2 for TMR2, T3 for TMR3 DAC0 APBCLK x 1Hz from RTC moduleCLKO LXT 32KHz HXT OSC 4-32MHz USBDIV /1 ~ 16 LIRC CPU MIRC 4MHz MIRC HIRC FMC(Write) AHBCL K HIRC BODLIRC LIRC MIRC PSIO APBCL Kx LIRC 38.4KHz PWM0 PWM0~1 BPWM0 BPWM0~1 EADC0 APBCLK x EADCDI V /1 ~ 256 CLKDI Vx NOTE: 1. PCLK0 for QSPI0, SC0, BPWM0, PWM0, USCI0, USCI2, I2C0, UART0, UART2, TMR0~1 2. PCLK1 for SPI_I2S0, PWM1, BPWM1, USCI1, I2C1, TMR2~3, UART1, PSIO QSPI0 PLL HIRC HXT PCLKx LIRC LXT PSIODIV /1 ~ 256 CLKDI Vx SOF HCLK I2C0~1 Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2 Clock Generator
The clock generator consists of 6 clock sources, which are listed below: 32.768 kHz external low speed crystal oscillator (LXT) 4~32 MHz external high speed crystal oscillator (HXT) Programmable PLL output clock frequency (PLLFOUT) - PLL source can be selected from external 4~32 MHz external high speed crystal (HXT), 48 MHz internal high speed oscillator (HIRC/4) or 4 MHz internal medium speed oscillator (MIRC) 48 MHz internal high speed RC oscillator (HIRC) 38.4 kHz internal low speed RC oscillator (LIRC) 4 MHz internal medium speed oscillator (MIRC) XT1_OUT External 4~32 MHz Crystal (HXT) HXTEN (CLK_PWRCTL[0]) XT1_IN Internal 48 MHz Oscillator (HIRC) HIRCEN (CLK_PWRCTL[2]) 00 PLL PLLSRC (CLK_PLLCTL[20:19]) PLL FOUT X32_OUT External 32.768 kHz Crystal (LXT) LXT LXTEN (CLK_PWRCTL[1]) X32_IN Internal 38.4 kHz Oscillator (LIRC) LIRCEN (CLK_PWRCTL[3]) HXT HIRC LIRC Internal 4 MHz Oscillator (MIRC) MIRCEN (CLK_PWRCTL[19]) MIRC /4 11 Figure 6.3-2 Clock Generator Block Diagram
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6.3.3 System Clock and SysTick Clock
The system clock has 6 clock sources, which are generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is show n in Figure 6.3-3 011 010 001 PLLFOUT LXT HXT LIRC HCLKSEL (CLK_CLKSEL0[2:0]) HIRC 000 1/(HCLK_N+1) HCLKDIV (CLK_CLKDIV0[3:0]) CPU in Power Down Mode CPU AHB APB1 CPUCLK HCLK PCLK1 111 1/(HCLK_N+1)1/(HCLKDIV+1) APB0PCLK0 MIRC 101 Figure 6.3-3 System Clock Block Diagram There are two clock fail detectors to observe HXT and LXT clock source and they have individual enable and interrupt control. When HXT detector is enabled, the MIRC clock is enabled automatically. When LXT detector is enabled, the LIRC clock is enabled automatically. When HXT clock detector is enabled, the system clock will auto switch to MIRC if HXT clock stop being detected on the following condition: system clock source comes from HXT or system clock source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is set to 1. User can try to recover HXT by disable HXT and enable HXT again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again. The HXT clock stop detect and system clock switch to MIRC procedure is shown in Figure 6.3-4.
July 2, 2020 Page 164 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Set HXTFDEN To enable HXT clock detector HXTFIF = 1? System clock source = “HXT” or “PLL with HXT” ? YES System clock keep original clockNO YES Switch system clock to MIRC NO Figure 6.3-4 HXT Stop Protect Procedure The clock source of SysTick in Cortex® -M23 core can use CPU clock or external clock (SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLK SEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure 6.3-5. 111 011 010 001 HXT LXT HXT HCLK STCLKSEL (CLK_CLKSEL0[5:3]) STCLK HIRC 000 Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4 Peripherals Clock
The peripherals clock ha s different clock source switch setting, which depends on the different peripheral. Please refer to the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.8.
6.3.5 Power-down Mode Clock
July 2, 2020 Page 165 of 266 Rev 1.01 M251/M252 SERIES DATASHEET When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are disabled. Some clock sources and peripherals clock are still active in Power-down mode. For theses clocks, which still keep active, are listed below: Clock Generator – 38.4 kHz internal low speed RC oscillator (LIRC) clock – 32.768 kHz external low speed crystal oscillator (LXT) clock Peripherals Clock, except for HCLK, PCLK0 and PCLK1(When the modules adopt LXT or LIRC as clock source)
6.3.6 Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by 16 chained divide- by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power -of-2 divided clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider. The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, F out is the clock divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and stays in low state. 0000 0001 1110 1111 16 to 1 MUX FREQSEL (CLK_CLKOCTL[3:0]) CLKO 16 chained divide-by-2 counter CLKOEN (CLK_CLKOCTL[4]) Enable divide-by-2 counter DIV1EN (CLK_CLKOCTL[5]) CLK1HZEN (CLK_CLKOCTL[6])
1 Hz clock from LXT0
RTCSEL(RTC_LXTCTL[7]) /32768 011 HCLK LXT HXT HIRC CLKOSEL (CLK_CLKSEL1[6:4]) 010 001 000 LIRC MIRC 101 100 PLL SOF 111 110 Figure 6.3-6 Clock Output Block Diagram
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6.3.7 USB Clock Source
The clock source of USB 1.0 is generated from 48Mhz HIRC or programmable PLL output. The generated clocks are shown in Figure 6.3-7. USBPLLDIV is the clock divider output frequency, the output formula is (PLLFOUT frequency) / (USBDIV + 1). USB1.1 Device ControllerPLLFOUT HIRC48M /(USBDIV + 1) USBDSEL 1USBPLLDIV Figure 6.3-7 USB Clock Source
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6.4 Flash Memeory Controller (FMC)
6.4.1 Overview
The FMC is equipped with 32/64/128/256 Kbytes on-chip embedded Flash for application . A User Configuration block provides for system initiation. A 4 K bytes loader ROM (LDROM) is used for In - System-Programming (ISP) function. XOM (Execution Only Memory ) setting block to conceal user program in XOM region. A 512 bytes cache with zero wait cycle is used to improve Flash access performance. This chip also supports In -Application-Programming (IAP) function . User switches the code executing without chip reset after the embedded Flash is updated.
6.4.2 Features
Supports 32/64/128/256 Kbytes application ROM (APROM) Supports 4 Kbytes loader ROM (LDROM) Supports 1 XOM (Execution Only Memory) region to conceal user program in APROM Supports 12 bytes User Configuration block to control system initiation. Supports 512 bytes page erase for all embedded Flash Supports 32-bit and multi-word Flash programming function Supports CRC32 checksum calculation function Supports Flash all one verification function Supports embedded SRAM remap to system vector memory Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update embedded Flash memory Supports cache memory to improve Flash access performance and reduce power consumption
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 85 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 85 pins are arranged in 6 ports named as PA, PB, PC, PD, PE, and PF. PA, PB and PE has 16 pins on port. PC has 14 pins on port, PD has 15 pins on port. PF has 8 pins on port. Each of the 85 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins ca n be configured by software individually as Input, Push-pull output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are depending on CIOINI (CONFIG0[10]). Each I/O pin has a very weakly individual pull -up resistor which is about 50 k.
6.5.2 Features
Four I/O modes: – Quasi-bidirectional mode – Push-Pull Output mode – Open-Drain Output mode – Input only with high impendence mode TTL/Schmitt trigger input selectable I/O pin can be configured as interrupt source with edge/level setting Supports High Drive and High Slew Rate I/O mode Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting – CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset – CIOINI = 1, all GPIO pins in input mode after chip reset Support independent pull-up and pull-down control Enabling the pin interrupt function will also enable the wake-up function Improve access efficiency by using single cycle I/O bus
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high -speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a total of 8 channels and each channel can perform transfer between memory and peripherals or between memory and memory.
6.6.2 Features
Supports up to 8 independently configurable channels Supports selectable 2 level of priority (fixed priority or round-robin priority) Supports transfer data width of 8, 16, and 32 bits Supports source and destination address increment size can be byte, half -word, word or no increment Request source can be from software,PSIO , SPI/I2S, UART, USCI, EADC,DAC,PWM capture event and TIMER Supports Scatter-gather mode to perform sophisticated transfer through the use of the descriptor link list table Supports single and burst transfer type Supports time-out function on channel 0 and channel1 Supports stride function from channel 0 to channel 5
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes four 32 -bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. T he timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. The timer controller also provides four PWM generators. Each PWM ge nerator supports one PWM output and two selectable PWM output channels (TMx or TMx_EXT). The output state of PWM output pin can be control by polarity control, output enable control and output channel select.
6.7.2 Features
Timer Function Features 6.7.2.1 Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale counter Independent clock source for each timer Provides one-shot, periodic, toggle-output and continuous counting operation modes 24-bit up counter value is readable through CNT (TIMERx_CNT[23:0]) Supports event counting function 24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0]) Supports external capture pin (TMx_EXT) event for interval measurement Supports external capture pin (TMx_EXT) event to reset 24-bit up counter Supports internal clock (HIRC, LIRC, MIRC) and external clock (HXT, LXT) for capture event Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger BPWM, PWM, EADC, DAC and PDMA function Supports internal capture triggered while internal ACMP output signal transition Supports Inter-Timer trigger mode Supports event counting source from internal USB SOF signal PWM Function Features 6.7.2.2 Supports PWM generator with two selectable output channels Supports 16-bit PWM counter – Up count operation type – One-shot or auto-reload counter operation mode Supports 8-bit prescale from 1 to 256 Supports 16-bit compare register and period register and double buffer for period register and compare register Supports tri-state enable and polarity control for each PWM selectable output channels Supports interrupt on the following events: – PWM period point, up-count compared point events
July 2, 2020 Page 171 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports wake-up when interrupt occurs when clock source is LXT or LIRC PWM can generator output in power down mode Supports trigger EADC, PDMA, and DAC on the following events: – PWM period point and up-count compared point events
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs i nto an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Wat chdog Timer supports the function to wake up system from Idle/Power-down mode.
6.8.2 Features
20-bit free running up counter for WDT time-out interval Selectable time-out interval (24 ~ 220) and the time-out interval is 417us ~ 27. 3 s if WDT_CLK = 38.4 kHz (LIRC). System kept in reset state for a period of (1 / WDT_CLK) * 63 Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset delay period Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in Config0 register Supports WDT time-out wake-up function only if WDT clock source is selected as 38.4 kHz LIRC or LXT.
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software running to uncontrollable status by any unpredictable condition.
6.9.2 Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value (CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit prescale counter period of WWDT counter WWDT counter suspends in Idle/Power-down mode
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6.10 Real Time Clock (RTC)
6.10.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy.
6.10.2 Features
Supports external power pin V BAT. Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in RTC_CAL (year, month, day) for RTC time and calendar check. Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in RTC_TALM and RTC_CALM. Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in RTC_TAMSK and RTC_CAMSK. Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register. Supports Leap Year indication in RTC_LEAPYEAR register. Supports Day of the Week counter in RTC_WEEKDAY register. Frequency of RTC clock source compensate by RTC_FREQADJ register. All time and calendar message expressed in BCD format. Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second. Supports RTC Time Tick and Alarm Match interrupt. Supports 1 Hz clock output. Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated. Supports Daylight Saving Time software control in RTC_DSTCTL. Supports one tamper pin. Supports 20 bytes spare registers and tamper-pin detection to clear the content of these spare registers.
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6.11 Basic PWM Generator and Capture Timer (BPWM)
6.11.1 Overview
The chip provides two BPWM generators. Each BPWM supports 6 channels of BPWM output or input capture. There is a 12 -bit prescaler to support flexible clock to the 16 -bit BPWM counter with 16 -bit comparator. The BPWM counter supports up, down and up -down counter types , all 6 channels share one counter . BPWM uses the comparator compared with counter to generate events. These events are used to generate BPWM pulse, interrupt and trigger signal for EADC to start conv ersion. For BPWM output control unit, it supports polarity output, independent pin mask and tri-state output enable. The BPWM generator also supports input capture function to latch BPWM counter value to corresponding register when input channel has a risi ng transition, falling transition or both transition is happened.
6.11.2 Features
BPWM Function Features 6.11.2.1 Supports maximum clock frequency up to maximum PLL frequency. Supports up to two BPWM modules; each module provides 6 output channels Supports independent mode for BPWM output/Capture input channel Supports 12-bit prescalar from 1 to 4096 Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter – Up, down and up/down counter operation type Supports mask function and tri-state enable for each BPWM pin Supports interrupt in the following events: – BPWM counter matches 0, period value or compared value Supports trigger EADC in the following events: – BPWM counter matches 0, period value or compared value Capture Function Features 6.11.2.2 Supports up to 12 capture input channels with 16-bit resolution Supports rising or falling capture condition Supports input rising/falling capture interrupt Supports rising/falling capture with counter reload option
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6.12 PWM Generator and Capture Timer (PWM)
6.12.1 Overview
The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of PWM output or input capture. There is a 12 -bit prescaler to support flexible clock to the 16 -bit PWM counter with 16 -bit compa rator. The PWM counter supports up, down and up -down counter types. PWM uses comparator compared with counter to generate events. These events use to generate PWM pulse, interrupt and trigger signal for ADC to start conversion. The PWM generator supports t wo standard PWM output modes: Independent mode and Complementary mode, they have difference architecture. In Complementary mode , there are two comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control unit, it supports polarity output, independent pin mask and brake functions. The PWM generator also supports input capture function to latch PWM counter value to the corresponding register when input channel has a rising transition, falling transition or both transition is happened. Capture function also support PDMA to transfer captured data to memory.
6.12.2 Features
PWM function features 6.12.2.1 Supports maximum clock frequency up to maximum PLL frequency Supports up to two PWM modules, each module provides 6 output channels Supports independent mode for PWM output/Capture input channel Supports complementary mode for 3 complementary paired PWM output channel – Dead-time insertion with 12-bit resolution – Two compared values during one period Supports 12-bit prescaler from 1 to 4096 Supports 16-bit resolution PWM counter – Up, down and up/down counter operation type Supports mask function and tri-state enable for each PWM pin Supports brake function – Brake source from pin and system safety events (clock failed, Brown-out detection and CPU lockup) – Noise filter for brake source from pin – Edge detect brake source to control brake state until brake interrupt cleared – Level detect brake source to auto recover function after brake condition removed Supports interrupt on the following events: – PWM counter matches 0, period value or compared value – Brake condition happened Supports trigger ADC on the following events: – PWM counter matches 0, period value or compared value
6.12.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
July 2, 2020 Page 177 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports rising or falling capture condition Supports input rising/falling capture interrupt Supports rising/falling capture with counter reload option Supports PDMA transfer function for PWM all channels
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6.13 UART Interface Controller (UART)
6.13.1 Overview
The chip provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The UART controller performs Normal Speed UART and supports flow control function. The UART controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel - to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN , RS-485 and Single-wire function modes and auto-baud rate measuring function.
6.13.2 Features
Full-duplex asynchronous communications Separates receive and transmit 16/16 bytes entry FIFO for data payloads Supports hardware auto-flow control Programmable receiver buffer trigger level Supports programmable baud rate generator for each channel individually Supports nCTS, incoming data, Received Data FIFO reached threshold and RS -485 Address Match (AAD mode) wake-up function Supports 8-bit receiver buffer time-out detection function Programmable transmitting data delay time between the last stop and the next START bit by setting DLY (UART_TOUT [15:8]) Supports Auto-Baud Rate measurement and baud rate compensation function – Support 9600 bps for UART_CLK is selected LXT. Supports break error, frame error, parity error and receive/transmit buffer overflow detection function Fully programmable serial-interface characteristics – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable PARITY bit, even, odd, no parity or stick PARITY bit generation and detection – Programmable STOP bit, 1, 1.5, or 2 STOP bit generation Supports IrDA SIR function mode – Supports for 3/16 bit duration for normal mode Supports LIN function mode (Only UART0 with LIN function) – Supports LIN master/slave mode – Supports programmable break generation function for transmitter – Supports break detection function for receiver Supports RS-485 function mode – Supports RS-485 9-bit mode – Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction Supports PDMA transfer function Support Single-wire function mode.
July 2, 2020 Page 179 of 266 Rev 1.01 M251/M252 SERIES DATASHEET UART Feature UART0 UART1/UART2 SC_UART USCI-UART FIFO 16 Bytes 16 Bytes 4 Bytes TX: 1byte RX: 2byte Auto Flow Control (CTS/RTS) √ √ - √ IrDA √ √ - - LIN √ - - - RS-485 Function Mode √ √ - √ nCTS Wake-up √ √ - √ Incoming Data Wake-up √ √ - √ Received Data FIFO reached threshold Wake-up √ √ - - RS-485 Address Match (AAD mode) Wake-up √ √ - - Auto-Baud Rate Measurement √ √ - √ STOP bit Length 1, 1.5, 2 bit 1, 1.5, 2 bit 1, 2 bit 1, 2 bit Word Length 5, 6, 7, 8 bits 5, 6, 7, 8 bits 5, 6, 7, 8 bits 6~13 bits Even / Odd Parity √ √ √ √ Stick Bit √ √ - - Note: √= Supported Table 6.13-1 UART Feature List
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6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816 -3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.14.2 Features
ISO 7816-3 T = 0, T = 1 compliant EMV2000 compliant One ISO 7816-3 port Separates receive/transmit 4 byte entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 267 ETU) One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times processing Supports auto direct / inverse convention function Supports transmitter and receiver error retry and error number limiting function Supports hardware activation sequence process, and the time between PWR on and CLK start is configurable Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detected the card removal Supports UART mode – Full duplex, asynchronous communications – Separates receiving / transmitting 4 bytes entry FIFO for data payloads – Supports programmable baud rate generator – Supports programmable receiver buffer trigger level – Programmable transmitting data delay time between the last stop bit leaving the TX- FIFO and the de-assertion by setting EGT (SCn_EGT[7:0]) – Programmable even, odd or no parity bit generation and detection – Programmable stop bit, 1- or 2- stop bit generation
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6.15 Serial Peripheral Interface (SPI)
6.15.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4 -wire bi-direction interface. The chip contains one of SPI controller performing a serial -to-parallel conversion on data received from a peripheral device, and a parallel -to-serial conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a master or a slave device and supports the PDMA function to access the data buffer. Each SPI controller also supports I2S mode to connect external audio CODEC.
6.15.2 Features
SPI Mode – Support one SPI controller – Supports Master or Slave mode operation – Configurable bit length of a transaction word from 8 to 32-bit – Provides separate 4-level depth transmit and receive FIFO buffers – Supports MSB first or LSB first transfer sequence – Supports Byte Reorder function – Supports Byte or Word Suspend mode – Supports PDMA transfer – Supports one data channel half-duplex transfer – Supports receive-only mode I2S Mode – Supports Master or Slave – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving – Supports monaural and stereo audio data – Supports PCM mode A, PCM mode B, I2S and MSB justified data format – Supports two PDMA requests, one for transmitting and the other for receiving
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6.16 Quad Serial Peripheral Interface (QSPI)
6.16.1 Overview
The Quad Serial Peripheral Interface ( QSPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4 -wire bi -direction interface. The chip contains one QSPI controller performing a serial -to-parallel conversion on data received from a peripheral device, and a parallel -to-serial conversion on data transmitted to a peripheral device. The QSPI controller supports 2 -bit Transfer mode to perform full -duplex 2-bit data transfer and also supports Dual and Quad I/O Transfer mo de and the controller supports the PDMA function to access the data buffer.
6.16.2 Features
Supports one QSPI controller Supports Master or Slave mode operation Supports 2-bit Transfer mode Supports Dual and Quad I/O Transfer mode Configurable bit length of a transaction word from 8 to 32-bit Provides separate 8-level depth transmit and receive FIFO buffers Supports MSB first or LSB first transfer sequence Supports Byte Reorder function Supports Byte or Word Suspend mode Supports PDMA transfer Supports 3-Wire, no slave selection signal, bi-direction interface Supports one data channel half-duplex transfer Supports receive-only mode
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6.17 I2C Serial Interface Controller (I2C)
6.17.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient metho d of data exchange between devices. The I 2C standard is a true multi -master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. There are two sets of I2C controllers that support Power-down wake-up function.
6.17.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the I2C bus include: Supports up to two I2C ports Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps) Arbitration between simultaneously transmitting masters without corruption of se rial data on the bus Serial clock synchronization allow devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflow Programmable clocks allow for versatile rate control Supports 7-bit addressing and 10-bit addressing mode Supports multiple address recognition ( four slave address with mask option) Supports Power-down wake-up function Supports PDMA with one buffer capability Supports setup/hold time programmable Supports Bus Management (SM/PM compatible) function.
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6.18 USCI - Universal Serial Control Interface Controller (USCI)
6.18.1 Overview
The Uni versal Serial Control Interface (USCI) is a flexible interface module covering several serial communication protocols. The user can configure this controller as UART, SPI, or I 2C functional protocol.
6.18.2 Features
The controller can be individually configured t o match the application needs. The following protocols are supported: UART SPI I2C
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6.19 USCI – UART Mode
6.19.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous data frames. It performs a serial -to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the c ontroller. The receiver and transmitter being independent, frames can start at different points in time for transmission and reception. The UART controller also provides auto flow control. There are three conditions to wake -up the system.
6.19.2 Features
Supports one transmit buffer and two receive buffer for data payload Supports hardware auto flow control function Supports programmable baud-rate generator Support 9-bit Data Transfer (Support 9-bit RS-485) Baud rate detection possible by built-in capture event of baud rate generator Supports PDMA capability Supports Wake-up function (Data and nCTS Wakeup Only)
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6.20 USCI - SPI Mode
6.20.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full duplex transfer. It supports b oth master and Slave operation mode with the 4 -wire bi -direction interface. SPI mode of USCI controller performs a serial -to-parallel conversion on data received from a peripheral device, and a parallel -to-serial conversion on data transmitted to a periphe ral device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1 This SPI protocol can operate as master or Slave mode by setting the SLAVE ( USPI_PROTCTL[0]) to communicate with the off -chip SPI Slave or master device. The application block diagrams i n master and Slave mode are shown below. Figure 6.20-1 SPI Master Mode Application Block Diagram Figure 6.20-2 SPI Slave Mode Application Block Diagram
6.20.2 Features
Configurable bit length of a transfer word from 4 to 16-bit Supports one transmit buffer and two receive buffers for data payload Supports MSB first or LSB first transfer sequence Supports Word Suspend function Supports PDMA transfer SPI Slave Device Master Transmit Data Master Receive Data Serial Bus Clock Slave Select SPI_MOSI (USCIx_DAT0) SPI_MISO (USCIx_DAT1) SPI_CLK (USCIx_CLK) SPI_SS (USCIx_CTL) SPI_MOSI SPI_MISO USCI SPI MasterUSCI SPI Master SPI_CLK SPI_SS Note: x = 0, 1, 2 SPI Master Device Slave Receive Data Slave Transmit Data Serial Bus Clock Slave Select SPI_MOSI (USCIx_DAT0) SPI_MISO (USCIx_DAT1) SPI_CLK (USCIx_CLK) SPI_SS (USCIx_CTL) SPI_MOSI SPI_MISO USCI SPI SlaveUSCI SPI Slave SPI_CLK SPI_SS Note: x = 0, 1, 2
July 2, 2020 Page 187 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports 3-wire, no slave select signal, bi-direction interface Supports wake-up function by slave select signal in Slave mode Supports one data channel half-duplex transfer
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6.21 USCI - I2C Mode
6.21.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte -by-byte basis. Each data byte is 8 -bit. There is one SCL clock pulse for each data bit with the MSB being transmitted first, an d an acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure 6.21-1 for more detailed I2C BUS Timing. tBUF STOP SDA SCL START tHD_STA tLOW tHD_DAT tHIGH tf tSU_DAT Repeated START tSU_STA tSU_STO STOP tr Figure 6.21-1 I2C Bus Timing The device’s on -chip I 2C provides the serial interface that meets the I 2C bus standard mode specification. The I 2C port handles byte transfers autonomously. The I 2C mode is selected by FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I 2C bus via two pins: SDA and SCL. When I/O pins are used as I 2C ports, user must set the pins function to I 2C in advance. Note: Pull-up resistor is need ed for I 2C operation because the SDA and SCL are set to open -drain pins when USCI is selected to I2C operation mode.
6.21.2 Features
Full master and slave device capability Supports of 7-bit addressing, as well as 10-bit addressing Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s) Supports multi-master bus Supports one transmit buffer and two receive buffer for data payload Supports 10-bit bus time-out capability Supports bus monitor mode. Supports Power down wake-up by data toggle or address match Supports setup/hold time programmable Supports multiple address recognition (two slave address with mask option)
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6.22 Programmable Serial IO (PSIO)
6.22.1 Overview
Programmable Serial I /O (PSIO) provides a simple way to implement simple serial signal pr occesing, e.g. UART and IR. The PSIO can control when the pin will output high or low and how long the pin need to output high or low. It also provides the easy way to sample the pin state.
6.22.2 Features
Supports up to 8 PSIO pins, from PSIO pin0 to PSIO pin7 Supports 6 clock sources, they are HXT, LXT, HIRC, LIRC, PLL, PCLK1 Supports one clock divider, which can be divided from 1 to 255 Supports slot controller for timing sequence control – Supports 4 slot controllers, 8 slots in each slot controller – Supports counting from 1 PSIO clock to 15 PSIO clocks in each slot – Supports 3 slot repeat modes: Normal repeat mode Normal repeat mode with infinity loops Whole repeat mode – Supports 4 slot trigger conditions: Triggered by software Triggered by falling edge Triggered by rising edge Triggered by rising edge or falling edge Supports PSIO PIN for pin state control – Supports 8 check points to connect with slots in each pin – Supports 8 check point actions in each check point. – Supports 7 kinds of check point action to setting Output high Output low Output data Output toggle Input data Input status Input status update – Supports 4 I/O modes, input, output, open-drain, and quasi – Supports switch I/O mode in different check points Supports 4 kinds of Interrupt trigger conditions – Two sets of configurable slot interrupt controllers – Mismatch interrupt when PSIO is enabled with PDMA
July 2, 2020 Page 190 of 266 Rev 1.01 M251/M252 SERIES DATASHEET – Transfer Error interrupt – Slot controller counting done interrupt Supports PDMA function 011 010 001 000 LXT HXT PLL PSIO Controller PSIO_CLK Clock Controller PSIOSEL PSIOSEL CLKSEL2[30:28] CLKDIV1[31:24] CLK_APBCLK1[31] PSIODIV PSIOCKEN 1/(PSIODIV+1) PSIOCKEN PCLK1 100LIRC 111HIRC Figure 6.22-1 PSIO Clock Control Diagram (8-bit Pre-scale Counter in Clock Controller)
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6.23 External Bus Interface (EBI)
6.23.1 Overview
This chip is equipped with an external bus interfac e (EBI) for external device use . To save the connections between an external device and a chip, EBI is operating at address bus and data bus multiplex mode. The EBI supports three chip selects that can connect three external devices with different timing setting requirements.
6.23.2 Features
Supports up to three memory banks Supports dedicated external chip select pin with polarity control for each bank Supports accessible space up to 1 Mbytes for each bank, actually external addressable space is dependent on package pin out Supports 8-/16-bit data width Supports byte write in 16-bit data width mode Supports Address/Data multiplexed Mode Supports Timing parameters individual adjustment for each memory block Supports LCD interface i80 mode Supports PDMA mode Supports variable external bus base clock (MCLK) which based on HCLK Supports configurable idle cycle for different access condition: Idle of Write command finish (W2X) and Idle of Read-to-Read (R2R)
July 2, 2020 Page 192 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 6.24 USB 1.1 Device Controller (USBD)
6.24.1 Overview
There is one set of USB 2.0 full -speed device controller and transceiver in this device. It is compliant with USB 2.0 full -speed device specification and support s control/bulk/interrupt/isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 1 Kbytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer throu gh buffer segmentation register (USBD_BUFSEGx). There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. There are five different interrupt events in this contr oller. They are the no-event-wake-up, device plug- in or plug -out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register ( USBD_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register ( USBD_EPSTS0 and USBD_EPSTS1 ) to acknowledge what kind of event occurring in this endpoint. A software -disconnect function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller will force the output of USB_D + and USB_D- to level low and its function is di sabled. After disable the SE0 bit, host will enumerate the USB device again. For more information on the Universal Serial Bus , please refer to Universal Serial Bus Specification Revision 1.1.
6.24.2 Features
Compliant with USB 2.0 Full-Speed specification Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET, USB and BUS) Supports Control/Bulk/Interrupt/Isochronous transfer type Supports suspend function when no bus activity existing for 3 ms Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 1 Kbytes buffer size Provides remote wake-up capability
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6.25 CRC Controller (CRC)
6.25.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with f our common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.25.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 – CRC-CCITT: X16 + X12 + X5 + 1 – CRC-8: X8 + X2 + X + 1 – CRC-16: X16 + X15 + X2 + 1 – CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 Programmable seed value Supports programmable order reverse setting for input data and CRC checksum Supports programmable 1’s complement setting for input data and CRC checksum Supports 8/16/32-bit of data width – 8-bit write mode: 1-AHB clock cycle operation – 16-bit write mode: 2-AHB clock cycle operation – 32-bit write mode: 4-AHB clock cycle operation Supports using PDMA to write data to perform CRC operation
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6.26 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.26.1 Overview
The chip contains one 12 -bit successive approximation analog -to-digital converter (SAR ADC converter) with 16 external input channels and 3 internal channels. The ADC converter can be started by software trigger, PWM0/1 triggers, BPWM0/1 triggers, Timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0_ST) input signal.
6.26.2 Features
Analog input voltage range: 0~VREF (Max to AVDD) Reference voltage from VREF pin or AVDD 12-bit resolution and 10-bit accuracy is guaranteed Up to 16 single-end analog external input channels 3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP), and Battery power (VBAT/4) Four EADC interrupts (ADINT0~3) with individual interrupt vector addresses Maximum EADC clock frequency is 16 MHz Up to 880 kSPS conversion rate Configurable EADC internal sampling time. Up to 19 sample modules: – Each of sample is configurable for EADC converter channel EADC_CH0~15 and trigger source – Sample module 16~18 is fixed for EADC channel 16, 17, 18 input sources as band- gap voltage, temperature sensor, and battery power (VBAT/4) – Configurable sampling time for each sample module – Support left-adjusted result – 12-bit resolution for conversion result and 16-bit resolution for accumulated conversion result – Conversion results are held in 19 data registers with valid and overrun indicators – Averaging (2n times, n=0~8) to support up to 12-bit result and over-sampling, or called Accumulation, (2n times, n=0~8) to support up to 16-bit result An ADC conversion can be started by: – Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18) – External pin EADC0_ST – Timer0~3 overflow pulse triggers – ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers – PWM0/1 triggers – BPWM0/1 triggers Supports configurable PDMA transfer Auto turn on/off EADC power at power off or operation mode with wait state(10us stable time)
July 2, 2020 Page 195 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Supports digital comparator to monitor conversion result and user can select whether to generate an interrupt when conversion result matches the compare register setting Supports offset cancellation
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6.27 Digital to Analog Converter (DAC)
6.27.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12-or 8- bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a voltage output buffer that can be used to reduce output im pendence and drive external loads directly without having to add an external operational amplifier.
6.27.2 Features
Analog output voltage range: 0~AVDD. Supports 12-or 8-bit output mode. Rail to rail settle time 6us. Supports up to one 12-bit 1 MSPS voltage type DAC. Reference voltage from internal reference voltage (INT_VREF), VREF pin. DAC maximum conversion updating rate 1 MSPS. Supports voltage output buffer mode and bypass voltage output buffer mode. Supports software and hardware trigger, including Timer0~3 and external trigger pin to start DAC conversion. Supports PDMA mode.
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6.28 Analog Comparator Controller (ACMP)
6.28.1 Overview
The chip provide s two comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. Each comparator can be configured to generate an interrupt when the comparator output value changes.
6.28.2 Features
Analog input voltage range: 0 ~ AVDD Up to two rail-to-rail analog comparators Supports hysteresis function – Supports programmable hysteresis window: 0mV, 10mV, 20mV and 30mV Supports wake-up function Supports programmable propagaion speed and low power consumption Selectable input sources of positive input and negative input ACMP0 supports: – 4 multiplexed I/O pins at positive sources: ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3 – 4 negative sources: ACMP0_N Comparator Reference Voltage (CRV) Internal band-gap voltage (VBG) DAC0 output (DAC0_OUT) ACMP1 supports: – 4 multiplexed I/O pins at positive sources: ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3 – 4 negative sources: ACMP1_N Comparator Reference Voltage (CRV) Internal band-gap voltage (VBG) DAC0 output (DAC0_OUT) Shares one ACMP interrupt vector for all comparators Interrupts generated when compare results change (Interrupt event condition is programmable) Supports triggers for break events and cycle-by-cycle control for PWM Supports window compare mode and window latch mode
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6.29 OP Amplifier (OPA)
6.29.1 Overview
This chip is equipped with one operational amplifier. The OP amplifier outputs is connected to ADC channel for measurement requirement. The OP amplifier circuit can also be used in the application of Programmable Gain Amplifier (PGA).
6.29.2 Features
Analog input voltage range: 0~AVDD. Supports up to 1 operational amplifier Supports to use schmitt trigger buffer output for simple comparator function. Supports schmitt trigger buffer output interrupts.
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6.30 Peripherals Interconnection
6.30.1 Overview
Some peripherals have interconnections which allow autonomous communication or s ynchronous action between peripherals without needing to involve the CPU . Peripherals interact without CPU saves CPU resources, reduces power consumption, operates with no software latency and fast responds.
6.30.2 Peripherals Interconnect Matrix table
Clock Fail - - - - - 14 - - CPU Lockup - - - - - 14 - - Internal External Pin 1, 2 - 5, 6 8, 9, 10 - 14 - - PWM - 3 - 11 - 14, 15 - 19 Timer - 4 7 12 - 16 - - USB 1.1 Device - - - 13 - 18 - Table 6.30-1 Peripherals Interconnect Matrix table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
0.1uF*N AVDD AVSS 10uF+0.1uF 1uF+0.1uF+0.01uF EXT_PWR EXT_VSS as close to VDD/VDDIO/VBAT as possible as close to the EXT_PWR as possible as close to AVDD as possible LDO_CAP 1uF VSS as close to LDO as possible VREF L=30Z L=30Z as close to VREF as possible 2.2uF+1uF+470pFL=30Z L=30Z VBAT 0.1uF VSS
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7.2 Peripheral Application Scheme
4~24 MHz crystal XT1_OUT XT1_IN VDD VSS nRESET ICE_DAT ICE_CLKSWD Interface X32_OUT X32_IN LDO_CAP 1 uF Reset Circuit USB Full Speed Slot USB_D- USB_D+ USB_VCC33_CAP USB_VBUS 20pF 20pF 20pF 20pF 10K 32.768 kHz crystal Addr[15:0] nCE nOE Data[15:0] nWE 64K x 16-bit SRAM LATCH En DQ nLB nUB ALE nCS nRD nWR nWRL nWRH AD[15:0] EBI 27R 27R 1uF 100K100K DVCC VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC I2C Device I2C_SDA I2C_SCL DVCC DVCC 4.7 K 4.7 K VDD VSS CLK DIO RS 232 Transceiver PC COM Port UART UART_RXD UART_TXD ROUT TIN RIN TOUT Line In Line Out SPI_I2SMCLK SPI_CLK(I2S_BCLK) SPI_SS (I2S_LRCLK) SPI_MOSI (I2S_DO) SPI_MISO (I2S_DI) Audio codec Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin. Note 2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. Note 3: It is recommended to use 10Ω series resistor on USB_VBUS pin.
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The limiting values are stress ratings only and cannot be used to functional operation of the device. Exposure to the absolute maximum ratings ma y affect device reliability and proper operation is not guaranteed.
8.1.1 Voltage Characteristics
Symbol Description Min Max Unit VDD-VSS [*1] DC power supply -0.3 6.5 V VDDIO-VSS [*1] VDDIO Power Supply -0.3 6.5 V VBAT-VSS [*1] VBAT Power Supply -0.3 6.5 V ΔVDD Variations between different VDD power pins - 50 mV |VDD –AVDD| Allowed voltage difference for VDD and AVDD - 50 mV ΔVSS Variations between different ground pins - 50 mV |VSS - AVSS| Allowed voltage difference for VSS and AVSS - 50 mV VIN Input voltage on any other pin[*2] VSS-0.3 6.5 V Note: 1. All main power (VDD, VDDIO, VBAT, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply. 2. Refer to Table 8.1-2 for the values of the maximum allowed injected current. Table 8.1-1 Voltage Characteristics
8.1.2 Current Characteristics
Symbol Description Min Max Unit ΣIDD [*1] Maximum current into VDD - 200 mA IDDIO / IBAT Maximum current into VDDIO / IBAT - 100 / 100 ΣISS Maximum current out of VSS - 100 IIO Maximum current sunk by a I/O Pin - 20 Maximum current sourced by a I/O Pin - 20 Maximum current sunk by total I/O Pins[*2] - 100 Maximum current sourced by total I/O Pins[*2] - 100 IINJ(PIN) [*3] Maximum injected current by a I/O Pin - ±5 ΣIINJ(PIN) [*3] Maximum injected current by total I/O Pins - ±25 Note: 1. Maximum allowable current is a function of device maximum power dissipation. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins. 3. A positive injection is caused by V IN>AVDD and a negative injection is caused by V IN<VSS. I INJ(PIN) must never be exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
July 2, 2020 Page 203 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Table 8.1-2 Current Characteristics
8.1.3 Thermal Characteristics
The average junction temperature can be calculated by using the following equation: TJ = TA + (PD x θJA ) TA = ambient temperature (℃) θJA = thermal resistance junction-ambient (℃/Watt) PD = sum of internal and I/O power dissipation Symbol Description Min Typ Max Unit TA Operating ambient temperature -40 - 105 ℃ TJ Operating junction temperature -40 - 125 TST Storage temperature -65 - 150 θJA [*1] Thermal resistance junction-ambient 20-pin TSSOP(4.4x6.5 mm) - 38 - ℃/Watt Thermal resistance junction-ambient 28-pin TSSOP(4.4x9.7 mm) - 30 - ℃/Watt Thermal resistance junction-ambient 33-pin QFN(5x5 mm) - 39.6 - ℃/Watt Thermal resistance junction-ambient 48-pin LQFP(7x7 mm) - 60 - ℃/Watt Thermal resistance junction-ambient 64-pin LQFP(7x7 mm) - 58 - ℃/Watt Thermal resistance junction-ambient 128-pin LQFP(14x14 mm) - 38.5 - ℃/Watt Note: 1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Table 8.1-3 Thermal Characteristics
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8.1.4 EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high -frequency trasnients bursts of narrow high-frequency transients on the power distribution system.. Inductive loads: – Relays, switch contactors – Heavy-duty motors when de-energized etc. The fast transient immunity requirements for electronic products are defined in IEC 61000 -4-4 by International ElectrotechnicalCommission (IEC). Symbol Description Min Typ Max Unit VHBM [*1] Electrostatic discharge,human body mode -6000 - +6000 V VCDM [*2] Electrostatic discharge,charge device model -1000 - +1000 LU[*3] Pin current for latch-up[*3] -150 - +150 mA VEFT [*4] [*5] Fast transient voltage burst -4.4 - +4.4 kV Note: 1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) – Component Level 2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing – Charged Device Model (CDM) – Component Level. 3. Determined according to JEDEC EIA/JESD78 standard. 4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test. 5. The performace cretia class is 4A. Table 8.1-4 EMC Characteristics for M251xC/M251xD/M252xC/M252xD
July 2, 2020 Page 205 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Description Min Typ Max Unit VHBM [*1] Electrostatic discharge,human body mode -6000 - +6000 V VCDM [*2] Electrostatic discharge,charge device model -500 - +500 LU[*3] Pin current for latch-up[*3] -150 - +150 mA VEFT [*4] [*5] Fast transient voltage burst -4.4 - +4.4 kV Note: 1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) – Component Level 2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing – Charged Device Model (CDM) – Component Level. 3. Determined according to JEDEC EIA/JESD78 standard. 4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test. 5. The performace cretia class is 4A. Table 8.1-5 EMC Characteristics for M251xE/M251xG/M252xE/M252xG
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8.1.5 Package Moisture Sensitivity (MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been opened. All Nuvoton surface mount chips have a moisture level classification. The information is also displayed on the bag packing. Pacakge MSL 20-pin TSSOP(4.4x6.5 mm) [*1] MSL 3 28-pin TSSOP(4.4x9.7 mm) [*1] MSL 3 33-pin QFN(5x5 mm) [*1] MSL 3 48-pin LQFP(7x7 mm) [*1] MSL 3 64-pin LQFP(7x7 mm) [*1] MSL 3 128-pin LQFP(14x14 mm) [*1] MSL 3 Note: 1. Determined according to IPC/JEDEC J-STD-020 Table 8.1-6 Package Moisture Sensitivity(MSL)
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8.1.6 Soldering Profile
Figure 8.1-1 Soldering profile from J-STD-020C Porfile Feature Pb Free Package Average ramp-up rate (217℃ to peak) 3℃/sec. max Preheat temperature 150℃ ~200℃ 60 sec. to 120 sec. Temperature maintained above 217℃ 60 sec. to 150 sec. Time with 5℃ of actual peak temperature > 30 sec. Peak temperature range 260℃ Ramp-down rate 6℃/sec ax. Time 25℃ to peak temperature 8 min. max Note: 1. Determined according to J-STD-020C Table 8.1-7 Soldering Profile
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8.2 General Operating Conditions
(VDD-VSS = 1.75 ~ 5.5V, TA = 25C, HCLK = 48 MHz unless otherwise specified.) Symbol Parameter Min Typ Max Unit Test Conditions TA Temperature -40 - 105 ℃ fHCLK Internal AHB clock frequency - - 48 MHz VDD Operation voltage 1.75 - 5.5 V VDDIO VDDIO Operation voltage 1.65 - 5.5 VBAT VBAT Operation voltage 1.75 - 5.5 AVDD [*1] Analog operation voltage VDD VREF Analog reference voltage 1.75 - AVDD VLDO LDO output voltage - 1.5 - VBG Band-gap voltage 795 815 840 mV CLDO [*2] LDO output capacitor on each pin 1 µF RESR [*3] ESR of CLDO output capacitor - - 0.5 Ω IRUSH [*3] InRush current on voltage regulator power-on (POR or wakeup from Standby) - 60 150 mA ERUSH [*3] InRush energy on voltage regulator power-on (POR or wakeup from Standby) - 0.9 - µC VDD = 1.8 V, TA = 105 °C, IRUSH = 60 mA for 15 µs Note: 1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and AVDD can be tolerated during power-on and power-off operation . 2. To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor. Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease output noise and improves the load transient response. 3. Guaranteed by design, not tested in production Table 8.2-1 General Operating Conditions
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8.3 DC Electrical Characteristics
8.3.1 Supply Current Characteristics for M251xC/M251xD/M252xC/M252xD
The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The current consumption is measured as described in below condition and table to inform test characterization result. All GPIO pins are in push pull mode and output high. The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 1.75 ~ 5.5 V unless otherwise specified. VDD = AVDD = VDDIO When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK. Program run CoreMark® code in Flash. Symbol Conditions FHCLK Typ [*1] Max[*1][*2] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_RUN Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 5.4 6.05 6.25 6.45 mA 32 MHz 4.1 4.6 4.8 5.1 24 MHz 3.2 3.65 3.85 4.1 12 MHz 2.0 2.3 2.5 2.8 Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals disable. HCLK is set as MIRC clock. 4 MHz 0.74 0.95 1.15 1.35 2 MHz 0.55 0.75 0.9 1.1 1 MHz 0.45 0.6 0.80 1.0 Normal run mode with PL3 (PLSEL = 11), executed from Flash, all peripherals disable. HCLK is set as LIRC or LXT clock.. Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals enable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 15 16.6 16.8 17 32 MHz 10 11.5 11.8 12 24 MHz 8.0 9.0 9.3 9.5 12 MHz 4.5 5.05 5.3 5.5 Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals enable. HCLK is set as MIRC clock. 4 MHz 1.4 1.65 1.85 2.1 2 MHz 0.95 1.15 1.35 1.6 1 MHz 0.65 0.85 1.1 1.3 Normal run mode with PL3 (PLSEL = 11), executed from Flash, all peripherals enable HCLK is set as LIRC or LXT clock..
July 2, 2020 Page 210 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Note: 1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. Table 8.3-1 Current Consumption in Normal Run Mode Symbol Conditions FHCLK Typ [*1] Max[*1][*2] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_IDLE Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 2.25 2.6 2.8 3.0 mA 32 MHz 2.05 2.4 2.6 2.8 24 MHz 1.6 1.9 2.1 2.3 12 MHz 1.2 1.45 1.65 1.85 Idle mode with PL0 (PLSEL = 00), all peripherals disable. HCLK is set as MIRC clock. 4 MHz 0.47 0.62 0.8 1.0 2 MHz 0.42 0.57 0.77 0.97 1 MHz 0.39 0.53 0.73 0.93 Idle mode with PL3 ( PLSEL = 11), all peripherals disable HCLK is set as LIRC or LXT clock. Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 12 13.3 13.4 13.7 32 MHz 8.1 9.1 9.3 9.5 24 MHz 6.6 7.4 7.6 7.8 12 MHz 3.9 4.4 4.6 4.8 Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as MIRC clock. 4 MHz 1.25 1.5 1.7 1.9 2 MHz 0.8 1.0 1.2 1.4 1 MHz 0.58 0.74 0.95 1.15 Idle mode with PL3 ( PLSEL = 11), all peripherals enable HCLK is set as LIRC or LXT clock. Note: 1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. Table 8.3-2 Current consumption in Idle Mode
July 2, 2020 Page 211 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Test Conditions LXT[*1] 32.768 kHz LIRC 38.4 kHz Typ[*2] Max[*3][*4] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_DPD Deep Power-down mode, all peripherals disable - - 1.45 3.5 15.5 76 µA Deep Power-down mode, RTC enable and run V - 2.0 3.95 16 78 IDD_PD Power-down mode, all peripherals disable - - 1.7 3.7 23.5 128 µA Power-down mode, RTC enable and run V - 2.5 4.55 25 129 Power-down mode, WDT/Timer enable and run - V 3.65 5.65 26 130 Power-down mode, WDT/Timer/UART/RTC enable and run, WDT use LIRC, UART/Timer/RTC use LXT V V 4.3 6.2 26.5 131 IDD_FWPD Fast wake up Power-down mode, all peripherals disable - - 100 140 171 292 µA Fast wake up Power-down mode, RTC enable and run V - 101 141 173 293 Fast wake up Power-down mode, WDT/Timer enable and run - V 102 142 174 295 Fast wake up Power-down mode, WDT/Timer/UART/RTC enable and run, WDT use LIRC, UART/Timer/RTC use LXT V V 103 143 175 296 Note: 1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for L1 gain level 2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled. 3. Based on characterization, not tested in production unless otherwise specified. 4. When analog peripheral blocks such as USB, ADC and ACMP are ON, an additional power consumption should be considered. Table 8.3-3 Chip Current Consumption in Power-down Mode
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8.3.2 Supply Current Characteristics for M251xE/M251xG/M252xE/M252xG
The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The current consumption is measured as described in below condition and table to inform test characterization result. All GPIO pins are in push pull mode and output high. The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 1.75 ~ 5.5 V unless otherwise specified. VDD = AVDD = VDDIO = VBAT When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK. Program runs CoreMark® code in Flash. Symbol Conditions FHCLK Typ [*1] Max[*1][*2] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_RUN Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 6.2 6.95 7.15 7.35 mA 32 MHz 4.55 5.15 5.35 5.65 24 MHz 3.6 4.05 4.25 4.55 12 MHz 2.25 2.55 2.75 3.0 Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals disable. HCLK is set as MIRC clock. 4 MHz 0.74 0.95 1.15 1.35 2 MHz 0.55 0.75 0.9 1.1 1 MHz 0.45 0.6 0.80 1.0 Normal run mode with PL3 (PLSEL = 11), executed from Flash, all peripherals disable. HCLK is set as LIRC or LXT clock.. Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals enable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 17.5 19.5 19.8 20 32 MHz 11.5 13 13.3 13.5 24 MHz 9.5 10.5 10.8 11 12 MHz 5.5 6.1 6.3 6.5 Normal run mode with PL0 (PLSEL = 00), executed from Flash, all peripherals enable. HCLK is set as MIRC clock. 4 MHz 1.6 1.85 2.05 2.3 2 MHz 1.0 1.25 1.45 1.7 1 MHz 0.7 0.95 1.15 1.35 Normal run mode with PL3 (PLSEL = 11), executed from Flash, all peripherals enable HCLK is set as LIRC or LXT clock..
July 2, 2020 Page 213 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Note: 1. When analog peripheral blocks such as ADC, OPA, DAC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. Table 8.3-4 Current consumption in Normal Run Mode Symbol Conditions FHCLK Typ [*1] Max[*1][*2] Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_IDLE Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 2.4 2.75 2.95 3.05 mA 32 MHz 2.25 2.6 2.8 3.0 24 MHz 1.7 1.9 2.1 2.3 12 MHz 1.25 1.5 1.7 1.9 Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as MIRC clock. 4 MHz 0.48 0.62 0.8 1.0 2 MHz 0.42 0.57 0.77 0.97 1 MHz 0.39 0.53 0.73 0.93 Idle mode with PL3 ( PLSEL = 11), all peripherals disable HCLK is set as LIRC or LXT clock. Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as HIRC, PLL or HXT clock. 48 MHz 13 14.5 14.7 14.9 32 MHz 9.2 10.5 10.7 10.9 24 MHz 7.5 8.5 8.7 8.9 12 MHz 4.5 5.1 5.3 5.5 Idle mode with PL0 ( PLSEL = 00), all peripherals disable. HCLK is set as MIRC clock. 4 MHz 1.3 1.55 1.75 1.95 2 MHz 0.85 1.1 1.3 1.5 1 MHz 0.6 0.8 1.0 1.2 Idle mode with PL3 ( PLSEL = 11), all peripherals enable HCLK is set as LIRC or LXT clock. Note: 1. When analog peripheral blocks such as USB, OPA, DAC, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an additional power consumption should be considered. 2. Based on characterization, not tested in production unless otherwise specified. Table 8.3-5 Current Consumption in Idle Mode
July 2, 2020 Page 214 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Test Conditions LXT[*1] 32.768 kHz LIRC 38.4 kHz Typ[*2] Max[*3][*4] Unit TA = 25 TA = 25 TA = 85 °C TA = 105 °C IDD_DPD Deep Power-down mode, all peripherals disable - - 1.4 3.5 16.5 80 µA Deep Power-down mode, RTC enable and run V - 1.9 4.3 TBD TBD IDD_PD Power-down mode, all peripherals disable - - 1.8 3.7 30 155 µA Power-down mode, RTC enable and run V - 2.45 4.7 31 157 Power-down mode, WDT/Timer enable and run - V 3.9 6 32.5 159 Power-down mode, WDT/Timer/UART/RTC enable and run, WDT use LIRC, UART/Timer/RTC use LXT V V 4.5 6.9 34 161 IDD_FWPD Fast wake up Power-down mode, all peripherals disable - - 160 260 315 490 µA Fast wake up Power-down mode, RTC enable and run V - 161 261 316 492 Fast wake up Power-down mode, WDT/Timer enable and run - V 162 262 318 494 Fast wake up Power-down mode, WDT/Timer/UART/RTC enable and run, WDT use LIRC, UART/Timer/RTC use LXT V V 163 263 320 496 Note: 1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for L3 gain level 2. VDD = AVDD = VBAT = 3.3V, LVR17 enabled, POR disabled and BOD disabled. 3. Based on characterization, not tested in production unless otherwise specified. 4. When analog peripheral blocks such as USB, OPA, DAC, ADC and ACMP are ON, an additional power consumption should be considered. Table 8.3-6 Chip Current Consumption in Power-down Mode
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8.3.3 On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = VBAT = 3.3 V unless otherwise specified. All GPIO pins are set as output high of push pull mode without multi-function. HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK. The result value is calculated by measuring the difference of current consumption between all peripherals clocked off and only one peripheral clocked on. The peripheral clock selection keeps reset default setting. Peripheral IDD [*1] Unit EADC[*2] 0.55 mA ACMP01[*3] 0.067 PWM0 0.72 PWM1 0.75 BPWM0 0.36 BPWM1 0.39 WDT/WWDT 0.05 QSPI 0.44 SPI/I2S 0.64 UART0 0.40 UART1 0.34 UART2 0.33 I2C0 0.058 I2C1 0.087 USCI0 0.28 USCI1 0.26 USCI2 0.27 SC0 0.22 PSIO0 0.75 (4 channels) 1.4 (8 channels) EBI 0.12 TMR0 0.28 TMR1 0.30 TMR2 0.29 TMR3 0.26 RTC 0.046
July 2, 2020 Page 216 of 266 Rev 1.01 M251/M252 SERIES DATASHEET USB FS Device[*4] 1.03 CRC 0.045 PDMA 0.57 FMC 0.43 Note: 1. Guaranteed by characterization results, not tested in production. 2. When the ADC is turned on, add an additional power consumption per ADC for the analog part. 3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part. 4. When the USB is turned on, add an additional power consumption per USB for the analog part. Table 8.3-7 Peripheral Current Consumption
8.3.4 Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC oscillator. Symbol Parameter Typ Max Unit tWU_IDLE Wakeup from IDLE mode 5 6 cycles tWU_DPD [*1][*2] Wakeup from deep Power-down mode 190 250 µS tWU_NPD [*1][*2] Wakeup from normal Power-down mode 19 30 tWU_FWPD [*1][*2] Wakeup from fast wake up Power-down mode 12 15 Note: 1. Based on test during characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first Table 8.3-8 Low-power Mode Wakeup Timings
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8.3.5 I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below V SS or above V DD should be avoided during normal product operation. However, the analog compoenent of the MCU is most likely to be affected by the injection current , but it is not easily clarified when abnormal injection accidentally happens. It is recommended to add a S chottky diode (pin to ground or pin to V DD) to pins that include analog function which may potentially injection currents. Symbol Parameter Negative injection Positive injection Unit Test Condition IINJ(PIN) Injected current by a I/O Pin -0 0 mA Injected current on nReset pins -0 0 Injected current on PF2~PF5, PA10, PA11 and PB0~PB15 for analog input function -5 +5 Injected current on any other I/O except analog input pin Table 8.3-9 I/O Current Injection Characteristics
8.3.6 I/O DC Characteristics
8.3.6.1 PIN Input Characteristics
Symbol Parameter Min Typ Max Unit Test Conditions VIL Input low voltage (Schmitt trigger) 0 - 0.3*VDD V Input low voltage (TTL trigger) 0 - 0.8 VDD = 4.5 V 0 - 0.7 VDD = 2.7 V 0 - 0.5 VDD = 1.8 V VIH Input high voltage (Schmitt trigger) 0.7*VDD - VDD V Input high voltage (TTL trigger) 2 - VDD VDD = 5.5 V 1.5 - VDD VDD = 3.3 V 0.8 - VDD VDD = 1.8 V VHY [*1] Hysteresis voltage of schmitt input - 0.2*VDD - V ILK [*2] Input leakage current -1 - 1 VSS < VIN < VDD, Open-drain or input only mode -1 - 1 VDD < VIN < 5 V, Open-drain or input only mode on any other 5v tolerance pins RPU [*1] Pull up resistor 45 52 57 kΩ RPD [*1] Pull down resistor 45 52 57 kΩ Note: 1. Guaranteed by characterization result, not tested in production. 2. Leakage could be higher than the maximum value, if abnormal injection happens. Table 8.3-10 I/O Input Characteristics
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8.3.6.2 I/O Output Characteristics
Symbol Parameter Min Typ Max Unit Test Conditions ISR [*1] [*2] Source current for quasi- bidirectional mode and high level -7.5 -7.75 -8 µA VDD = 4.5 V VIN=(VDD-0.4) V -7.4 -7.7 -8 µA VDD = 2.7 V VIN=(VDD-0.4) V -7.2 -7.6 -8 µA VDD = 1.8 V VIN=(VDD-0.4) V Source current for push - pull mode and high level -7.7 -8 -8.3 mA VDD = 4.5 V VIN=(VDD-0.4) V -4.9 -5.2 -5.5 mA VDD = 2.7 V VIN=(VDD-0.4) V -2.9 -3.2 -3.5 mA VDD = 1.8 V VIN=(VDD-0.4) V ISK [*1] [*2] Sinkcurrent for push-pull mode and low level 19 20 21 mA VDD = 4.5 V VIN= 0.4 V 12 13 14 mA VDD = 2.7 V VIN= 0.4 V 7 8 9 mA VDD = 1.8 V VIN= 0.4 V VOH [*1] Output high level voltage for quasi -bidirectional mode VDD – 0.4 - VDD V ISR = -7.2 µA Output high level voltage for push-pull mode VDD – 0.4 - VDD V VDD ≥ 2.7 V ISR = -4.9 mA V VDD ≥ 1.8 V ISR = -2.9 mA VOL [*1] Output low level voltage for push-pull mode VSS - 0.4 V VDD ≥ 2.7 V ISR = 12 mA V VDD ≥ 1.8 V ISR = 7 mA CIO [*1] I/O pin capacitance - 5 - pF Note: 1. Guaranteed by characterization result, not tested in production. 2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not exceed ΣIDD and ΣISS. Table 8.3-11 I/O Output Characteristics
July 2, 2020 Page 219 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.3.6.3 nRESET Input Characteristics Symbol Parameter Min Typ Max Unit Test Conditions VILR Negative going threshold, nRESET - - 0.3*VDD V VIHR Positive going threshold, nRESET 0.7*VDD - - V RRST [*1] Internal nRESET pull up resistor 45 53 47 kΩ tFR [*1] nRESET input filtered pulse time - 24 - µS Normal run and Idle mode - 24 - Fast wake up Power-down mode - TBD - Power-down mode - 0.1 - Deep Power-down mode Note: 1. Guaranteed by characterization result, not tested in production. 2. It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin Table 8.3-12 nRESET Input Characteristics
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8.4 AC Electrical Characteristics
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) The 48 MHz RC oscillator is calibrated in production. Symbol. Parameter Min Typ Max Unit Test Conditions VDD Operating voltage 1.75 - 5.5 V fHRC Oscillator frequnecy 47.52 48 48.48 MHz TA = 25 °C, VDD = 3.3V Frequency drift over temperarure and volatge -1 - 1 % TA = 25 °C, VDD = 3.3V VDD = 1.75 ~ 5.5V VDD = 1.75 ~ 5.5V VDD = 1.75 ~ 5.5V IHRC [*1] Operating current - 500 800 µA TS [*2] Stable time - 14 16 µS TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V Note: 1. Guaranteed by characterization result, not tested in production. 2. Guaranteed by design. Table 8.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
July 2, 2020 Page 221 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.4.2 4 MHz Internal Median Speed RC Oscillator (MIRC) The 4 MHz RC oscillator is calibrated in production. Symbol. Parameter Min Typ Max Unit Test Conditions VDD Operating voltage 1.75 - 5.5 V FMRC Oscillator frequnecy 3.951 4.032 4.112 MHz TA = 25 °C, VDD = 3.3V Frequency drift over temperarure and volatge -2 - 2 % TA = 25 °C, VDD = 3.3V VDD = 1.75 ~ 5.5V IMRC [*1] Operating current - - 30 µA TS [*2] Stable time - - 24 µS TA = -40C ~ +105 °C, VDD = 1.75 ~ 5.5V Note: 1. Guaranteed by characterization result, not tested in production. 2. Guaranteed by design. Table 8.4-2 4 MHz Internal Median Speed RC Oscillator (MIRC) Characteristics
July 2, 2020 Page 222 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.4.3 38.4 kHz Internal Low Speed RC Oscillator (LIRC) Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions VDD Operating voltage 1.75 - 5.5 V FLRC [*2] Oscillator frequnecy - 38.4 - kHz TA = 25 °C, VDD = 3.3V Frequency drift over temperarure and volatge -2 - 2 % TA = 25 °C, VDD = 3.3V -15 - 15 % TA=-40~105°C VDD=1.75V~5.5V Without software calibration ILRC Operating current - 0.85 1 µA VDD = 3.3V TS Stable time - - 70 μS TA=-40~105°C VDD=1.75V~5.5V Note: 1. Guaranteed by characterization, not tested in production. 2. The 38.4 kHz low speed RC oscillator can be calibrated by user. 3. Guaranteed by design. Table 8.4-338.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics
July 2, 2020 Page 223 of 266 Rev 1.01 M251/M252 SERIES DATASHEET The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the XT1_IN and XT1_Out pins and must not be connec ted to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min[*1] Typ Max[*1] Unit Test Conditions VDD Operating voltage 1.75 - 5.5 V Rf Internal feedback resister - 1000 - kΩ fHXT Oscillator frequency 4 - 32 MHz IHXT Current consumption - 45 150 µA 4 MHz, Gain = L0, CL = 12.5 pF, ESR = 120Ω - 80 250 8 MHz, Gain = L1, CL = 12.5 pF, ESR = 60Ω - 150 430 12 MHz, Gain = L2, CL = 12.5 pF, ESR = 25Ω - 230 600 16 Mhz, Gain = L3, CL = 12.5 pF, ESR = 25Ω - 280 760 24 MHz, Gain = L4, CL = 12.5 pF, ESR = 25Ω - 630 1550 32 MHz, Gain = L7, CL = 12.5 pF, ESR = 25Ω TS Stable time - 2550 2950 µs 4 MHz, Gain = L0, CL = 12.5 pF, ESR = 120Ω - 900 1250 8 MHz, Gain = L1, CL = 12.5 pF, ESR = 60Ω - 550 850 12 MHz, Gain = L2, CL = 12.5 pF, ESR = 25Ω - 400 700 16 Mhz, Gain = L3, CL = 12.5 pF, ESR = 25Ω - 300 650 24 MHz, Gain = L4, CL = 12.5 pF, ESR = 25Ω - 250 610 32 MHz, Gain = L7, CL = 12.5 pF, ESR = 25Ω DuHXT Duty cycle 40 - 60 % Vpp Peak-to-peak amplitude - 1.6 - V Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-4 External 4~32 MHz High Speed Crystal (HXT) Oscillator
July 2, 2020 Page 224 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Parameter Min Typ Max [*1] Unit Test Conditions Rs Equivalent series resisotr(ESR) - - 120 Ω Crystal @4 MHz, CL = 12.5 pF, Gain = L0 - - 60 Crystal @8 MHz, CL = 12.5 pF, Gain = L1 - - 25 Crystal @12 MHz , C L = 12.5 pF, Gain = L2 - - 25 Crystal @16 MHz , C L = 12.5 pF, Gain = L3 - - 25 Crystal @24 MHz , C L = 12.5 pF, Gain = L4 - - 25 Crystal @32 MHz , C L = 12.5 pF, Gain = L7 Note: 1. Guaranteed by characterization, not tested in production. 2. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life. If Safety factor isn’t enough, the HXT gain need be changed to higher driving level. RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is only used to measure Safety factor (Sf) of crystal in engineer stage, not for mass produciton. XT1_INXT1_OUT RADD Table 8.4-5 External 4~32 MHz High Speed Crystal Characteristics
8.4.4.1 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 20 pF range, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. The crystal manufacturer typically specifies a load capacitance which is the seri es combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C1 and C2. CRYSTAL C1 C2 R1
4 MHz ~ 32 MHz 10 ~ 20 pF 10 ~ 20 pF without
July 2, 2020 Page 225 of 266 Rev 1.01 M251/M252 SERIES DATASHEET XT1_INXT1_OUT C1R1C2 Figure 8.4-1 Typical Crystal Application Circuit
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8.4.5 External 4~32 MHz High Speed Clock Input Signal Characteristics
For clock input mode , the HXT oscillator is switched off and XT1_IN is a standard input pin to receive external clock. The external clock signal has to respect the table below. The characteristics result from tests performed uses a wavefrom generator. Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions fHXT_ext External user clock source frequency 1 - 32 MHz tCHCX Clock high time 8 - - nS tCLCX Clock low time 8 - - nS tCLCH Clock rise time - - 10 nS Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 10 nS High (90%) to low level (10%) fall time DuE_HXT Duty cycle 40 - 60 % VIH Input high voltage 0.7*VDD - VDD V VIL Input low voltage VSS - 0.3*VDD V XT1_IN External clock source tCHCX 90% 10% tCLCH tCHCL tCLCX tCLCL VIL VIH Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-6 External 4~32 MHz High Speed Clock Input Signal 8.4.6 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics for M251xC/M251xD/M252xC/M252xD The low -speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external compon ents. In the application, the external components have to be placed as close as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crys tal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions
July 2, 2020 Page 227 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions VDD Operation voltage 1.75 - 5.5 V TLXT Temperature range -40 - 105 C Rf Internal feedback resistor - 15 - MΩ FLXT Oscillator frequency 32.768 kHz ILXT Current consumption from VDD - 0.6 2.0 ESR=35 kΩ, CL = 12.5 pF, Gain = - 0.74 2.5 ESR=70 kΩ, CL = 12.5 pF, Gain = - 1 3.0 ESR=70 kΩ, CL = 12.5 pF, Gain = TsLXT Stable time - 2 - S DuLXT Duty cycle 30 - 70 % Vpp [*1] Peak-to-peak amplitude - 0.4 - V Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-7 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Symbol Parameter Min Typ Max Unit Test Conditions Rs Equivalnet Series Resisotr(ESR) - 35 70 kΩ Crystal @32.768 kHz Table 8.4-8 External 32.768 kHz Low Speed Crystal Characteristics
8.4.6.1 Typical Crystal Application Circuits
32.768 kHz, ESR < 70 KΩ 5 ~ 20 pF 5 ~ 20 pF without X32_INX32_OUT C1R1C2 Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit
July 2, 2020 Page 228 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.4.7 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics for M251xE/M251xG/M252xE/M252xG The low -speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the X32_OUT and X32_IN pins and mus t not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions VBAT Operation voltage 1.75 - 5.5 V TLXT Temperature range -40 - 105 C Rf Internal feedback resistor - 15 - MΩ FLXT Oscillator frequency 32.768 kHz ILXT Current consumption from VBAT - 0.49 4.6 ESR=35 kΩ, CL = 6 pF, Gain = L1 - 0.55 4.75 ESR=35 kΩ, CL = 6 pF, Gain = L2 - 0.76 5 ESR=35 kΩ, CL = 12.5 pF, Gain = - 0.87 5.3 ESR=35 kΩ, CL = 12.5 pF, Gain = - 0.97 5.55 ESR=35 kΩ, CL = 12.5 pF, Gain = - 1.4 6.4 ESR=70 kΩ, CL = 12.5 pF, Gain = - 1.ƒ 7.5 ESR=70 kΩ, CL = 12.5 pF, Gain = TsLXT Stable time - 2 - S DuLXT Duty cycle 30 - 70 % Vpp Peak-to-peak amplitude - 0.3 - V Note: 1. Guaranteed by characterization, not tested in production. Table 8.4-9 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Symbol Parameter Min Typ Max Unit Test Conditions Rs Equivalnet Series Resisotr(ESR) - 35 70 kΩ Crystal @32.768 kHz Table 8.4-10 External 32.768 kHz Low Speed Crystal Characteristics
8.4.7.1 Typical Crystal Application Circuits
32.768 kHz, ESR < 70 KΩ 5 ~ 20 pF 5 ~ 20 pF without
July 2, 2020 Page 229 of 266 Rev 1.01 M251/M252 SERIES DATASHEET X32_INX32_OUT C1R1C2 Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit 8.4.8 External 32.768 kHz Low Speed Clock Input Signal Characteristics For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive external clock. The external clock signal has to respect the table below. The characteristics result from tests performed uses a wavefrom generator. Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions fLXT_ext External clock source frequency - 32.768 - kHz tCHCX Clock high time 450 - - nS tCLCX Clock low time 450 - - nS tCLCH Clock rise time - - 50 nS Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 50 nS High (90%) to low level (10%) fall time DuE_LXT Duty cycle 30 - 70 % Xin_VIH LXT input pin input high voltage 0.7*VDD - VDD V VBAT = VDD Xin_VIL LXT input pin input low voltage VSS - 0.3*VDD V VBAT = VDD X32_IN External clock source tCHCX 90% 10% tCLCH tCHCL tCLCX tCLCL VIL VIH Note: 1. Guaranteed by design, not tested in production. Table 8.4-11 External 32.768 kHz Low Speed Clock Input Signal
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8.4.9 PLL Characteristics
Symbol Parameter Min[*1] Typ Max[*1] Unit Test Conditions fPLL_in PLL input clock 4 - 24 MHz fPLL_OUT PLL multiplier output clock 16 - 100 MHz fPLL_REF PLL reference clock 4 - 8 MHz fPLL_VCO PLL voltage controlled oscillator 64 - 100 MHz TL PLL locking time - - 100 µS Jitter[*2] Cycle-to-cycle Jitter - - 500 pS IDD Power consumption - 1 2 mA VDD=5.5V @ fPLL_VCO = 100 MHz Note: 1. Guaranteed by characterization, not tested in production 2. Guaranteed by design, not tested in production Table 8.4-12 PLL Characteristics
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8.4.10 I/O AC Characteristics
Symbol Parameter Typ. Max[*1]. Unit Test Conditions[*2] tf(IO)out Output high (90%) to low level (10%) fall time (Normal Slew Rate) - 6.5 nS CL = 30 pF, VDD >= 4.5 V - 4.5 CL = 10 pF, VDD >= 4.5 V - 10 CL = 30 pF, VDD >= 2.7 V - 7 CL = 10 pF, VDD >= 2.7 V - 16.5 CL = 30 pF, VDD >= 1.8 V - 11.5 CL = 10 pF, VDD >= 1.8 V Output high (90%) to low level (10%) fall time (High Slew Rate) - 5 CL = 30 pF, VDD >= 4.5 V - 3.5 CL = 10 pF, VDD >= 4.5 V - 8 CL = 30 pF, VDD >= 2.7 V - 5 CL = 10 pF, VDD >= 2.7 V - 12.5 CL = 30 pF, VDD >= 1.8 V - 8 CL = 10 pF, VDD >= 1.8 V tr(IO)out Output low (10%) to high level (90%) rise time (Normal Slew Rate) - 7.5 nS CL = 30 pF, VDD >= 4.5 V - 5 CL = 10 pF, VDD >= 4.5 V - 12 CL = 30 pF, VDD >= 2.7 V - 8 CL = 10 pF, VDD >= 2.7 V - 20.5 CL = 30 pF, VDD >= 1.8 V - 13.5 CL = 10 pF, VDD >= 1.8 V Output low (10%) to high level (90%) rise time (High Slew Rate) - 6.5 nS CL = 30 pF, VDD >= 4.5 V - 4.5 CL = 10 pF, VDD >= 4.5 V - 10 CL = 30 pF, VDD >= 2.7 V - 6.5 CL = 10 pF, VDD >= 2.7 V - 18 CL = 30 pF, VDD >= 1.8 V - 10.5 CL = 10 pF, VDD >= 1.8 V fmax(IO)out [*3] I/O maximum frequency (Normal Slew Rate) - 47 MHz CL = 30 pF, VDD >= 4.5 V - 70 CL = 10 pF, VDD >= 4.5 V - 30 CL = 30 pF, VDD >= 2.7 V - 44 CL = 10 pF, VDD >= 2.7 V - 18 CL = 30 pF, VDD >= 1.8 V
July 2, 2020 Page 232 of 266 Rev 1.01 M251/M252 SERIES DATASHEET - 26 CL = 10 pF, VDD >= 1.8 V I/O maximum frequency (High Slew Rate) - 55 MHz CL = 30 pF, VDD >= 4.5 V - 80 CL = 10 pF, VDD >= 4.5 V - 36 CL = 30 pF, VDD >= 2.7 V - 56 CL = 10 pF, VDD >= 2.7 V - 21 CL = 30 pF, VDD >= 1.8 V - 35 CL = 10 pF, VDD >= 1.8 V IDIO [*4] I/O dynamic current consumption 2.77 - mA CL = 30 pF, VDD = 3.3 V, f(IO)out = 24 MHz 1.19 - CL = 10 pF, VDD = 3.3 V, f(IO)out = 24 MHz 0.69 - CL = 30 pF, VDD = 3.3 V, f(IO)out = 6 MHz 0.3 - CL = 10 pF, VDD = 3.3 V, f(IO)out = 6 MHz Note: 1. Guaranteed by characterization result, not tested in production. 2. CL is a external capacitive load to simulate PCB and device loading. 3. The maximum frequency is defined by 4. The I/O dynamic current consumption is defined by Table 8.4-13 I/O AC Characteristics
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8.5 Analog Characteristics
8.5.1 LDO
Symbol Parameter Min Typ Max Unit Test Condition VDD Power supply 1.75 - 5.5 V VLDO Output voltage - 1.5 - V TA Temperature -40 - 105 ℃ Note: 1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device. 2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of the device. 3. VLDO is only used to supply internal power.
8.5.2 Reset and Power Control Block Characteristics
The parameters in the table below are derived from tests performed under ambient temperature. Symbol Parameter Min Typ Max Unit Test Conditions IPOR [*1] POR operating current - 70 100 µA AVDD = 5.5V ILVR [*1] LVR operating current - 0.3 3 AVDD = 5.5V IBOD [*1] BOD operating current - 40 60 AVDD = 5.5V, Normal mode - 3 6 AVDD = 5.5V, Low Power mode VPOR POR reset voltage 1.40 1.5 1.65 V - VLVR LVR reset voltage 1.55 1.6 1.7 VBOD BOD brown-out detect voltage (Falling edge) 1.70 1.80 1.90 BODVL = 1 1.90 2.00 2.10 BODVL = 2 2.30 2.40 2.50 BODVL = 3 2.60 2.70 2.80 BODVL = 4 2.90 3.00 3.10 BODVL = 5 3.60 3.70 3.80 BODVL = 6 4.25 4.40 4.50 BODVL = 7 BOD brown-out detect voltage (Rising edge) 1.76 1.88 2.00 BODVL = 1 1.96 2.08 2.20 BODVL = 2 2.36 2.48 2.60 BODVL = 3 2.66 2.78 2.90 BODVL = 4 2.96 3.08 3.20 BODVL = 5 3.66 3.78 3.90 BODVL = 6 4.31 4.48 4.60 BODVL = 7 TLVR_SU [*1] LVR startup time - 200 2000 µS -
July 2, 2020 Page 234 of 266 Rev 1.01 M251/M252 SERIES DATASHEET TLVR_RE [*1] LVR respond time - 20 50 - TBOD_SU [*1] BOD startup time - 1000 2000 - TBOD_RE [*1] BOD respond time - 1 2 Normal mode - - 30000 Low Power mode RVDDR [*1] VDD rise time rate 10 - 20000 µS/V POR Enabled RVDDF [*1] VDD fall time rate 10 - - POR Enabled 250 - - LVR Enabled 10 - - BOD Enabled for Normal mode Note: 1. Guaranteed by characterization, not tested in production. 2. Design for specified applcaiton. Table 8.5-1 Reset and power control unit RVDDR VPOR VDD Time RVDDF VLVR VBOD Figure 8.5-1 Power Ramp Up/Down Condition
July 2, 2020 Page 235 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 8.5.3 12-bit SAR Analog to Digital Converter (ADC) Symbol Parameter Min Typ Max Unit Test Conditions TA Temperature -40 - 105 ℃ AVDD Analog operating voltage 1.75 - 5.5 V VDD = AVDD VREF Reference voltage 1.75 - AVDD V VIN ADC channel input voltage 0 - VREF V IADC [*1] ADC Operating current (AVDD + VREF current) - - 355 µA AVDD = VDD = VREF = 3.3 V FADC = 16 MHz TCONV = 18 * TADC NR Resolution 12 Bit FADC [*1] 1/TADC ADC Clock frequency 4 - 16 MHz TSMP Sampling Time 1 - 256 1/FADC TSMP = ( EXTSMPT(EADC_SCTL TCONV Conversion time 18 - 273 1/FADC TCONV = TSMP + 17 * TADC FSPS [*1] Sampling Rate 250 - 888.8 kSPS FSPS = FADC / TCONV EXTSMPT(ADC_ESMPCTL[7:0]) = 0 TEN Enable to ready time TBD - - μS INL[*1] Integral Non-Linearity Error -3 - +3 LSB VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 -TBD +TBD LSB VREF = AVDD, REX = 50Ω TSSOP20 and TSSOP28 DNL[*1] Differential Non-Linearity Error -1 - +3 LSB VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 -TBD - +TBD LSB VREF = AVDD, REX = 50Ω TSSOP20 and TSSOP28 EG [*1] Gain error -6 - +6 LSB VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 -TBD - +TBD LSB VREF = AVDD, REX = 50Ω TSSOP20 and TSSOP28 EO [*1] T Offset error -3 - +3 LSB VREF = AVDD, REX = 50Ω except TSSOP20 and TSSOP28 -TBD - +TBD LSB VREF = AVDD, REX = 50Ω TSSOP20 and TSSOP28 EA [*1] Absolute Error -1.5 - +6.5 LSB VREF = AVDD, , REX = 50Ω except TSSOP20 and TSSOP28 -TBD - +TBD LSB VREF = AVDD, REX = 50Ω TSSOP20 and TSSOP28 ENOB[*1] Effective number of bits TBD TBD - bits FADC = 16 MHz
July 2, 2020 Page 236 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Parameter Min Typ Max Unit Test Conditions SINAD[*1] Signal-to-noise and distortion ratio TBD TBD - dB AVDD = VDD = VREF = 1.8 V ~ 5.5 V REX = 50Ω Input Frequency = 1 kHz ~ 20 kHz TA = 25 °C SNR[*1] Signal-to-noise ratio TBD TBD - THD[*1] Total harmonic distortion TBD TBD - CIN [*1] Internal Capacitance - 26 30 pF RIN [*1] Internal Switch Resistance - 0.5 - kΩ REX [*1] External input impedance - - 33 kΩ Note: 1. Guaranteed by characterization result, not tested in production. 2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on 12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real signal and reduce the ADC accuracy. VDD 12-bit Converter EADC_CHx RIN CIN REX CEXVEX Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins should be avoided to protect the conversion being performed on another analog input. It is recommended to add Schottky diodes (pin to ground and pin to powe r) to analog pins which may potentially inject currents.
July 2, 2020 Page 237 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 4095 4094 4093 4092 Ideal transfer curve Actual transfer curve Offset Error EO Analog input voltage (LSB) 4095 ADC output code Offset Error EO Gain Error EG EF (Full scale error) = EO + EG DNL
1 LSB
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.
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8.5.4 Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Conditions AVDD Analog supply voltage 1.75 - 5.5 V VDD = AVDD TA Temperature -40 - 105 ℃ IACMP [*2] ACMP operating current - 38 90 MODESEL = 11 - 10 30 MODESEL = 10 - 3 10 MODESEL = 01 - 1.2 6 MODESEL = 00 VCM [*2] Input common mode voltage range 0.1 1/2 AVDD AVDD -0.1 VDI [*2] Differential input voltage sensitivity - 10 - mV Hysteresis disable (HYSSEL = 00) Voffset [*2] Input offset voltage - ±10 ±20 mV Hysteresis disable (HYSSEL = 00) Vhys [*2] Hysteresis window - 10 20 mV HYSSEL = 01 - 20 40 HYSSEL = 10 - 30 60 HYSSEL = 11 Av [*1] DC voltage Gain 43 70 - dB Td [*2] Propagation delay - 175 250 nS MODESEL = 11 - 350 600 MODESEL = 10 - 700 2000 MODESEL = 01 - 1400 4500 MODESEL = 00 TSetup [*2] Setup time - 250 + Td 450 + Td µS ACRV [*2] CRV output voltage -5 - 5 % AVDD x (1/6+CRVCTL/24) RCRV [*2] Unit resistor value - 4.7 - kΩ IDD_CRV [*2] Operating current - 30 120 A Note: 1. Guaranteed by design, not tested in production. 2. Guaranteed by characteristic, not tested in production. Table 8.5-2 ACMP Characteristics
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8.5.5 Digital to Analog Converter (DAC)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Condition AVDD Analog supply voltage 2.5 - 5.5 V - NR Resolution 12 bit - VREF Reference supply voltage 1.65 - AVDD V VREF ≤ AVDD DNL[*2] Differential non-linearity error - - ±1 LSB 12-bit mode - - ±0.5 LSB 8-bit mode INL[*2] Integral non-linearity error - - ±2 LSB 12-bit mode - - ±0.5 LSB 8-bit mode OE[*2] Offset Error - - ±25 LSB 12-bit mode DACOUT buffer ON - - ±5 LSB 12-bit mode DACOUT buffer OFF - - ±2 LSB 8-bit mode GE[*2] Gain Error - - ±20 LSB 12-bit mode DACOUT buffer ON - - ±4 LSB 12-bit mode DACOUT buffer OFF - - ±2 LSB 8-bit mode AE[*2] Absolute Error - - ±8 LSB 12-bit mode DACOUT buffer ON - - ±4 LSB 12-bit mode DACOUT buffer OFF - - ±2 LSB 8-bit mode - Monotonic 10-bit guaranteed - - VO [*1] Output Voltage 0.2 - AVDD -
0.2 V DACOUT buffer ON
1*LSB - VREF - 1*LSB V DACOUT buffer OFF RLOAD [*2] [*3] Resistive load 5 - - kΩ DACOUT buffer ON RO [*2] Output impedance - 8 20 kΩ DACOUT buffer OFF CLOAD [*2] [*4] Capacitive load - - 50 pF -
July 2, 2020 Page 240 of 266 Rev 1.01 M251/M252 SERIES DATASHEET IDAC_AVDD [*2] DAC operating current on AVDD supply - 340 550 A AVDD = 5.5V, no load , lowest code (0x000) AVDD = 5.5V, no load , middle code (0x800) IDAC_VREF[*2] DAC operating current on VREF supply - - 280 A VREF =5.5V, no load , middle code (0x800) TB [*2] Settling Time - 3 4 μS Full scale: for a 12 -bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value +/-1 LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ FS Update Rate - - 1 MSPS Max. frequency for a correct DAC_OUT change from core i to i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ TWAKEUP Wake-up Time - 9 15 μS Wakeup time from OFF state. Input code between lowest and highest possible codes. DAC clock source = 1MHz PSRR[*1] Power Supply Rejection Ratio - -60 -40 dB No RLOAD, CLOAD = 50pF Note: 1. Guaranteed by design, not tested in production 2. Guaranteed by characteristic, not tested in production. 3. Resistive load between DACOUT and AVSS. 4. Capacitive load at DACOUT pin.
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8.5.6 OP Amplifier (OPA)
The maximum values are obtained for V DD = 5.5 V and maximum ambient temperature (T A), and the typical values for TA = 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Condition AVDD Analog supply voltage 2.5 - 5.5 V TA Temperature -40 - 105 ℃ IOPA OPA operating current - 500 1400 A VCM [*2] Common mode input range 0.1 - AVDD-0.1 V VOS [*2] Output Saturation Voltage 0.1 - AVDD-0.1 V RLOAD = 4 KΩ VOFFSET0 [*2] Input offset voltage - ±1 ±3 mV After Offset voltage calibration VCM=AVDD/2 - ±1 ±5 mV After Offset voltage calibration VCM=0.1 ~ AVDD – 0.1 CMRR[*1] Common Mode Rejection Ratio - 89 - dB AVDD=3.3V, VCM=AVDD/2 PSRR[*1] Power Supply Rejection Ratio - 120 - dB AVDD=3.3V, VCM=AVDD/2 GBW[*2] Bandwidth - 5 - MHz AVDD=3.3V, VCM=AVDD/2 SR[*2] Slew rate - 7.5 - V/S RLOAD = 4 KΩ, CLOAD = 50pF AO[*1] Open loop gain - 91 - dB PM[*1] Phase Margin - 63 - degree AVDD=3.3V, VCM=AVDD/2 GM[*1] Gain Margin - TBD - dB TWAKEUP [*2] Wake up time from disable state - 2 20 S RLOAD [*2] Resistive load 4 - - kΩ CLOAD [*2] Capacitive load - - 50 pF Note: 1. Guaranteed by design, not tested in production 2. Guaranteed by characteristic, not tested in production.
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8.5.7 Internal Voltage Reference
The maximum values are obtained for V DD = 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Condition VREF_INT Internal reference voltage 1.49 1.536 1.59 V AVDD >= 2.0 V 1.98 2.048 2.11 AVDD >= 2.4 V 2.48 2.560 2.64 AVDD >= 2.9 V 2.97 3.072 3.17 AVDD >= 3.4 V 3.97 4.096 4.22 AVDD >= 4.5 V Ts [*1] Stable time - 0.5 0.8 mS CL =4.7 uF, VREF initial=0V, Pr eload is enabled. - 9.3 13 mS CL =4.7 uF, VREF initial=5.5V, Preload is enabled. - 24 180 S CL =1 u F, VREF initial=0V, Preload is enabled. - 2 2.6 mS CL =1 uF, VREF initial=5.5V, Preload is enabled. IVREF_INT [*1] Internal VREF Operating current - - 1 mA Note: 1. Guaranteed by characterization, not tested in production. VREF 1uF Note: VREF_INT is only supported while package includes VREF pin with external capacitor. Figure 8.5-2 Typical Connection with Internal Voltage Reference
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8.5.8 Temperature Sensor
The maximum values are obtained for V DD = 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Condition VTEMP_OS [*1] Temperature sensor offset voltage 690 720 750 mV TA = 0°C TC [*1] Temperature Coefficient -1.74 -1.83 -1.9 mV/°C ITEMP [*1] Operating current - 16 30 A Note: 1. Guaranteed by characterization, not tested in production 2. Guaranteed by design, not tested in production 3. VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV)
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8.6 Communications Characteristics
8.6.1 SPI Dynamic Characteristics
Specificaitons[*1] Test Conditions Min Typ Max Unit FSPICLK 1/ TSPICLK SPI clock frequency - - 24 MHz 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 24 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 16 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tCLKH Clock output High time TSPICLK / 2 nS tCLKL Clock output Low time TSPICLK / 2 nS tDS Data input setup time 2 - - nS tDH Data input hold time 4 - - nS tV Data output valid time - - 4.5 nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 4.5 nS 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 4.5 nS 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-1 SPI Master Mode Characteristics CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 MISO MOSI Data Valid Data ValidData Valid Data Valid SPICLK MISO MOSI Data Valid Data ValidData Valid Data Valid CLKP=0 CLKP=1 tV tDS tDH tV tDS tDH tCLKH tCLKL Figure 8.6-1 SPI Master Mode Timing Diagram
July 2, 2020 Page 245 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Parameter Specificaitons[*1] Test Conditions Min Typ Max Unit FSPICLK 1/ TSPICLK SPI clock frequency - - 11.2 MHz 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 8.8 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 4.6 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tCLKH Clock output High time TSPICLK / 2 nS tCLKL Clock output Low time TSPICLK / 2 nS tSS Slave select setup time TSPICLK + 2ns - - nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF TSPICLK + 2ns - - 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF TSPICLK + 3ns - - 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tSH Slave select hold time 1 TSPICLK - - nS tDS Data input setup time 1.5 - - nS tDH Data input hold time 3.5 - - nS tV Data output valid time - - 35 nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 42 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 74 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-2 SPI Slave Mode Characteristics
July 2, 2020 Page 246 of 266 Rev 1.01 M251/M252 SERIES DATASHEET SPI Clock SPI data input (SPI_MOSI) SPI data output (SPI_MISO) Data Valid CLKPOL=0 TXNEG=1 RXNEG=0 CLKPOL=1 TXNEG=0 RXNEG=1 tV Data Valid Data Valid Data Valid tDS tDH tSH tSS SPI SS SPI Clock SPI data input (SPI_MOSI) SPI data output (SPI_MISO) Data Valid CLKPOL=0 TXNEG=0 RXNEG=1 CLKPOL=1 TXNEG=1 RXNEG=0 tV Data Valid Data Valid Data Valid tDS tDH tSHtSS SPI SS SSACTPOL=1 SSACTPOL=0 SSACTPOL=1 SSACTPOL=0 tCLKH tCLKL tCLKH tCLKL Figure 8.6-2 SPI Slave Mode Timing Diagram
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8.6.2 SPI - I2S Dynamic Characteristics
Symbol Parameter Min [*1] Max [*1] Unit Test Conditions tw(CKH) I2S clock high time 80 - nS Master fPCLK = 48 MHz, data: 24 bits, audio frequency = 128 kHz tw(CKL) I2S clock low time 80 - tv(WS) WS valid time 2 6 Master mode th(WS) WS hold time 2 - Master mode tsu(WS) WS setup time 24 - Slave mode th(WS) WS hold time 0 - Slave mode DuCy(SCK) I2S slave input clock duty cycle 30 70 % Slave mode tsu(SD_MR) Data input setup time 10 - nS Master receiver tsu(SD_SR) 7 - Slave receiver th(SD_MR) Data input hold time 7 - Master receiver th(SD_SR) 4 - Slave receiver tv(SD_ST) Data output valid time - 25 Slave transmitter (after enable edge) th(SD_ST) Data output hold time 4 - Slave transmitter (after enable edge) tv(SD_MT) Data output valid time - 4 Master transmitter (after enable edge) th(SD_MT) Data output hold time 0 - Master transmitter (after enable edge) Note: 1. Guaranteed by design. Table 8.6-3 I2S Characteristics tw(CKH) tw(CKL) th(WS)tv(WS) th(SD_ST) LSB transmit(2) MSB transmit Bitn transmit LSB transmit LSB receive(2) MSB receive Bitn receive LSB receive tsu(SD_MR) th(SD_MR) SDtransmit SDreceive WS output CPOL = 1 CPOL = 0 tv(SD_ST) CK output Figure 8.6-3 I2S Master Mode Timing Diagram
July 2, 2020 Page 248 of 266 Rev 1.01 M251/M252 SERIES DATASHEET tw(CKH) tw(CKL) th(WS) tsu(WS) th(SD_ST) LSB transmit(2) MSB transmit Bitn transmit LSB transmit LSB receive(2) MSB receive Bitn receive LSB receive tsu(SD_SR) th(SD_SR) SDtransmit SDreceive WS input CPOL = 1 CPOL = 0 tv(SD_ST) CK Input Figure 8.6-4 I2S Slave Mode Timing Diagram
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8.6.3 I2C Dynamic Characteristics
Symbol Parameter Standard Mode[1][2] Fast Mode[1][2] Unit Min Max Min Max tLOW SCL low period 4.7 - 1.3 - µS tHIGH SCL high period 4 - 0.6 - µS tSU; STA Repeated START condition setup time 4.7 - 0.6 - µS tHD; STA START condition hold time 4 - 0.6 - µS tSU; STO STOP condition setup time 4 - 0.6 - µS tBUF Bus free time 4.7[3] - 1.2[3] - µS tSU;DAT Data setup time 250 - 100 - nS tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] µS tr SCL/SDA rise time - 1000 20+0.1Cb 300 nS tf SCL/SDA fall time - 300 - 300 nS Cb Capacitive load for each bus line - 400 - 400 pF Note: 1. Guaranteed by characteristic, not tested in production 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. Table 8.6-4 I2C Characteristics tBUF STOP SDA SCL START tHD;STA tLOW tHD;DAT tHIGH tf tSU;DAT Repeated START tSU;STA tSU;STO STOP tr Figure 8.6-5 I2C Timing Diagram
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8.6.4 USCI - SPI Dynamic Characteristics
Symbol Parameter Min [*1] Typ Max[*1] Unit Test Conditions FSPICLK 1/ TSPICLK SPI clock frequency - - 24 MHz 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 24 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 16 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tCLKH Clock output High time TSPICLK / 2 nS tCLKL Clock output Low time TSPICLK / 2 nS tDS Data input setup time 2 - - nS tDH Data input hold time 4 - - nS tV Data output valid time - - 9 nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 9 nS 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 8.5 nS 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-5 USCI-SPI Master Mode Characteristics CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 MISO MOSI Data Valid Data ValidData Valid Data Valid SPICLK MISO MOSI Data Valid Data ValidData Valid Data Valid CLKP=0 CLKP=1 tV tDS tDH tV tDS tDH tCLKH tCLKL Figure 8.6-6 USCI-SPI Master Mode Timing Diagram
July 2, 2020 Page 251 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions FSPICLK 1/ TSPICLK SPI clock frequency - - 6.3 MHz 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 5.6 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 4.2 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tCLKH Clock output High time TSPICLK / 2 nS tCLKL Clock output Low time TSPICLK / 2 nS tSS Slave select setup time TSPICLK + 2ns - - nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF TSPICLK + 2ns - - 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF TSPICLK + 3ns - - 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF tSH Slave select hold time 1 TSPICLK - - nS tDS Data input setup time 2 - - nS tDH Data input hold time 4 - - nS tV Data output valid time - - 79 nS 4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 88 2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF - - 117 1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF Note: 1. Guaranteed by design. Table 8.6-6 USCI-SPI Slave Mode Characteristics
July 2, 2020 Page 252 of 266 Rev 1.01 M251/M252 SERIES DATASHEET SPI Clock SPI data input (SPI_MOSI) SPI data output (SPI_MISO) Data Valid CLKPOL=0 TXNEG=1 RXNEG=0 CLKPOL=1 TXNEG=0 RXNEG=1 tV Data Valid Data Valid Data Valid tDS tDH tSH tSS SPI SS SPI Clock SPI data input (SPI_MOSI) SPI data output (SPI_MISO) Data Valid CLKPOL=0 TXNEG=0 RXNEG=1 CLKPOL=1 TXNEG=1 RXNEG=0 tV Data Valid Data Valid Data Valid tDS tDH tSHtSS SPI SS SSACTPOL=1 SSACTPOL=0 SSACTPOL=1 SSACTPOL=0 tCLKH tCLKL tCLKH tCLKL Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram
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8.6.5 USCI-I2C Dynamic Characteristics
Symbol Parameter Standard Mode[1][2] Fast Mode[1][2] Unit Min Max Min Max tLOW SCL low period 4.7 - 1.3 - µS tHIGH SCL high period 4 - 0.6 - µS tSU; STA Repeated START condition setup time 4.7 - 0.6 - µS tHD; STA START condition hold time 4 - 0.6 - µS tSU; STO STOP condition setup time 4 - 0.6 - µS tBUF Bus free time 4.7[3] - 1.2[3] - µS tSU;DAT Data setup time 250 - 100 - nS tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] µS tr SCL/SDA rise time - 1000 20+0.1Cb 300 nS tf SCL/SDA fall time - 300 - 300 nS Cb Capacitive load for each bus line - 400 - 400 pF Note: 1. Guaranteed by characteristic, not tested in production 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. Table 8.6-7 USCI-I2C Characteristics tBUF STOP SDA SCL START tHD;STA tLOW tHD;DAT tHIGH tf tSU;DAT Repeated START tSU;STA tSU;STO STOP tr Figure 8.6-8 USCI-I2C Timing Diagram
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8.6.6 USB Characteristics
8.6.6.1 USB Full-Speed Characteristics
Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions VBUS USB full speed transceiver operating voltage 4.4 - 5.25 V - VDD33 [*2] USB Internal power regulator output 3.0 3.3 3.6 V - VIH Input high (driven) 2.0 - - V - VIL Input low - - 0.8 V - VDI Differential input sensitivity 0.2 - - V |(USB_D+) - (USB_D-)| VCM Differential common-mode range 0.8 - 2.5 V Includes VDI range VSE Single-ended receiver threshold 0.8 - 2.0 V - Receiver hysteresis - 200 - mV - VOL Output low (driven) 0 - 0.3 V - VOH Output high (driven) 2.8 - 3.6 V - VCRS Output signal cross voltage 1.3 - 2.0 V - RPU Pull-up resistor 1.19 - 1.9 kΩ - VTRM Termination voltage for upstream port pull-up (RPU) 3.0 - 3.6 V - ZDRV [*3] Driver output resistance - 10 - Ω Steady state drive CIN Transceiver capacitance - - 26 pF Pin to GND Note: 1. Guaranteed by characterization result, not tested in production. 2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the USB_VDD33_CAP pin and the closest GND pin of the device. 3. USB_D+ and USB_D- must be connected with external series resistors to fit USB Full-speed spec request (28 ~ 44Ω). Table 8.6-8 USB Full-Speed Characteristics
8.6.6.2 USB Full-Speed PHY Characteristics
Symbol Parameter Min [*1] Typ Max [*1] Unit Test Conditions TFR rise time 4 - 20 nS CL=50 pF TFF fall time 4 - 20 nS CL=50 pF TFRFF rise and fall time matching 90 - 111.11 % TFRFF = TFR/TFF Note: 1. Guaranteed by characterization result, not tested in production. Table 8.6-9 USB Full-Speed PHY Characteristics
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8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased. Symbol Parameter Min Typ Max Unit Test Condition VFLA [1] Supply voltage - 1.5 - V TA = 25℃ TERASE Page erase time - 20 - mS TPROG Program time - 60 - µS IDD1 Read current - 7 - mA IDD2 Program current - 8 - mA IDD3 Erase current - 12 - mA NENDUR Endurance 100,000 - - cycles[2] TJ = -40℃~125℃ TRET Data retention 10 - - year 100 kcycle[3] TJ = 85℃ Note: 1. VFLA is source from chip internal LDO output voltage. 2. Number of program/erase cycles. 3. Guaranteed by design.
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9 PACKAGE DIMENSIONS
9.1 TSSOP20 (4.4x6.5x0.9 mm3)
July 2, 2020 Page 257 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 9.2 TSSOP28 (4.4x9.7x1.0 mm3)
July 2, 2020 Page 258 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 9.3 QFN 33L (5x5x0.8 mm3)
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July 2, 2020 Page 260 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 9.4 LQFP 48L (7x7x1.4 mm3 Footprint 2.0 mm) 1 12 H H Controlling dimension : Millimeters 0.10 070 0.004 1.00 0.750.600.45 0.039 0.0300.0240.018 0.50 0.20 0.25 1.451.40 0.10 0.15 1.35 0.008 0.010 0.0570.055 0.026 0.004 0.006 0.053 Symbol Min Nom Max MaxNomMin Dimension in inch Dimension in mm A b c D e HD HE L Y A A E 0.008 0.006 0.15 0.20 0.020 0.35 0.65 0.014 36 25
July 2, 2020 Page 261 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 9.5 LQFP 64L (7x7x1.4 mm3 Footprint 2.0 mm)
July 2, 2020 Page 262 of 266 Rev 1.01 M251/M252 SERIES DATASHEET 9.6 LQFP 128L (14x14x1.4 mm3 Footprint 2.0 mm)
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10 ABBREVIATIONS
10.1 Abbreviations
ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EADC Enhanced Analog-to-Digital Converter EBI External Bus Interface EMAC Ethernet MAC Controller EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 12 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation
July 2, 2020 Page 264 of 266 Rev 1.01 M251/M252 SERIES DATASHEET QEI Quadrature Encoder Interface SD Secure Digital SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 10.1-1 List of Abbreviations
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11 REVISION HISTORY
2020.04.10 1.00 Initial version. 2020.07.02 1.01 1. Revised stable time test condition of internal reference voltage in section 8.5.7. 2. Revised RADD connection that is closed to XT1_OUT pin in Table 8.4-5. 3. Revised tWU_DPD value in Table 8.3-8 4. Revised application circuit in Chapter 7. 5. Revised IDD_FWPD value in Table 8.3-3. 6. Added a 10Ω series resistor on USB_Vbus in section 7.2 7. Updated OPA characteristics in section 8.5.6. 8. Updated supply current characteristics for M251x E/M251xG/M252xE/M252xG in section 8.3.2.
July 2, 2020 Page 266 of 266 Rev 1.01 M251/M252 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damages and liabilities thus incurred by Nuvoton.