M1010-01

M1010-01 ICST | Alldatasheet

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M1010-01 Datasheet Rev 0.4 2 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information DETAILED BLOCK DIAGRAM Figure 3: Detailed Block Diagram PIN DESCRIPTIONS Number Name I/O Configuration Description 1, 2, 3, 10, 14, 26 GND Ground Power supply ground connections. OP_IN nOP_IN Input External loop filter connections. See Figure 4, External Loop Filter, on pg. 4. nOP_OUT OP_OUT Output nVC VC Input 11, 18, 19, 33 VCC Power Power supply connection, connect to + 3.3V. 12, 13, 17, 25, 32 NC No internal connection. FOUT nFOUT Output No internal terminator Clock output pairs. Differential LVPECL. 20 nDIF_REF1 Input Internal pull-UP resistor1 Note 1: For typical values of internal pull-down and pull-up resistors, see “Inputs with Pull-down” and “Inputs with Pull-up” in Table 8, DC Characteristics, on pg. 6. Reference clock input pair. Differential LVPECL or LVDS.21 DIF_REF1 Internal pull-down resistor1 22 REF_SEL Input Internal pull-down resistor 1 Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. 23 nDIF_REF0 Input Internal pull-UP resistor1 Reference clock input pair. Differential LVPECL or LVDS.24 DIF_REF0 Internal pull-down resistor1 FIN_SEL1 FIN_SEL0 Input Internal pull-down resistor 1 Input clock frequency selection. LVCMOS/LVTTL. See Table 3, Mfin (Frequency Input) Divider Look-Up Table (LUT) on pg. 3. SEL0 SEL1 SEL2 Input Internal pull-UP resistor 1 M and R divider value selection. LVCMOS/ LVTTL. See Table 4, SEL2:0 Look-up Table (LUT) on pg. 3. 34, 35, 36 DNC Do Not Connect. Table 2: Pin Descriptions Phase Locked Loop (PLL) M1010 SAW Delay Line Phase Shifter VCSO CPOST CPOST VCnVC RPOST nOP_OUTOP_OUT RPOST RLOOP RLOOP CLOOP CLOOP RIN RIN OP_IN nOP_IN Phase Detector Loop Filter Amplifier External Loop Filter Components FOUT nFOUT SEL2:0 FIN_SEL1:0 R Div MUX REF_SEL DIF_REF1 nDIF_REF1 DIF_REF0 nDIF_REF0 Divider LUT3 Mfin Divider LUT Mfin DividerM Div

M1010-01 Datasheet Rev 0.4 3 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information Integrated Circuit Systems, Inc. PLL DIVIDER LOOK-UP TABLES Mfin (Frequency Input) Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value (“Mfin”). SEL2:0 Look-up Table (LUT) The SEL2:0 pins select the feedback and reference divider values M and R to enable adjustment of loop bandwidth and jitter tolerance. FUNCTIONAL DESCRIPTION The M1010-01 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchro- nized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). A configurable frequency divider (labeled “Mfin Divider”) provides the division options to accomodate various reference clock frequencies. In addition, configurable feedback and reference dividers (the “M Divider” and “R Divider”) provide divider value options to enable adjustment of loop bandwidth and jitter tolerance. For example, the M1010-01-155.5200 (see “Ordering Information” on pg. 8) has a 155.52MHz VCSO frequency: The Mfin feedback divider allows an input frequency to be the VCSO output frequency divided by 1, 2, or 8. Therefore, for the base input frequency of 155.52MHz, the actual input reference clock frequencies can be: The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The “Mfin Divider” and “M Divider” divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the “R Divider”. The result is fed into the other input of the phase detector. The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output’s frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO 200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO (Fvcso) frequency, the Mfin divider, the M divider, the R divider, and the input reference frequency (Fin) is: Clock Output The M1010-01 provides one differential LVPECL output pair FOUT. PECL and LVDS product options are available; consult factory. FIN_SEL1:0 Mfin Value M1010-01-155.5200 Sample Ref. Freq. (MHz) 1 Note 1: Example with M1010-01-155.5200. 0 0 8 19.44 0 1 2 77.76 10 1 1 5 5 . 5 2 1 1 x Test mode. Do not use. Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT) SEL2:0 M R Description 0 0 0 236 236 Various divider values to adjust bandwidth and jitter tolerance 001 7 9 7 9 010 1 4 1 4 0 1 1 239 239 100 1 1 101 2 2 110 4 4 111 8 8 Table 4: SEL2:0 Look-up Table (LUT) Fvcso Fin Mfin× M R----×=

M1010-01 Datasheet Rev 0.4 4 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information External Loop Filter To provide stable PLL operation, the M1010-01 requires the use of an external loop filter. This is implemented by connecting passive external components to the device as shown in Figure 4 below. The M1010-01 utilizes a differential analog signal path to minimize noise coupling from the system. Because of this, the loop filter implementation requires two identical complementary RC filters as shown here. Figure 4: External Loop Filter PLL bandwidth is affected by the “M” value and the “Mfin” value, as well as the VCSO frequency. The various SEL1:0 settings can be used to actively change PLL loop bandwidth in a given application. See “SEL2:0 Look-up Table (LUT)” on pg. 3. See Table 5, Example Loop Filter Component Values for M1010-01-155.5200, on pg. 4. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. CPOST CPOST VCnVC RPOST nOP_OUTOP_OUT RPOST RLOOP RLOOP CLOOP CLOOP OP_IN nOP_IN 6 7549 8 Example Loop Filter Component Values for M1010-01-155.52001 VCSO Parameters: KVCO = 200kHz/V, RIN = 2050kΩ, VCSO Bandwidth = 700kHz. Device Configuration Example External Loop Filter Component Value Nominal Performance Using These Values FRef (MHz) FVCSO (MHz) Mfin M, R Value2 R loop C loop R post C post PLL Loop Bandwidth Damping Factor Passband Peak Amplitude @ Center (dB) Freq. 2 118.0kΩ 22.0µF 200kΩ 1000pF 134Hz 6.8 0.04 4Hz 77.76 155.52 2 1 59.0kΩ 1.0µF 100kΩ 1000pF 610Hz 6.5 0.05 20Hz 2 59.0kΩ 2.2µF 100kΩ 1000pF 267Hz 6.8 0.04 10Hz 8 118.0kΩ 2.2µF 200kΩ 1000pF 134Hz 6.8 0.04 10Hz 155.52 155.52 1 4 59.0kΩ 1.0µF 100kΩ 1000pF 267Hz 6.8 0.04 10Hz 8 76.8kΩ 2.0µF 200kΩ 1000pF 180Hz 6.3 0.05 8Hz Table 5: Example Loop Filter Component Values for M1010-01-155.5200 Note 1: K VCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. Note 2: For loop timing applications, the recommended value for the product of “Mfin” x “M” is 8 or higher.

M1010-01 Datasheet Rev 0.4 5 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information Integrated Circuit Systems, Inc. ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Rating Unit VI Inputs -0.5 to VCC +0.5 V VO Outputs -0.5 to VCC +0.5 V VCC Power Supply Voltage 4.6 V TS Storage Temperature -45 to +100 oC Table 6: Absolute Maximum Ratings Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. RECOMMENDED CONDITIONS OF OPERATION Symbol Parameter Min Typ Max Unit VCC Positive Supply Voltage 3.135 3.3 3.465 V TA Ambient Operating Temperature Commercial 0 +70 oC Industrial -40 +85 oC Table 7: Recommended Conditions of Operation

M1010-01 Datasheet Rev 0.4 6 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information ELECTRICAL SPECIFICATIONS DC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter Min Typ Max Unit Conditions Power Supply VCC Positive Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 162 mA Differential Inputs IIH Input High Current DIF_REF0, DIF_REF1 150 µA nDIF_REF0, nDIF_REF1 5 µA IIL Input Low Current DIF_REF0, DIF_REF1 -5 µA nDIF_REF0, nDIF_REF1 -150 µA VP-P Peak to Peak Input DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 0.15 V VCMR Common Mode Input 0.5 Vcc - V LVCMOS / LVTTL Inputs VIH Input High Voltage REF_SEL, FIN_SEL1, FIN_SEL0, SEL2, SEL1, SEL0 2 Vcc + 0.3 V VIL Input Low Voltage -0.3 0.8 V CIN Input Capacitance 4 pF Inputs with Pull-down IIH Input High Current All Inputs except nDIF_REF1:0, SEL2:0 150 µA VCC = VIN = 3.456V IIL Input Low Current -5 µA Rpulldown Internal Pull-down Resistor 51 kΩ Inputs with Pull-up IIH Input High Current nDIF_REF1, nDIF_REF0, SEL2, SEL1, SEL0 5 µA VCC = 3.456V VIN = 0 V IIL Input Low Current -150 µA Rpullup Internal Pull-up Resistor 51 kΩ All Inputs CIN Input Capacitance All Inputs 4 pF Differential Outputs VOH Output High Voltage FOUT, nFOUT Vcc - 1.4 Vcc - 1.0 V VOL Output Low Voltage Vcc - 2.0 Vcc - 1.7 V VP-P Peak to Peak Output Voltage 1 Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time on pg. 7. 0.4 0.85 V Table 8: DC Characteristics

M1010-01 Datasheet Rev 0.4 7 of 8 Revised 29Sep2003 Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400 M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information Integrated Circuit Systems, Inc. ELECTRICAL SPECIFICATIONS (CONTINUED) PARAMETER MEASUREMENT INFORMATION Output Rise and Fall Time Figure 5: Output Rise and Fall Time Output Duty Cycle Figure 6: Output Duty Cycle AC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter Min Typ Max Unit Conditions FIN Input Frequency DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 18.75 175 MHz

50 MHz

FOUT Output Frequency FOUT, nFOUT 150 175 MHz APR VCSO Pull-Range Commercial ±120 ±200 ppm Industrial ±50 ±150 ppm PLL Loop Constants 1 Note 1: Parameters needed for PLL Simulator software; see Table 5, Example Loop Filter Component Values for M1010-01-155.5200 on pg. 4. KVCO VCO Gain 200 kHz/V RIN Internal Loop Resistor 2050 kΩ BWVCSO VCSO Bandwidth 700 kHz Phase Noise and Jitter Φ n Single Side Band Phase Noise 155.52MHz 1kHz Offset -72 dBc/Hz Fin=19.44_MHz Mfin=8, M=x, R=x 10kHz Offset -94 dBc/Hz 100kHz Offset -123 dBc/Hz J(t) Jitter (rms) @155.52MHz 12kHz to 20MHz 0.5 ps 50kHz to 80MHz 0.5 ps odc Output Duty Cycle 2 Note 2: See Parameter Measurement Information on pg. 7. 45 50 55 % tR Output Rise Time 2 for FOUT, nFOUT 325 450 500 ps 20% to 80% tF Output Fall Time 2 for FOUT, nFOUT 325 450 500 ps 20% to 80% Table 9: AC Characteristics 20% 80% tR 20% tF 80% Clock Output VP-P nFOUT FOUT tPW tPERIOD (Output Pulse Width) tPERIOD tPWodc =