LTM4619EV

LTM4619 LINER | Alldatasheet

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Technical content

DESCRIPTION

Dual, 26VIN, 4A DC/DC µModule Regulator The L TM®4619 is a complete dual 4A step-down switch- ing mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductor , and all support components. Operating over input voltage ranges of 4.5V to 26.5V , the L TM4619 supports two outputs with voltage ranges of 0.8V to 5V , each set by a single external resistor . Its high effi ciency design delivers 4A continuous current (5A peak) for each output. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrifi cing stability. The two outputs are interleaved with 180° phase to minimize the ripple noise and reduce the I/O capacitors. The device supports frequency synchronization and output voltage tracking for supply rail sequencing. Burst Mode operation or pulse-skipping mode can be selected for light load operations. Fault protection features include overvoltage protection, overcurrent protection and foldback current limit for short-circuit protection. The low profi le package (2.8mm) enables utilization of unused space on the bottom of PC boards for high density point of load regulation. The power module is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package. The L TM4619 is Pb-free and RoHS compliant. Dual 4A 3.3V/2.5V DC/DC μModule® Regulator

FEATURES

APPLICATIONS

n Complete Standalone Power Supply n Wide Input Voltage Range: 4.5V to 26.5V (EXTVCC Available for VIN ≤ 5.5V) n Dual 180° Out-of-Phase Outputs with 4A DC Typical, 5A Peak Output Current for Each n Dual Outputs with 0.8V to 5V V OUT Range n Output Voltage T racking n ±1.5% Total DC Output Error n Current Mode Control/Fast T ransient Response n Power Good n Phase-Lockable Fixed Frequency 250kHz to 780kHz n On Board Frequency Synchronization n Parallel Current Sharing n Selectable Burst Mode ® Operation n Output Overvoltage Protection n Small Surface Mount Footprint, Low Profi le (15mm × 15mm × 2.8mm) LGA Package n Telecom and Networking Equipment n Servers n Storage Cards n ATCA Cards n Industrial Equipment n Point of Load Regulation Effi ciency and Power Loss at 12V input

4619 TA01a

V FB2 COMP2 VOUT2 TK/SS2 RUN2 EXTVCC INTVCCMODE/PLLIN L TM4619 SGND PGND 28k 19.1k 100μF100μF VOUT2 3.3V/4A VOUT1 2.5V/4A 0.1μF 10μF 0.1μF 5.5V TO 26.5V 22pF 22pF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 2.0 1.5 1.0 0.5 321 1.5 3.5

4619 TA01b

42.50.5 2.5VOUT 3.3VOUT EFFICIENCY POWER LOSS L, L T , L TC, L TM, Linear Technology, the Linear logo, Burst Mode and μModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS MODE/PLLIN, TK/SS1, TK/SS2, CC Internal Operating Temperature Range (Note 2) (Note 1) LGA PACKAGE 144-LEAD (15mm × 15mm × 2.8mm) TOP VIEW 12345678 1 0 91 1 1 2 L K J H G F E D C B M A TJMAX = 125°C, θJA = 13°C/W , θJP = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage V IN ≤ 5.5V , Connect VIN and INTVCC Together l 4.5 26.5 V VOUT1, 2(RANGE) Output Voltage Range V IN = 5.5V to 26.5V l 0.8 5.0 V VOUT1, 2(DC) Output Voltage CIN = 10μF ×1, COUT = 100μF Ceramic, 100μF POSCAP, RSET = 28.0kΩ V IN = 12V , VOUT = 2.5V , IOUT = 0A V IN = 12V , VOUT = 2.5V , IOUT = 4A l 2.483 2.470 2.52 2.52 2.557 2.570 V V Input Specifi cations V IN(UVLO) Undervoltage Lockout Thresholds V INTVCC Rising VINTVCC Falling 2.00 1.85 2.2 2.0 2.35 2.15 V V ORDER INFORMATION ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V . Per typical application in Figure 18. Specifi ed as each channel. (Note 3) LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4619EV#PBF L TM4619EV#PBF L TM4619V 144-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4619IV#PBF L TM4619IV#PBF L TM4619V 144-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V . Per typical application in Figure 18. Specifi ed as each channel (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 10μF , COUT = 100μF , VOUT = 2.5V VIN = 12V 0.25 A IQ(VIN) Input Supply Bias Current V IN = 12V , VOUT1 = 2.5V , Switching Continuous VIN = 12V , VOUT2 = 2.5V , Switching Continuous VIN = 26.5V , VOUT1 = 2.5V , Switching Continuous VIN = 26.5V , VOUT2 = 2.5V , Switching Continuous Shutdown, RUN = 0, VIN = 20V mA mA mA mA μA I S(VIN) Input Supply Current V IN = 12V , VOUT = 2.5V , IOUT = 4A VIN = 26.5V , VOUT = 2.5V , IOUT = 4A 0.97 0.480 A A INTVCC Internal VCC Voltage V IN = 12V , VRUN > 2V, No Load 4.8 5 5.2 V EXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive l 4.5 4.7 V Output Specifi cations I OUT1, 2(DC) Output Continuous Current Range V IN = 12V , VOUT = 2.5V (Note 5) 0 4 A ΔVOUT1(LINE) VOUT(NOM) Line Regulation Accuracy V OUT = 2.5V , VIN from 6V to 26.5V IOUT = 0A For Each Output l 0.15 0.25 0.3 0.5 ΔV OUT2(LINE) VOUT(NOM) Line Regulation Accuracy V OUT = 2.5V , VIN from 6V to 26.5V IOUT = 0A For Each Output l 0.15 0.25 0.3 0.5 ΔV OUT1(LOAD) VOUT1(NOM) Load Regulation Accuracy For Each Output, V OUT = 2.5V , 0A to 4A (Note 5) VIN = 12V l 0.6 0.8 ±% ΔVOUT2(LOAD) VOUT2(NOM) Load Regulation Accuracy For Each Output, V OUT = 2.5V , 0A to 4A (Note 5) VIN = 12V l 0.6 0.8 ±% VOUT1, 2(AC) Output Ripple Voltage I OUT = 0A, COUT = 100μF X5R Ceramic V IN = 12V , VOUT = 2.5V V IN = 26.5V , VOUT = 2.5V mV mV fS Output Ripple Voltage Frequency I OUT = 2A, VIN = 12V , VOUT = 2.5V FREQ/PLLFL TR = INTVCC 780 kHz ΔVOUTSTART Turn-On Overshoot C OUT = 100μF X5R Ceramic, VOUT = 2.5V , IOUT = 0A V IN = 12V V IN = 26.5V mV mV tSTART Turn-On Time C OUT = 100μF X5R Ceramic, VOUT = 2.5V , IOUT = 0A Resistive Load, V IN = 12V V IN = 26.5V 0.250 0.130 ms ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 100μF X5R Ceramic,VOUT = 2.5V , VIN = 12V 15 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load COUT = 100μF X5R Ceramic,VOUT = 2.5V , VIN = 12V 10 μs IOUTPK Output Current Limit C OUT = 100μF X5R Ceramic, V IN = 6V , VOUT = 2.5V V IN = 26.5V , VOUT = 2.5V A A Control Section VFB1, VFB2 Voltage at VFB Pin I OUT = 0A, VOUT = 2.5V l 0.792 0.788 0.8 0.8 0.808 0.810 V ITK/SS1, 2 Soft-Start Charge Current V TK/SS = 0V , VOUT = 2.5V 0.9 1.3 1.7 μA DFMAX Maximum Duty Factor In Dropout (Note 4) 97 % tON(MIN) Minimum On-Time (Note 4) 90 ns

ELECTRICAL CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V . Per typical application in Figure 18. Specifi ed as each channel. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fNOM Nominal Frequency V FREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency V FREQ = 0V 210 250 290 kHz fHIGH Highest Frequency V FREQ ≥ 2.4V 700 780 860 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ IFREQ Frequency Setting Sinking Current Sourcing Current f MODE > fOSC fMODE < fOSC –13 μA μA VRUN1, 2 RUN Pin ON/OFF Threshold RUN Rising RUN Falling 1.1 1.02 1.22 1.14 1.35 1.27 V V RFB1, RFB2 Resistor Between VOUT and VFB Pins for Each Channel 60.1 60.4 60.7 kΩ VPGL PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current V PGOOD = 5V ±2 μA ΔVPGOOD PGOOD Range V FB Ramping Negative VFB Ramping Positive –7.5 7.5 –10 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4619E is guaranteed to meet performance specifi cations over the 0°C to 125°C internal operating temperature range. Specifi cations over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4619I is guaranteed to meet specifi cations over the full internal operating temperature range. Note that the maximum ambient temperature is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The two outputs are tested separately and the same testing condition is applied to each output. Note 4: 100% tested at wafer level only. Note 5: See Output Current Derating curves for different V IN, VOUT and TA. Effi ciency vs Load Current with 5VIN (f = 500kHz for 0.8VOUT, 1.2VOUT and 1.5VOUT) Effi ciency vs Load Current with 12VIN (f = 500kHz for 1.2VOUT and 1.5VOUT) Effi ciency vs Load Current with 24VIN (f = 500kHz for 1.5VOUT) (Refer to Figures 18 and 19) LOAD CURRENT (A) EFFICIENCY (%) 2.51.5 3.5

4619 G01

420.5 1 3 0.8VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 2.51.5 3.5

4619 G02

420.5 1 3 5VOUT 1.2VOUT1.5VOUT 2.5VOUT 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 2.51.5 3.5

4619 G03

420.5 1 3 5VOUT 1.5VOUT 2.5VOUT 3.3VOUT

TYPICAL PERFORMANCE CHARACTERISTICS 3.3V Output T ransient Response Start-Up, I OUT = 0A Start-Up, I OUT = 4A Short Circuit, IOUT = 0A Short Circuit, I OUT = 4A 1.2V Output T ransient Response 1.5V Output T ransient Response 2.5V Output T ransient Response (Refer to Figures 18 and 19) IOUT 1A/DIV VOUT 50mV/DIV 100μs/DIV 4619 G04 6VIN 1.2VOUT AT 2A/μs LOAD STEP f = 780kHz C OUT 2s 22μF, 6.3V X5R CERAMIC COUT 1s 330μF, 6.3V SANYO POSCAP IOUT 1A/DIV VOUT 50mV/DIV 100μs/DIV 4619 G05 6VIN 1.5VOUT AT 2A/μs LOAD STEP f = 780kHz C OUT 2s 22μF, 6.3V X5R CERAMIC COUT 1s 330μF, 6.3V SANYO POSCAP IOUT 1A/DIV VOUT 50mV/DIV 100μs/DIV 4619 G06 6VIN 2.5VOUT AT 2A/μs LOAD STEP f = 780kHz C OUT 2s 22μF, 6.3V X5R CERAMIC COUT 1s 330μF, 6.3V SANYO POSCAP IOUT 1A/DIV VOUT 50mV/DIV 100μs/DIV 4619 G07 6VIN 3.3VOUT AT 2A/μs LOAD STEP f = 780kHz C OUT 2s 22μF, 6.3V X5R CERAMIC COUT 1s 330μF, 6.3V SANYO POSCAP IIN 0.5A/DIV VIN 1V/DIV 20ms/DIV 4619 G08 VIN = 12V, VOUT = 2.5V, IOUT = 0A COUT = 2s 22μF 10V AND 1s 100μF 6.3V CERAMIC CAPs CSOFTSTART = 0.1μF USE RUN PIN TO CONTROL START-UP IIN 0.5A/DIV VIN 1V/DIV 20ms/DIV 4619 G09 VIN = 12V, VOUT = 2.5V, IOUT = 4A RESISTIVE LOAD COUT = 2s 22μF 10V, AND 1s 100μF 6.3V CERAMIC CAPs CSOFTSTART = 0.1μF USE RUN PIN TO CONTROL START-UP IIN 0.5A/DIV VOUT 1V/DIV 50μs/DIV 4619 G10 VIN = 12V, VOUT = 2.5V, IOUT = 0A COUT = 2s 22μF 10V, AND 1s 100μF 6.3V CERAMIC CAPs IIN 0.5A/DIV VOUT 1V/DIV 50μs/DIV 4619 G11 VIN = 12V, VOUT = 2.5V, IOUT = 4A COUT = 2s 22μF 10V, AND 1s 100μF 6.3V CERAMIC CAPs

VIN (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5, L8 to L12, M1 to M12): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. For V IN < 5.5, tie V IN and INTV CC together . VOUT1, VOUT2 (A10 to D10, A11 to D11, A12 to D12, A1 to D1, A2 to D2, A3 to D3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to F5, F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9, A4 to A9): Power ground pins for both input and output returns. INTV CC (F6): Internal 5V Regulator Output. This pin is for additional decoupling of the 5V internal regulator . EXTVCC (J4): External Power Input to Controller . When EXTVCC is higher than 4.7V , the internal 5V regulator is disabled and external power supplies current to reduce the power dissipation in the module. This will improve the effi ciency more at high input voltages. SGND (J6, J7, H6, H7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to PGND in the application. MODE/PLLIN (H8): Mode selection or external synchroniza- tion pin. Tying this pin high enables pulse-skipping mode. Tying this pin low enables force continuous operation. Floating this pin enables Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator . The external clock input high threshold is 1.6V , while the input low threshold is 1V . FREQ/PLLFL TR (J8): Frequency Selection Pin. An internal lowpass fi lter is tied to this pin. The frequency can be se- lected from 250kHz to 780kHz by varying the DC voltage on this pin from 0V to 2.4V . Leave this pin fl oating when external synchronization is used. TK/SS1, TK/SS2 (K8, K5): Output Voltage T racking and Soft-Start Pins. Internal soft-start currents of 1.3μA charge the soft-start capacitors. See the Applications Information section to use the tracking function. V FB1, V FB2 (K7, K6): The negative input of the error amplifi er . Internally, this pin is connected to VOUT with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between V FB and SGND pins. See the Applications Information section for details. COMP1, COMP2 (L7, L6): Current Control Threshold and Error Amplifi er Compensation Point. The module has been internally compensated for most I/O ranges. PGOOD (H5): Output Voltage Power Good Indicator . Open drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. RUN1, RUN2 (J9, J5): Run Control Pins. 0.5μA pull-up currents on these pins turn on the module if these pins are fl oating. Forcing either of these pins below 1.2V will shut down the corresponding outputs. An additional 4.5μA pull-up current is added to this pin, once the RUN pin rises above 1.2V . Also, active control or pull-up resistors can be used to enable the RUN pin. The maximum voltage is 6V on these pins. SW1, SW2 (H10, H3): Switching Test Pins. These pins are provided externally to check the operation frequency.

TA = 25°C. Use Figure 1 confi guration. Figure 1. Simplifi ed L TM4619 Block Diagram

The L TM4619 is a dual-output standalone non-isolated switching mode DC/DC power supply. It can deliver up to 4A (DC current) for each output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from typical application schematic is shown in Figure 18. The L TM4619 has integrated constant frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 780kHz. To reduce switching noise, the two outputs are interleaved with 180° phase internally and it can be syn- chronized externally using the PLLIN pin. With current mode control and internal feedback loop compensation, the L TM4619 module has suffi cient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±7.5% window around the regulation point. The power good pin is disabled during start-up. Pulling the RUN pin below 1.2V forces the controller into its shutdown state, by turning off both MOSFETs. The TK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The L TM4619 is internally compensated to be stable over all operating conditions. The Linear Technology μModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. Multiphase operation can be easily employed with the synchronization. High effi ciency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping mode using the MODE pin. Effi ciency graphs are provided for light load operations in the Typical Performance Charac- teristics section.

Figure 18. External component selection is primarily The PWM controller has an internal 0.8V reference voltage. Table 1. VFB Resistor Table vs Various Output Voltages capacitor can be used for more input bulk capacitance. or not enough source capacitance. of implemented phases increased by N times.

Burst Mode operation, fl oat the MODE/PLLIN pin. out-of-phase with the external clock. respondingly larger current and voltage ripple. to choose a proper frequency. Figure 2. Switching Frequency vs FREQ/PLLFL TR Pin Voltage

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Figure 3. Example of Coincident T racking voltages with coincident tracking. values for coincident or ratio tracking. pulled to ground in this shutdown state. Figure 4. Coincident T racking

4619 F03

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Figure 5. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Phases Figure 6. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L

Multiphase operation with multiple L TM4619 devices in parallel will lower the effective input RMS ripple current as well as the output ripple current due to the interleaving operation of the regulators. Figure 5 provides a ratio of input RMS ripple current to DC load current as a function of duty cycle and the number of paralleled phases. Choose the corresponding duty factor and the number of phases to get the correct ripple current value. For example, the 2-phase parallel for one L TM4619 design provides 8A at 2.5V output from a 12V input. The duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25 ratio of RMS ripple cur- rent to a DC load current of 8A equals ~2A of input RMS ripple current for the external input capacitors. The effective output ripple current is lowered with mul- tiphase operations as well. Figure 6 provides a ratio of peak-to-peak output ripple current to the normalized output ripple current as a function of duty factor and the number of paralleled phases. Choose the corresponding duty factor and the number of phases to get the correct output ripple current ratio value. If a 2-phase operation is chosen at 12V IN to 2.5VOUT with a duty factor of 21%, then 0.6 is the ratio of the normalized output ripple current to inductor ripple DIr at the zero duty factor . This leads to ~1.3A of the effective output ripple current ΔI L if the DIr is at 2.2A. Refer to Application Note 77 for a detailed explanation of the output ripple current reduction as a function of paralleled phases. The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. Therefore, the output voltage ripple can be calculated with the known effective output ripple current. The equation: ΔV OUT(P-P) ≈ ΔIL/(8 • f • N • COUT) + ESR • ΔIL where f is frequency and N is the number of parallel phases. APPLICATIONS INFORMATION RUN Pin The RUN pins can be used to enable or sequence the particular regulator channel. The RUN pins have their own internal 0.5μA current source to pull up the pin to 1.2V , and then the current increases to 4.5μA above 1.2V . Careful consideration is needed to assure that board contamination or residue does not load down the 0.5μA pull-up current. Otherwise active control to these pins can be used to activate the regulators. A voltage divider can be used from V IN to set an enable point that can be used as a UVLO feature for the regulator . The resistor divider needs to be low enough resistance to swamp out the pull- up current sources and not enable the device when not attended. See the Simplifi ed Block Diagram. Power Good The PGOOD pin is connected to an open drain of an internal N-channel MOSFET . The MOSFET turns on and pulls the PGOOD pin low when either V FB pin voltage is not within ±7.5% of the 0.8V reference voltage. The PGOOD pin is also pulled low when either RUN pin is below 1.2V or when the L TM4619 is in the soft-start or tracking phase. When the V FB pin voltage is within the ±7.5% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V . The PGOOD pin will fl ag power good immediately when both V FB pins are within the ±7.5% window. However , there is an internal 17μs power bad mask when either V FB goes out of the ±7.5% window.

The INTVCC is the internal 5V regulator that powers the L TM4619 internal circuitry and drives the power MOSFETs. The input voltage of the L TM4619 must be 6V or above for the INTV CC to regulate to the proper 5V level due to the internal LDO dropout from the input voltage. For ap- plications that need to operate below 6V input, then the input voltage can be connected directly to the EXTV CC pin to bypass the LDO dropout concern, or an external 5V supply can be used to power the EXTV CC pin when the input voltage is at high end of the supply range to reduce power dissipation in the module. For example the dropout voltage for 24V input would be 24V – 5V = 19V . This 19V headroom then multiplied by the power MOSFET drive current of ~15mA would equal ~0.3W additional power dissipation. So utilizing an external 5V supply on the EXTV CC would improve design effi ciency and reduce device temperature rise. Slope Compensation The module has already been internally compensated for all output voltages. The Linear Technology μModule Power Design Tool will be provided for control loop op- timization. Burst Mode Operation and Pulse-Skipping Mode The L TM4619 regulator can be placed into high effi ciency power saving modes at light load condition to conserve power . The Burst Mode operation can be selected by fl oat- ing the MODE/PLLIN pin, and pulse-skipping mode can be selected by pulling the MODE/PLLIN pin to INTV CC. Burst Mode operation offers the best effi ciency at light load, but output ripple will be higher and lower frequency ranges are capable which can interfere with some systems. Pulse-skipping mode effi ciency is not as good as Burst Mode operation, but this mode only skips pulses to save effi ciency and maintains a lower output ripple and a higher switching frequency. Burst Mode operation and pulse-skip- ping mode effi ciencies can be reviewed in graph supplied in the Typical Performance Characteristics section. Fault Conditions: Current Limit and Overcurrent Foldback The L TM4619 has a current mode controller , which inher- ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. To further limit current in the event of an overload condi- tion, the L TM4619 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to one-third of its full current limit value. Foldback current limiting is disabled during the soft-start and tracking up. Thermal Considerations and Output Current Derating In different applications, the L TM4619 operates in a variety of thermal environments. The maximum output current is limited by the environmental thermal condition. Suffi cient cooling should be provided to ensure reliable operation. When the cooling is limited, proper output current derat- ing is necessary, considering the ambient temperature, airfl ow, input/output conditions, and the need for increased reliability. T wo outputs of L TM4619 are paralleled to get high output current for derating curve tests. The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate θ JA for the module with various cooling methods. Application Note 103 provides a detailed ex- planation of the analysis for the thermal models and the derating curves. Tables 2 and 3 provide a summary of the equivalent θ JA for the noted conditions. These equivalent θJA parameters are correlated to the measured values, and are improved with airfl ow. The junction temperature is maintained at 125°C or below for the derating curves. Safety Considerations The L TM4619 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.

Figure 7. Power Loss at 1.5V Output Figure 8. Power Loss at 3.3V Output

4619 F07

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Table 2. 1.5V Output Table 3. 3.3V Output

Figure 12. 12VIN to 1.5VOUT Figure 13. 12VIN to 3.3VOUT Figure 14. 12VIN to 3.3VOUT Figure 15. 24VIN to 3.3VOUT Figure 16. 24VIN to 3.3VOUT Figure 9. 6VIN to 1.5VOUT Figure 10. 6VIN to 1.5VOUT Figure 11. 12VIN to 1.5VOUT

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Figure 18. Typical 4.5V to 26.5V Input, 5V and 3.3V Outputs at 4A Design

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Figure 20. Output Paralleled L TM4619 Module for 5V Output at 8A Design

4619 F20

Figure 21. 4-Phase, Four Outputs (5V , 3.3V , 2.5V and 1.8V) with T racking

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2 PHASE OSCILLATOR

(Arranged by Pin Function) PIN NAME PIN NAME PIN NAME PIN NAME A10 A11 A12 V OUT2 VOUT2 VOUT2 GND GND GND GND GND GND V OUT1 VOUT1 VOUT1 D10 D11 D12 V OUT2 VOUT2 VOUT2 GND GND GND GND GND GND V OUT1 VOUT1 VOUT1 G10 G11 G12 GND GND GND GND GND GND GND GND GND GND GND GND K10 K11 K12 V IN VIN VIN VIN TK2 VFB2 VFB1 TK1 V IN VIN VIN VIN B10 B11 B12 V OUT2 VOUT2 VOUT2 GND GND GND GND GND GND V OUT1 VOUT1 VOUT1 E10 E11 E12 GND GND GND GND GND GND GND GND GND GND GND GND H10 H11 H12 GND GND SW2 GND PGOOD SGND SGND MODE/PLLIN GND SW1 GND GND L10 L11 L12 V IN VIN VIN VIN VIN COMP2 COMP1 V IN VIN VIN VIN VIN C10 C11 C12 V OUT2 VOUT2 VOUT2 GND GND GND GND GND GND V OUT1 VOUT1 VOUT1 F10 F11 F12 GND GND GND GND GND INTV CC GND GND GND GND GND GND J10 J11 J12 V IN VIN VIN EXTVCC RUN2 SGND SGND FREQ/PLLFL TR RUN1 V IN VIN VIN M10 M11 M12 V IN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN PACKAGE DESCRIPTION

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 144-Lead (15mm × 15mm × 2.82mm) (Reference L TC DWG # 05-08-1816) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW3 PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 144 0308 REV A L TMXXXXXX mModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DIA 0.630 PAD 1 3x, C (0.22 x45°) DETAIL A 0.630 ±0.025 SQ. 143x S YXeee L K J H G F E D C B M A 1234567810 91112

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2009 LT 0709 • PRINTED IN USA RELATED PARTS PACKAGE PHOTOGRAPH PART NUMBER DESCRIPTION COMMENTS L TM4614 Dual 4A Low V IN DC/DC μModule 2.375V ≤ VIN ≤ 5.5V; 0.8V ≤ VOUT ≤ 5V; 15mm × 15mm × 2.8mm LGA L TM4615 T riple Low V IN DC/DC μModule T wo 4A Outputs and One 1.5A; 15mm × 15mm × 2.8mm LGA L TM4616 Dual 8A Low V IN DC/DC μModule 2.7V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 15mm × 15mm × 2.8mm LGA