LTM4616

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4644feFor more information www.linear.com/LTM4644 n Quad Output Step-Down µModule® Regulator with 4A per Output n Wide Input Voltage Range: 4V to 14V n 2.375V to 14V with External Bias n 0.6V to 5.5V Output Voltage n 4A DC, 5A Peak Output Current Each Channel n Up to 5.5W Power Dissipation (TA = 60°C, 200 LFM, No Heat Sink) n ±1.5% Total Output Voltage Regulation n Current Mode Control, Fast T ransient Response n Parallelable for Higher Output Current n Output Voltage T racking n Internal Temperature Sensing Diode Output n External Frequency Synchronization n Overvoltage, Current and Temperature Protection n 9mm × 15mm × 5.01mm BGA Package TYPICAL APPLICATION FEATURES DESCRIPTION Quad DC/DC µModule Regulator with Configurable 4A Output Array The LT M®4644/LTM4644-1 is a quad DC/DC step-down µModule (micromodule) regulator with 4A per output. Outputs can be paralleled in an array for up to 16A capabil- ity. Included in the package are the switching controllers, power FETs, inductors and support components. Operating over an input voltage range of 4V to 14V or 2.375V to 14V with an external bias supply, the LTM4644/LTM4644-1 supports an output voltage range of 0.6V to 5.5V. Its high efficiency design delivers 4A continuous (5A peak) output current per channel. Only bulk input and output capacitors are needed. LTM4644 LTM4644-1 Top Feedback Resistor from VOUT-to-VFB (one resistor per channel) Integrated 60.4k 0.5% Resistor External (to be added on PCB) Application General

Applications

Configurable Output Array* 12A 16A * Note 4 Click to view associated TechClip Videos. 1.5V Output Efficiency and Power Loss (Each Channel) n Multirail Point of Load Regulation n FPGAs, DSPs and ASICs Applications 4V to 14V Input, Quad 0.9V, 1V, 1.2V and 1.5V Output DC/DC µModule Regulator* All registered trademarks and trademarks are the property of their respective owners.

4644 TA01a

22µF 16V CLKOUT TEMP GND V OUT1 FB1 PGOOD1 VOUT2 FB2 PGOOD2 VOUT3 FB3 PGOOD3 VOUT4 FB4 PGOOD4 47µF 1.5V/4A4V to 14V 40.2k 47µF 1.2V/4A 60.4k 47µF 1V/4A 90.9k 47µF 0.9V/4A 121k A = 60°C, 200LFM, NO HEAT SINK LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

4644 TA01b

0.5 1.5 42 3 VIN = 5V VIN = 12V

4644fe For more information www.linear.com/LTM4644 ABSOLUTE MAXIMUM RATINGS 0.3V to 15V PGOOD, MODE, TRACK/SS, 0.3V to INTVCC Internal Operating Temperature Range 40°C to 125°C 55°C to 125°C (Note 1) BGA PACKAGE 77-LEAD (9mm × 15mm × 5.01mm) 1 2 3 4 5 6 7 B C D E F G H J K L A TOP VIEW VOUT1 SVIN1 MODE1 RUN1 COMP1 INTVCC1 GND PGOOD2 PGOOD1 INTVCC2PGOOD3 TEMP INTVCC3 PGOOD4 CLKOUT FB1 TRACK/SS1 GND CLKIN TRACK/SS2 FB2 RUN2 SGND TRACK/SS3 FB3 TRACK/SS4 INTVCC4 RUN4 MODE2 SVIN2 COMP2 RUN3 FB4 MODE3 SV IN3 COMP3 COMP4 MODE4SVIN4VIN4 VIN1 GND GND GND VIN3 VIN2 VOUT4 VOUT3 VOUT2 TJMAX = 125°C, θJCtop = 17°C/W, θJCbottom = 2.75°C/W, θJB + θBA = 11°C/W, θJA = 10°C/W θ VALUES PER JESD 51-12 WEIGHT = 1.9g PIN CONFIGURATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RA TING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LT M4644EY#PBF SAC305 (RoHS) LT M4644Y e1 BGA 3 –40°C to 125°C LT M4644IY#PBF SAC305 (RoHS) LT M4644Y e1 BGA 3 –40°C to 125°C LT M4644MPY#PBF SAC305 (RoHS) LT M4644Y e1 BGA 3 –55°C to 125°C LT M4644IY SnPb (63/37) LT M4644Y e0 BGA 3 –40°C to 125°C LT M4644MPY SnPb (63/37) LT M4644Y e0 BGA 3 –55°C to 125°C LT M4644EY-1#PBF SAC305 (RoHS) LT M4644Y-1 e1 BGA 3 –40°C to 125°C LT M4644IY-1#PBF SAC305 (RoHS) LT M4644Y-1 e1 BGA 3 –40°C to 125°C LT M4644IY-1 SnPb (63/37) LT M4644Y-1 e0 BGA 3 –40°C to 125°C Note: The LTM4644-1 does not include the internal top feedback resistor. Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

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4644feFor more information www.linear.com/LTM4644 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Regulator Section: per Channel VIN, SVIN Input DC Voltage SVIN = VIN l 4 14 V VOUT(RANGE) Output Voltage Range l 0.6 5.5 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF, COUT = 100µF Ceramic, MODE = INTVCC,VIN = 4V to 14V, IOUT = 0A to 4A (Note 4) LTM4644: RFB(BOT) = 40.2k LTM4644-1: RFB(TOP) = 60.4k, RFB(BOT) = 40.2k l 1.477 1.50 1.523 V VRUN RUN Pin On Threshold VRUN Rising 1.1 1.2 1.3 V IQ(SVIN) Input Supply Bias Current V IN = 12V, VOUT = 1.5V, MODE = INTVCC VIN = 12V, VOUT = 1.5V, MODE = GND Shutdown, RUN = 0, VIN = 12V mA mA µA I S(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 4A 0.62 A IOUT(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Note 4) 0 4 A ΔVOUT (Line)/VOUT Line Regulation Accuracy V OUT = 1.5V, VIN = 4V to 14V, IOUT = 0A l 0.04 0.15 %/V ΔVOUT (Load)/VOUT Load Regulation Accuracy V OUT = 1.5V, IOUT = 0A to 4A l 0.5 1 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V 5 mV ΔVOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V 30 mV tSTART Turn-On Time COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF, VIN = 12V, VOUT = 1.5V 2.5 ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, C OUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V 160 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, C OUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V 40 µs IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V 6 7 A VFB Voltage at FB Pin IOUT = 0A, VOUT = 1.5V, 0°C to 125°C IOUT = 0A, VOUT = 1.5V, –40°C to 125°C l 0.594 0.592 0.60 0.60 0.606 0.608 V V I FB Current at FB Pin (Note 3) ±30 nA RFBHI Resistor Between VOUT and FB Pins LTM4644 Only 60.05 60.40 60.75 kΩ ITRACK/SS T rack Pin Soft-Start Pull-Up Current TRACK/SS = 0V 2.5 4 µA V IN(UVLO) VIN Undervoltage Lockout V IN Falling VIN Hysteresis 2.4 2.6 350 2.8 V mV tON(MIN) Minimum On-Time (Note 3) 40 ns tOFF(MIN) Minimum Off-Time (Note 3) 70 ns VPGOOD PGOOD T rip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –13 –10 I PGOOD PGOOD Leakage 2 µA VPGL PGOOD Voltage Low IPGOOD = 1mA 0.02 0.1 V VINTVCC Internal VCC Voltage SVIN = 4V to 14V 3.2 3.3 3.4 V VINTVCC Load Reg INTV CC Load Regulation I CC = 0mA to 20mA 0.5 % fOSC Oscillator Frequency 1 MHz CLKIN CLKIN Threshold 0.7 V

4644fe For more information www.linear.com/LTM4644 1.0V Output T ransient Response 1.5V Output T ransient Response 2.5V Output T ransient Response Efficiency vs Load Current from 5VIN (One Channel Operating) Efficiency vs Load Current from 12V IN (One Channel Operating) DCM Mode Efficiency from 1.5V OUT

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4644E/LTM4644E-1 is tested under pulsed load conditions such that T J ≈ TA. The LTM4644E/LTM4644-1 is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4644I/LTM4644I-1 is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. The LTM4644MP/LTM4644MP-1 is tested and guaranteed over full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level. Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS LOAD CURRENT (A) EFFICIENCY (%) 100

4644 G01

3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT LOAD CURRENT (A) EFFICIENCY (%)

4644 G02

3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT LOAD CURRENT (A) 0.001 EFFICIENCY (%) 100 0.01

4644 G03

100.1 1 5VIN 12VIN 20µs/DIV LOAD STEP 1A/DIV

4644 G04

VIN = 12V, VOUT = 1V, IOUT = 3A TO 4A, 1A/µs CFF = 10pF OUTPUT CAPACITOR = 1 • 47µF CERAMIC (Per Channel) 20µs/DIV LOAD STEP 1A/DIV

4644 G05

VIN = 12V, VOUT = 1.5V, IOUT = 3A TO 4A, 1A/µs CFF = 10pF OUTPUT CAPACITOR = 1 • 47µF CERAMIC 20µs/DIV LOAD STEP 1A/DIV

4644 G06

VIN = 12V, VOUT = 2.5V, IOUT = 3A TO 4A, 1A/µs CFF = 10pF OUTPUT CAPACITOR = 1 • 47µF CERAMIC

4644feFor more information www.linear.com/LTM4644 TYPICAL PERFORMANCE CHARACTERISTICS 3.3V Output T ransient Response 5V Output T ransient Response Start-Up with No Load Start-Up with 4A Load Short-Circuit with No Load Short-Circuit with 4A Load 20µs/DIV LOAD STEP 1A/DIV

4644 G08

VIN = 12V, VOUT = 5V, IOUT = 3A TO 4A, 1A/µs OUTPUT CAPACITOR = 47µF CERAMIC 5ms/DIV

4644 G09

0.1A/DIV VOUT 0.5V/DIV VIN = 12V, VOUT = 1.5V INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR SOFT-START CAPACITOR = 0.1µF 5ms/DIV

4644 G10

0.2A/DIV VOUT 0.5V/DIV VIN = 12V, VOUT = 1.5V INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR SOFT-START CAPACITOR = 0.1µF 20µs/DIV

4644 G11

0.5A/DIV VOUT 0.5V/DIV VIN = 12V, VOUT = 1.5V INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR 20µs/DIV

4644 G12

0.5A/DIV VOUT 0.5V/DIV VIN = 12V, VOUT = 1.5V INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR 20µs/DIV LOAD STEP 1A/DIV

4644 G07

VIN = 12V, VOUT = 3.3V, IOUT = 3A TO 4A, 1A/µs OUTPUT CAPACITOR = 47µF CERAMIC Recovery to No Load from Short-Circuit Output Ripple Start Into Pre-Biased Output IOUT 20A/DIV VOUT 200mV/DIV VIN = 12V VOUT = 1V INPUT CAPACITOR = 22µF SANYO ELECTROL YTIC CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP . OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP . SOFT-START CAPACITOR = 0.1µF 5µs/DIV

4644 G13

VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 22µF SANYO ELECTROL YTIC CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP . OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP . SOFT-START CAPACITOR = 0.1µF 20MHz MEASUREMENT BANDWIDTH 500µs/DIV

4644 G14

VIN = 12V VOUT = 5V INPUT CAPACITOR = 22µF SANYO ELECTROL YTIC CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP . OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP . SOFT-START CAPACITOR = 0.1µF 1µs/DIV

4644 G15

4644fe For more information www.linear.com/LTM4644 PIN FUNCTIONS VOUT1 (A1, A2, A3), V OUT2 (C1, D1, D2), V OUT3 (F1, G1, G2), VOUT4 (J1, K1, K2): Power Output Pins of Each Switching Mode Regulator Channel. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See the Applications Information section for paralleling outputs. GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5, H1-H2, J5, K3-K4, L1-L2): Power Ground Pins for Both Input and Output Returns. Use large PCB copper areas to connect all GND together. V IN1 (B3, B4), VIN2 (E3, E4), VIN3 (H3, H4), VIN4 (L3, L4): Power input pins connect to the drain of the internal top MOSFET for each switching mode regulator channel. Apply input voltages between these pins and GND pins. Recommend placing input decoupling capacitance directly between each of VIN pins and GND pins. PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2, J2): Output Power Good with Open-Drain Logic of Each Switching Mode Regulator Channel. PGOOD is pulled to ground when the voltage on the FB pin is not within ±10% of the internal 0.6V reference. CLKOUT (J3): Output Clock Signal for PolyPhase ® Opera- tion of the Module. The phase of CLKOUT with respect to CLKIN is set to 180°. CLKOUT’s peak-to-peak amplitude is INTVCC to GND. See the Application Information section for details. Strictly output; do not drive this pin. INTV CC1, INTVCC2, INTVCC3, INTVCC4 (C4, F4, J4, K5): Internal 3.3V Regulator Output of Each Switching Mode Regulator Channel. The internal power drivers and con - trol circuits are powered from this voltage. Each pin is internally decoupled to GND with 1µF low ESR ceramic capacitor already. SVIN1, SVIN2, SVIN, SVIN4 (B5, E5, H5, L5): Signal V IN. Filtered input voltage to the internal 3.3V regulator for the control circuitry of each Switching mode Regulator Channel. Tie this pin to the V IN pin respectively in most applications. Connect SVIN to an external voltage supply of at least 4V which must also be greater than VOUT. TRACK/SS1, TRACK/SS2, TRACK/SS3, TRACK/SS4 (A6, D6, G6, K6): Output T racking and Soft-Start Pin of Each Switching Mode Regulator Channel. Allows the user to control the rise time of the output voltage. Putting a volt- age below 0.6 V on this pin bypasses the internal reference input to the error amplifier, instead it servos the FB pin to match the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. There’s an internal 2.5µA pull-up current from INTVCC on this pin, so putting a capacitor here provides soft-start function. MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6): Operation Mode Select for Each Switching Mode Regula- tor Channel. Ti e this pin to INTV CC to force continuous synchronous operation at all output loads. Tying it to SGND enables discontinuous current mode operation at light loads. Do not leave floating. RUN1, RUN2, RUN3, RUN4 (C6, F6, J6, K7): Run Control Input of Each Switching Mode Regulator Channel. Enable regulator operation by tying the specific RUN pin above 1.2V. Pulling it below 1.1V shuts down the respective regulator channel. Do not leave floating. FB1, FB2, FB3, FB4 (A7, D7, G7, J7): The Negative Input of the Error Amplifier for Each Switching Mode Regulator Channel. Internally, in LTM4644, this pin is connected to V OUT of each channel with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between the FB and GND pins for the LTM4644, and two resistors between the V OUT, FB and GND pins for the LTM4644-1. In PolyPhase operation, tying the FB pins together allows for parallel operation. See the Applications Information section for details. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

4644feFor more information www.linear.com/LTM4644 PIN FUNCTIONS COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Cur- rent Control Threshold and Error Amplifier Compensation Point of Each Switching Mode Regulator Channel. The internal current comparator threshold is proportional to this voltage. Tie the COMP pins together for parallel opera- tion. The device is internally compensated. CLKIN ( C7): External Synchronization Input to Phase Detector of the Module. This pin is internally terminated to SGND with 20kΩ. The phase-locked loop will force the channel 1 turn-on signal to be synchronized with the rising edge of the CLKIN signal. Channel 2, channel 3 and channel 4 will also be synchronized with the rising edge of the CLKIN signal with a pre-determined phase shift. See the Applications Information section for details. SGND (F7): Signal Ground Connection. SGND is connected to GND internally through single point. Use a separated SGND ground copper area for the ground of the feedback resistor and other components connected to signal pins. A second connection between the PGND plane and SGND plane is recommended on the backside of the PCB under- neath the module. TEMP ( F3): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section.

4644fe For more information www.linear.com/LTM4644 BLOCK DIAGRAM 4644 BD POWER CONTROL CLKOUT FB1 CLKIN MODE1 TRACK/SS1 RUN1 COMP1 INTV CC1 INTERNAL FIL TER INTERNAL COMP VOUT1 1µF 0.22µF 1µH 100k 100k 100k 100k 10µF 47µF FREQ1 162k 60.4k (*L TM4644 ONL Y) 60.4k (*L TM4644 ONL Y) 60.4k (*L TM4644 ONL Y) 60.4k (*L TM4644 ONL Y) 60.4k 0.1µF VIN 4V TO 14V VOUT1 1.2V INTVCC1 PGOOD1 SVIN1 VIN1 VOUT1 GND SGND GND POWER CONTROL FB2 MODE2 TRACK/SS2 RUN2 COMP2 INTV CC2 INTERNAL FIL TER INTERNAL COMP VOUT2 1µF 0.22µF 1µH 10µF 47µF FREQ2 162k 40.2k 0.1µF VIN VOUT2 1.5V INTVCC2 PGOOD2 SVIN2 VIN2 VOUT2 GND POWER CONTROL FB3 MODE3 TRACK/SS3 RUN3 COMP3 INTV CC3 INTERNAL FIL TER INTERNAL COMP VOUT3 1µF 0.22µF 1µH 10µF 47µF FREQ3 162k 30.1k 0.1µF VIN VOUT3 1.8V INTVCC3 PGOOD3 SVIN3 VIN3 VOUT3 GND POWER CONTROL FB4 MODE4 TRACK/SS4 RUN4 COMP4 INTV CC4 INTERNAL FIL TER INTERNAL COMP VOUT4 1µF 0.22µF 1µH 10µF 47µF 1µF FREQ4 162k 90.9k 0.1µF VIN VOUT4 INTVCC4 PGOOD4 SVIN4 VIN4 VOUT4 GND TEMP CLKOUT *L TM4644-1 DOES NOT INCLUDE 60.4k RESISTOR CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN 1µF 1µF 1µF

4644feFor more information www.linear.com/LTM4644 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4V to 14V, VOUT = 1.5V) IOUT = 4A 4.7 10 µF COUT External Output Capacitor Requirement IN = 4V to 14V, VOUT = 1.5V) IOUT = 4A 22 47 µF DECOUPLING REQUIREMENTS OPERATION The LTM4644 is a quad output standalone non-isolated switch mode DC/DC power supply. It has four separate regulator channels with each of them capable of delivering up to 4A continuous output current with few external input and output capacitors. Each regulator provides precisely regulated output voltage programmable from 0.6V to 5.5V via a single external resistor (two resistors for LTM4644-1) over 4V to 14V input voltage range. With an external bias voltage, this module can operate from an input voltage as low as 2.375V. The typical application schematic is shown in Figure 33. The LTM4644 integrates four separate constant frequency controlled on-time valley current mode regulators, power MOSFETs, inductors, and other supporting discrete com- ponents. The typical switching frequency is set to 1MHz. For switching noise-sensitive applications, the µModule regulator can be externally synchronized to a clock from 700kHz to 1.3MHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4644 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides the flexibility of paralleling any of the separate regulator channels with accurate cur- rent sharing. With a built-in clock interleaving between each two regulator channels, the LTM4644 could easily employ a 2+2, 3+1 or 4 channels parallel operation which is more than flexible in a multirail POL application like FPGA. Furthermore, the LTM4644 has CLKIN and CLK - OUT pins for frequency synchronization or polyphasing multiple devices which allow up to 8 phases cascaded to run simultaneously. Current mode control also provides cycle-by-cycle fast current monitoring. Foldback current limiting is provided in an overcurrent condition to reduce the inductor valley current to approximately 40% of the original value when V FB drops. An internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Continuous conduction mode (CCM) operation is forced during OV and UV conditions except during start-up when the TRACK pin is ramping up to 0.6V. Pulling the RUN pin below 1.1V forces the controller into its shutdown state, turning off both power MOSFETs and most of the internal control circuitry. At light load cur - rents, discontinuous conduction mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous conduction mode (CCM) by setting the MODE pin to SGND. The TRACK/SS pin is used for power supply tracking and soft-start programming. See the Applications Information section. A temperature diode is included inside the module to moni- tor the temperature of the module. See the Applications Information section for details. (per Channel)

4644fe For more information www.linear.com/LTM4644 APPLICATIONS INFORMATION The typical LTM4644 application circuit is shown in Figure 33. External component selection is primarily external capacitor requirements for a particular application. and Output Current Derating section in this data sheet. The PWM controller has an internal 0.6V reference voltage. Table 1. VFB Resistor Table vs Various Output Voltages The PWM controller has an internal 0.6V reference voltage. Figure 1. LTM4644-1 Feedback Resistor

4644 F01

4644feFor more information www.linear.com/LTM4644 APPLICATIONS INFORMATION Input Decoupling Capacitors The LTM4644 module should be connected to a low ac- impedance DC source. For each regulator channel, a 10µF input ceramic capacitor is recommended for RMS ripple current decoupling. A bulk input capacitor is only needed when the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. The bulk capacitor can be an electrolytic aluminum capaci- tor or polymer capacitor. Without considering the inductor ripple current, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D •(1−D) where η% is the estimated efficiency of the power module. Output Decoupling Capacitors With an optimized high frequency, high bandwidth design, only single piece of low ESR output ceramic capacitor is required for each regulator channel to achieve low output voltage ripple and very good transient response. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 7 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2A load step tran- sient. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. The L TpowerCAD™ Design Tool is available to download online for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by N times. Discontinuous Conduction Mode (DCM) In applications where low output ripple and high efficiency at intermediate current are desired, discontinuous con - duction mode (DCM) should be used by connecting the MODE pin to SGND. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. Force Continuous Conduction Mode (CCM) In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous conduction mode operation should be used. Forced continuous opera- tion can be enabled by tying the MODE pin to INTV CC. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4644’s output voltage is in regulation. Operating Frequency The operating frequency of the LTM4644 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. The default operating frequency is internally set to 1MHz. In most ap- plications, no additional frequency adjusting is required. If any operating frequency other than 1MHz is required by application, the µModule regulator can be externally synchronized to a clock from 700kHz to 1.3MHz. Frequency Synchronization and Clock In The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows all internal top MOSFET turn-on to be locked to the rising edge of the same external clock. The external clock frequency range must be within ±30% around the 1MHz set frequency. A pulse detection circuit is used to detect a clock on the CLKIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be above 2V and clock low level below 0.3V. During the start-up of the regulator, the phase-locked loop function is disabled.

difference between regulator channels. Table 2. Phase Difference Between Regulator Channels schematic for clock phasing. Figure 2. 2+2 and 4 Channels Parallel Concept Schematic

4644 F02

than the number of phases used times the output voltage). to achieve a single high output current design. reduction as a function of the number of interleaved phases. during the soft-start process.

Figure 3. Normalized RMS Ripple Current for Single Phase or Polyphase Applications

4644 F03

proportional to the master’s (VOUT1). the following equation during the start-up.

4644 F05

4644 F04TIME

Figure 4. Output Ratiometric T racking Waveform Figure 5. Output Ratiometric Tracking Schematic Figure 5. From the equation, we could solve out that offset to a negligible value. slew rate (SR), as waveform shown in Figure 6.

= 3.3V and VOUT(SL) = 1.2V application. will turn on the entire regulator channel. which would discharge the output. turned off until the temperature drops about 15°C cooler. if good PCB layout practices are followed (see Figure 32). cannot go below VOUT voltage. Figure 6. Output Coincident T racking Waveform

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download for control loop optimization. power MOSFETs and most of its internal control circuitry.

1.2V extrapolated to absolute zero or –273°C. Kelvin temp and subtracting 273 from it. temperature will provide a general temperature monitor. rent to 100µA. See Figure 35 for an example. Figure 7. Diode Voltage VD vs Temperature T(°C)

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4644feFor more information www.linear.com/LTM4644 APPLICATIONS INFORMATION Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coef- ficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the page. In the typical µModule regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned ther - mal resistances is given in Figure 8; blue resistances are contained within the μModule regulator, whereas green resistances are external to the µModule package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a μModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the µModule package—as the standard defines for θ JCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4644, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity— but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software

Figure 8. Graphical Representation of JESD 51-12 Thermal Coefficients

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multiplicative factor according to the junction temperature.

4644feFor more information www.linear.com/LTM4644 rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the ef- ficiency curves in the Typical Performance Characteristics section and adjusted with the above junction temperature multiplicative factor. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The 16A represents all four channels in parallel at 4A each. The four parallel channels have their currents reduced at the same rate to develop an equivalent θJA circuit evalu- ation with thermal couples or IR camera used to validate the thermal resistance values. Maximum Operating Ambient T emperature Figures 30 and 31 display the Maximum Power Loss Allowance Curves vs ambient temperature with various heat sinking and airflow conditions. This data was derived from the thermal impedance generated by various ther - mal derating examinations with the junction temperature measured at 120°C. This maximum power loss limitation serves as a guideline when designing multiple output rails with different voltages and currents by calculating the total power loss. For example, to determine the maximum ambient tem - perature when VOUT1 = 2.5V at 0.6A, VOUT2 = 3.3V at 3A, VOUT3 = 1.8V at 1A, VOUT4 = 1.2V at 3A, without a heat sink and 400LFM airflow, simply add up the total power loss for each channel read from Figure 9 to Figure 15 which in this example equals 2.5W, then multiply by the 1.35 coef- ficient for 120° C junction temperature and compare the total power loss number, 3.4W with Figure 30. Figure 30 indicates with a 3.4W total power loss, the maximum am- bient temperature for this particular application is around 86°C. For reference, the actual thermal derating test in the chamber resulted in a maximum ambient temperature of 86.3°C, very close to the calculated value. Also from Figure 30, it is easy to determine with a 3.4W total power loss, the maximum ambient temperature is around 77°C with no airflow and 81°C with 200LFM airflow. Safety Considerations The LTM4644 modules do not provide galvanic isolation from V IN to V OUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and overcurrent protection. APPLICATIONS INFORMATION

Figure 9. Power Loss at 1.0V Figure 10. Power Loss at 1.2V Figure 11. Power Loss at 1.5V Figure 12. Power Loss at 1.8V Figure 13. Power Loss at 2.5V

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Figure 18. 5VIN to 1.0VOUT Figure 19. 12VIN to 1.0VOUT Figure 20. 5V

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Figure 15. Power Loss at 5V Figure 16. 5VIN to 1.0VOUT Figure 17. 12V

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Figure 21. 12VIN to 1.5VOUT Figure 22. 5VIN to 1.5VOUT Figure 23. 12V Figure 24. 5V Figure 25. 12V Figure 26. 5V

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Figure 27. 12VIN to 3.3VOUT Figure 28. 12VIN to 5VOUT Figure 29. 12V Figure 30. Power Loss Allowance Figure 31. Power Loss Allowance

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Table 3. 1.0V Output Table 4. 1.5V Output Table 5. 3.3V Output Table 6. 5V Output

4644feFor more information www.linear.com/LTM4644 APPLICATIONS INFORMATION VOUT (V) CIN (CERAMIC) (µF) CIN (BULK) COUT1 (CERAMIC) (µF) COUT2 (BULK) (µF) CFF (pF) VIN (V) DROOP (mv) P-P DERIV ATION (mV) RECOVERY TIME (µs) LOAD STEP (A) LOAD STEP SLEW RA TE (A/µs) RFB (kΩ) 1 10 47 5,12 5 72 40 1 1 90.9 1 10 100µF 10 5,12 5 60 40 1 1 90.9 1 10 47 5,12 5 127 40 2 1 90.9 1 10 100µF 10 5,12 5 90 40 2 1 90.9 1.2 10 47 5,12 5 76 40 1 1 60.4 1.2 10 100µF 10 5,12 5 65 40 1 1 60.4 1.2 10 47 5,12 5 145 40 2 1 60.4 1.2 10 100µF 10 5,12 5 103 40 2 1 60.4 1.5 10 47 5,12 5 80 40 1 1 40.2 1.5 10 100µF 10 5,12 5 70 40 1 1 40.2 1.5 10 47 5,12 5 161 40 2 1 40.2 1.5 10 100µF 10 5,12 5 115 40 2 1 40.2 1.8 10 47 5,12 5 95 40 1 1 30.1 1.8 10 100µF 10 5,12 5 80 40 1 1 30.1 1.8 10 47 5,12 5 177 40 2 1 30.1 1.8 10 100µF 10 5,12 5 128 40 2 1 30.1 2.5 10 47 5,12 5 125 40 1 1 19.1 2.5 10 100µF 10 5,12 5 100 50 1 1 19.1 2.5 10 47 5,12 5 225 40 2 1 19.1 2.5 10 100µF 10 5,12 5 161 50 2 1 19.1 3.3 10 47 5,12 5 155 40 1 1 13.3 3.3 10 100µF 10 5,12 5 122 60 1 1 13.3 3.3 10 47 5,12 5 285 40 2 1 13.3 3.3 10 100µF 10 5,12 5 198 60 2 1 13.3 5 10 47 10 5,12 5 220 40 1 1 8.25 5 10 100µF 10 5,12 5 420 40 2 1 8.25 Table 7 CIN PART NUMBER VALUE C OUT1 PART NUMBER VALUE C OUT2 PART NUMBER VALUE Murata GRM21BR61C106KE15L 10µF, 16V, 0805, X5R Murata GRM21BR60J476ME15 47µF, 6.3V, 0805, X5R Sanyo 4TPE100MZB 4V 100µF Taiyo Yuden EMK212BJ106KG-T 10µF, 16V, 0805, X5R Taiyo Yuden JMK212BJ476MG-T 47µF, 6.3V, 0805, X5R Murata GRM31CR61C226ME15L 22µF, 16V, 1206, X5R Taiyo Yuden EMK316BJ226ML-T 22µF, 16V, 1206, X5R

erations are still necessary. minimize the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci- tors next to the V IN, GND and V OUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put via directly on the pad, unless they are capped or plated over.
• Use a separated SGND ground copper area for com - ponents connected to signal pins. Connect the SGND to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK/SS pin can be tied a common capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring. Figure 32 gives a good example of the recommended layout.

Figure 32. Recommended PCB Layout

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Figure 35. 4V to 14V Input, 4-Phase, 1.2V at 16A Design with Temperature Monitoring

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Figure 36. 4V to 14V Input, 4-Phase, 1.2V at 16A Design with Temperature Monitoring

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Figure 37. 12V and 5V Tw o Separate Input Rails, 1.2V at 8A and 3.3V at 8A Output

Output at 4A Each with Input and Output Voltage, Current and Temperature Telemetry.

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4644feFor more information www.linear.com/LTM4644 LTM4644/LTM4644-1 Component BGA Pinout PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y. PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 V OUT1 B1 GND C1 V OUT2 D1 V OUT2 E1 GND F1 V OUT3 A2 V OUT1 B2 GND C2 PGOOD2 D2 V OUT2 E2 GND F2 PGOOD3 A3 V OUT1 B3 V IN1 C3 PGOOD1 D3 GND E3 V IN2 F3 TEMP A4 GND B4 V IN1 C4 INTV CC1 D4 GND E4 V IN2 F4 INTV CC2 A5 GND B5 SV IN1 C5 GND D5 GND E5 SV IN2 F5 GND A6 TRACK/SS1 B6 MODE1 C6 RUN1 D6 TRACK/SS2 E6 MODE2 F6 RUN2 A7 FB1 B7 COMP1 C7 CLKIN D7 FB2 E7 COMP2 F7 SGND PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 V OUT3 H1 GND J1 V OUT4 K1 V OUT4 L1 GND G2 V OUT3 H2 GND J2 PGOOD4 K2 V OUT4 L2 GND G3 GND H3 V IN3 J3 CLKOUT K3 GND L3 V IN4 G4 GND H4 V IN3 J4 INTV CC3 K4 GND L4 V IN4 G5 GND H5 SV IN3 J5 GND K5 INTV CC4 L5 SV IN4 G6 TRACK/SS3 H6 MODE3 J6 RUN3 K6 TRACK/SS4 L6 MODE4 G7 FB3 H7 COMP3 J7 FB4 K7 RUN4 L7 COMP4

4644fe For more information www.linear.com/LTM4644 77-Lead (9mm × 15mm × 5.01mm) (Reference L TC DWG # 05-08-1900 Rev D) PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 77-Lead (15.00mm × 9.00mm × 5.01mm) (Reference LTC DWG# 05-08-1900 Rev D) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (77 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 77 D E // bbb Z Z BGA 77 0113 REV D TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PACKAGE BOTTOM VIEW SEE NOTES A B C D E F G H J K L PIN 1 e b F G 7 6 5 4 3 2 1 SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 ±0.025 Ø 77x

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4644#packaging for the most recent package drawings.

4644feFor more information www.linear.com/LTM4644 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/14 Add SnPb BGA package option 1, 2 B 06/14 Add Tech Clip video link Update Order Information Update Run Threshold Update Figure 5 Update Soft-Start and Output Voltage T racking Section C 05/16 Added MP-grade (–55°C to 125°C) 2 D 12/16 Added LTM4644-1 Added Comparison Table between LTM4644 and LTM4644-1 Added Output Voltage Programing (LTM4644-1) Added Figure 36 Added Figure 38 1 ,2, 4, 9, 10, 33 E 01/18 Changed I OUTPK (MIN) from 5A to 6A 3

4644fe For more information www.linear.com/LTM4644 SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.  ANALOG DEVICES, INC. 2013 LT 0118 REV E • PRINTED IN USA www.linear.com/LTM4644 PACKAGE PHOTO RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4624 14VIN, 4A Step-Down µModule Regulator in Tiny 6.25mm × 6.25mm × 5.01mm BGA 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, VOUT T racking, PGOOD, Light Load Mode, Complete Solution in 1cm2 (Single-Sided PCB) LTM4619 Dual 26V, 4A Step-Down µModule Regulator 4.5V ≤ V IN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, PLL Input, VOUT T racking, PGOOD, 15mm × 15mm × 2.82mm LGA LTM4618 26V, 6A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 26.5V, 0.8V ≤ VOUT ≤ 5V, PLL Input, VOUT T racking, 9mm × 15mm × 4.32mm LGA LTM4628 Dual 26V, 8A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V, Remote Sense Amplifier, Internal Temperature Sensing Output, 15mm × 15mm × 4.32mm LGA LTM4614 Dual 5V, 4A µModule Regulator 2.375V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm LGA LTM4608A 5V, 8A Step-Down µModule Regulator with T racking, Margining and Frequency Synchronization 2.7V ≤ V IN ≤ 5.5V, 0.6V ≤ VOUT ≤ 5V, PLL input, Clock Output, VOUT T racking and Margining, PGOOD, 9mm × 15mm × 2.82mm LGA LTM4616 Dual 5V, 8A Step-Down µModule Regulator with T racking, Margining and Frequency Synchronization 2.7V ≤ V IN ≤ 5.5V, 0.6V ≤ VOUT ≤ 5V, PLL input, Clock Output, VOUT T racking and Margining, PGOOD, 15mm × 15mm × 2.82mm LGA LTM8045 Inverting or SEPIC µModule DC/DC Converter with Up to 700mA Output Current 2.8V ≤ V IN ≤ 18V, ±2.5V ≤ VOUT ≤ ±15V, Synchronizable, No Derating or Logic- Level Shift for Control Inputs when Inverting, 6.25mm × 11.25mm × 4.92mm BGA LTM8001 36V, 5A Step-Down µModule Regulator with Configurable Array of Five 1A LDOs 6V ≤ V IN ≤ 36V, 0V ≤ VOUT ≤ 24V, Five Parallelable 1.1A 90µVRMS Output Noise LDOs, Synchronizable, Adjustable Switcher Output Current Limit, 15mm × 15mm × 4.92mm BGA LT C 2978 Octal Digital Power Supply Manager with EEPROM I 2C/PMBus Interface, Configuration EEPROM, Fault Logging, 16-Bit ADC with ±0.25% TUE, 3.3V to 15V Operation LTC2974 Quad Digital Power Supply Manager with EEPROM I 2C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage, Current and Temperature Measurements DESIGN RESOURCES