LTM4613

LTM4612_1 LINER | Alldatasheet

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applicaTions

DescripTion

36VIN, 15VOUT, 5A, DC/DC µModule Regulator The L TM®4612 is a EN55022 Class B certified high voltage input and output, 5A switching mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V , the L TM4612 supports an output voltage range of 3.3V to 15V , set by a single resistor . Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)—see Figures 4 and 8. Furthermore, the DC/DC µModule ® regulator can be syn- chronized with an external clock to reduce undesirable frequency harmonics and allow PolyPhase ® operation for high load currents. The L TM4612 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point-of-load regulation. The L TM4612 is Pb-free and RoHS compliant. L, L T , L TC, L TM, Linear Technology, the Linear logo, PolyPhase and µModule are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 5V/5A Ultralow Noise µModule with 7V to 36V Input n Complete Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n Wide Input Voltage Range: 5V to 36V n 3.3V to 15V Output Voltage Range n 5A DC, 7A Peak Output Current n Low Input and Output Referred Noise n Output Voltage T racking and Margining n Power Good Tracks with Margining n PLL Frequency Synchronization n ±1.5% Set Point Accuracy n Current Foldback Protection (Disabled at Start-Up) n Parallel/Current Sharing n Ultrafast T ransient Response n Current Mode Control n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range TM4612MPV) n Small Surface Mount Footprint, Low Profile (15mm × 15mm × 2.8mm) LGA Package n Telecom and Networking Equipment n Industrial and Avionic Equipment n RF Systems Radiated Emission Scan at 24VIN, 5VOUT/5A FREQUENCY (MHz) dBµV/m 128.1 226.2 324.3 –10 422.4 520.5 618.6 716.7 814.8 912.9 1010 EN55022 CLASS B LIMIT

4612 TA01b

0.01µF 10µF 100pF COUT VOUT CIN VIN TO 36V PLLIN CLOCK SYNC L TM4612 SGND VD PGND MARGIN CONTROL 100k 13.7k 392k 5% MARGIN

4612 TA01

pin conFiguraTionabsoluTe MaxiMuM raTings PLLIN, FCB, TRACK/SS, MPGM, MARG0, 0.3V to INTVCC + 0.3V 0.3V to 5V Internal Operating Temperature Range (Note 2) E and I G 40°C to 125°C MP G 55°C to 125°C 25°C 55°C to 125°C (Note 1) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW SGND 122 1 4 3 5 6 9 8 10 117 A B C D E F G H J K L M TJMAX = 125°C, θJA = 15°C/W , θJC = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4612EV#PBF L TM4612EV#PBF L TM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4612IV#PBF L TM4612IV#PBF L TM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4612MPV#PBF L TM4612MPV#PBF L TM4612MPV 133-Lead (15mm × 15mm × 2.8mm) LGA –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 5 36 V VOUT(DC) Output Voltage CIN = 10µF × 3, COUT = 300µF; FCB = 0 VIN = 24V , VOUT = 12V , IOUT = 0A VIN = 36V , VOUT=12V , IOUT = 0A l l 11.83 11.83 12.07 12.07 12.31 12.31 V V Input Specifications V IN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4.8 V IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A; CIN = 10µF × 2, COUT = 200µF; VOUT = 12V VIN = 24V VIN = 36V 0.6 0.7 A A The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V , unless otherwise noted (Note 2). Per Typical Application (front page) configuration.

elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V , unless otherwise noted (Note 2). Per Typical Application (front page) configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current VIN = 36V , VOUT = 12V , Switching Continuous VIN = 24V , VOUT = 12V , Switching Continuous Shutdown, RUN = 0, VIN = 36V mA mA µA I S(VIN) Input Supply Current VIN = 36V , VOUT = 12V , IOUT = 5A VIN = 24V , VOUT = 12V , IOUT = 5A 1.85 2.72 A A V INTVCC Internal VCC Voltage VIN = 36V , RUN > 2V , IOUT = 0A 4.7 5 5.3 V Output Specifications IOUT(DC) Output Continuous Current Range V IN = 24V , VOUT = 12V (Note 4) 0 5 A DVOUT(LINE) VOUT Line Regulation Accuracy VOUT = 12V , FCB = 0V , VIN = 22V to 36V , IOUT = 0A l 0.05 0.3 DVOUT(LOAD) VOUT Load Regulation Accuracy VOUT = 12V , FCB = 0V , IOUT = 0A to 5A (Note 4) VIN = 36V VIN = 24V l l 0.3 0.3 0.6 0.6 V IN(AC) Input Ripple Voltage IOUT = 0A, CIN = 2 × 10µF X5R Ceramic and 1 × 100µF Electrolytic, 1 × 10µF X5R Ceramic on VD Pins VIN = 24V , VOUT = 5V VIN = 24V , VOUT = 12V 7.2 3.4 mV P-P mVP-P VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2 × 22µF , 2 × 47µF X5R Ceramic VIN = 24V , VOUT = 5V VIN = 24V , VOUT = 12V 17.5 12.5 mV P-P mVP-P fS Output Ripple Voltage Frequency I OUT = 1A, VIN = 24V , VOUT = 12V 940 kHz DVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF C OUT = 200µF , VOUT = 12V , IOUT = 0A VIN = 36V VIN = 24V mV mV t START Turn-On Time, TRACK/SS = Open C OUT = 300µF , VOUT = 12V , IOUT = 1A Resistive Load VIN = 36V VIN = 24V 0.5 0.5 ms ms DV OUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 2 × 22µF Ceramic, 150µF Bulk VIN = 24V , VOUT = 12V 153 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 24V 37 µs IOUT(PK) Output Current Limit COUT = 200µF VIN = 36V , VOUT = 12V VIN = 24V , VOUT = 12V A A Control Section V FB Voltage at VFB Pin IOUT = 0A, VOUT = 12V l 0.591 0.6 0.609 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS / TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 µA VFCB Forced Continuous Threshold 0.57 0.6 0.63 V IFCB Forced Continuous Pin Current V FCB = 0V –1 –2 µA tON(MIN) Minimum On-Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 3) 250 400 ns RPLLIN PLLIN Input Resistor 50 kW

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4612E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4612I is guaranteed to meet specifications over the SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IDRVCC Current into DRVCC Pin VOUT = 12V , IOUT = 1A 22 30 mA RFBHI Resistor Between VOUT and VFB Pins 99.5 100 100.5 kW VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD DVFBH PGOOD Upper Threshold VFB Rising 7 10 13 % DVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 % DVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V , unless otherwise noted (Note 2). Per Typical Application (front page) configuration. –40°C to 125°C internal operating temperature range. The L TM4612MP is guaranteed and tested over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different V IN, VOUT and TA.

Typical perForMance characTerisTics Efficiency vs Load Current with 3.3VOUT (FCB = 0) Efficiency vs Load Current with OUT (FCB = 0) Efficiency vs Load Current with 12V OUT (FCB = 0) Efficiency vs Load Current with 15V OUT (FCB = 0, Refer to Figure 20) T ransient Response from 12VIN to 3.3VOUT T ransient Response from 12VIN to 5VOUT T ransient Response from 24VIN to 12VOUT Start-Up with 24VIN to 12VOUT at IOUT = 0A Start-Up with 24VIN to 12VOUT at IOUT = 5A (Refer to Figure 18) LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5

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5VIN 3.3VOUT 12VIN 3.3VOUT 24VIN 3.3VOUT 36VIN 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4 5

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LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5

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LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5

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50µs/DIV 2A/DIV 100mV/DIV

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LOAD STEP: 0A to 3A COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS 50µs/DIV 2A/DIV 100mV/DIV

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LOAD STEP: 0A to 3A C OUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS 50µs/DIV 2A/DIV 200mV/ DIV

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LOAD STEP: 0A to 3A C OUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS 500µs/DIV IIN 0.2A/DIV VOUT 5V/DIV

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SOFT-START CAPACITOR: 3.9nF C IN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR 500µs/DIV IIN 1A/DIV VOUT 5V/DIV

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SOFT-START CAPACITOR: 3.9nF C IN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR

Typical perForMance characTerisTics Start-Up with 24VIN to 12VOUT at IOUT = 5A, TA = –55°C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A Short-Circuit with 24VIN to 12VOUT at IOUT = 5A VIN to VOUT Step-Down Ratio Input Ripple Output Ripple 500µs/DIV IIN 1A/DIV VOUT 5V/DIV

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SOFT-START CAPACITOR: 3.9nF CIN = 3 × 10µF CERAMIC CAPACITORS AND 1 × 47µF OSCON CAPACITOR 50µs/DIV IIN 0.2A/DIV VOUT 5V/DIV

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COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS 20µs/DIV IIN 2A/DIV VOUT 5V/DIV

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COUT = 2 × 22µF CERAMIC CAPACITORS AND 2 × 47µF CERAMIC CAPACITORS 3.3 6 104 8 12 14 15

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SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION OPERATING REGION WITH DEFAUL T FREQUENCY V OUT (V) VIN (V) 1µs/DIV 50mV/DIV

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VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD CIN = 3 × 10µF 50V CERAMIC 1 × 100µF BULK 1µs/DIV 10mV/DIV

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VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD COUT = 2 × 22µF 16V CERAMIC AND 2 × 47µF 16V CERAMIC

VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing out- put decoupling capacitance directly between these pins and GND pins (see the L TM4612 Pin Configuration below). VD (Pins B7, C7): Top FET Drain Pins. Add more capa- citors between VD and ground to handle the input RMS current and reduce the input ripple further . DRV CC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at higher input voltages by reducing power dissipation in the module. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator . PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock above 2V and below INTV CC. See the Applications Information section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTV CC to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. TRACK/SS (Pin A9): Output Voltage T racking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator . Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining In- put. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. May be left open if margining is not desired. See the Applications Information section. To parallel L TM4612s, each requires an individual MPGM resistor . Do not tie MPGM pins together . f SET (Pin B12): Frequency Set Internally to ~850kHz to 900kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. L TM4612 Pin Configuration (See Package Description for Pin Assignments) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW SGND 122 1 4 3 5 6 9 8 10 117 A B C D E F G H J K L M

VFB (Pin F12): The Negative Input of the Error Ampli- fier . Internally, this pin is connected to VOUT with a 100k 0.5% precision resistor . Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margin- ing Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current com- parator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be ac- complished with a resistor from V IN to this pin that is has a 5.1V zener to ground. Maximum pin voltage is 5V . NC (Pins J12, K12, L12): No Connect Pins. Leave floating. pin FuncTions

Specifications are at TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified Block Diagram

The L TM4612 is a standalone nonisolated switching mode DC/DC power supply. It can deliver 5A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 3.3V DC to 15VDC over a 5V to 36V wide input voltage. The typical application schematic is shown in Figure 18. The L TM4612 has an integrated constant on-time current mode regulator , ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load at 12V output. With current mode control and internal feedback loop compensation, the L TM4612 module has sufficient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Moreover , foldback current limiting is provided in an overcurrent condition while V FB drops. Internal over- voltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuitry reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) meets the limits of EN55022 Class B. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At light load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to con- tinuous mode (CCM) by setting FCB pin higher than 0.6V . When the DRV CC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at higher input voltages. The MPGM, MARG0, and MARG1 pins are used to sup- port output voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply track- ing and soft-start programming. The typical L TM4612 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. applicaTions inForMaTion VIN to VOUT Stepdown Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled “V IN to V OUT Step-Down Ratio.” Note that additional thermal derating may be ap- plied. See the Thermal Considerations and Output Current Derating section in this data sheet.

The PWM controller has an internal 0.6V reference voltage. Table 1. RFB Standard 1% Resistor Values vs VOUT Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20) RPGM resistor on the MPGM pin programs the current.

VOUT Where %VOUT is the percentage of VOUT to be margined, and VOUT(MARGIN) is the margin quantity in volts: RPGM = VOUT 0.6V
1.18V VOUT(MARGIN)
10k Where RPGM is the resistor value to place on the MPGM pin to ground. The output margining will be ± margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN

output ripple voltage while still providing high efficiency. additional frequency adjusting is required. pin and SGND, as shown in Figure 19. Figure 2. Operating Frequency vs Output Voltage Figure 3. Inductor Current Ripple vs Output Voltage

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higher than 1MHz, thus reducing the efficiency significantly.

Figure 4. Radiated Emission Scan with 24VIN to noise due to the fast switching of turn-on and turn-off. is needed for capacitor C1 selection.

D • 1– D( ) In this equation, h is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor , or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In a typical 5A output application, one very low ESR, X5R or X7R, 10µF ceramic capacitor is recommended for C1. This decoupling capacitor should be placed directly adja- cent to the module V D pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. FREQUENCY (MHz) dBµV/m 128.1 226.2 324.3 –10 422.4 520.5 618.6 716.7 814.8 912.9 1010 EN55022 CLASS B LIMIT

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The L TM4612 is designed for low output voltage ripple. to maximize transient performance. series resistance (ESR) of the output bulk capacitance.

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Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI

Figure 6. Coincident T racking Figure 7. Coincident Output T racking

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state operation, but also in transient. of its full current limit value. another regulator can be easily tracked. pin. The TRACK pin has a control range from 0 to 0.6V .

100k = R2 where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R2 is equal the 100k. R1 is derived from equation: R1= 0.6V VFB 100k + VFB RFB − VTRACK PGOOD RUN COMP INTV CC DRVCC TRACK/SS fSET VOUT VFB FCB MARG0 MARG1 MPGM TRACK CONTROL PLLIN L TM4612 RFB 5.23k 100k 10µF MASTER OUTPUT R2 100k COUT SLAVE OUTPUT

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where VFB is the feedback voltage reference of the regula- tor , and VTRACK is 0.6V . Since R2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R1 is equal to RFB with VFB = VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator . R2 can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R2 = 125k. Solve for R1 to equal to 5.18k. Each of the TRACK pins will have the 1.5µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 100k is used then a 10k can be used to reduce the TRACK pin offset to a negligible value. RUN Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with 5V logic levels. The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: VUVLO = RA +RB RB

1.5V where RA is the top resistor , and RB is the bottom resistor . Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point, and tracks with margining. COMP Pin The pin is the external compensation pin. The module has already been internally compensated for most output volt- ages. L TpowerCAD™ from Linear Technology is available for more control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET re- mains on when current reverses in the inductor . Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continu- ous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. PLLIN Pin The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector . This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be greater than 1.7V and clock low level below 0.3V . During the start-up of the regulator , the phase-locked loop function is disabled. INTV CC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRV CC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the L TM4612 can be directly powered by V IN. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA • (VIN – 5V) The L TM4612 also provides the external gate driver voltage pin DRV CC. If there is a 5V rail in the system, it is recom- mended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRV CC pin. applicaTions inForMaTion

Figure 8. Radiated Emission Scan with 24VIN to

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design. Figure 21 shows a schematic of the parallel design. N is the number of paralleled modules. meet the most applications with low noise requirements. EN55022 radiated emission limit.

Figure 9. Power Loss at Figure 10. Power Loss at 5VOUT Figure 11. No Heat Sink Figure 12. BGA Heat Sink Figure 13. No Heat Sink Figure 14. BGA Heat Sink

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Figure 15. No Heat Sink Figure 16. BGA Heat Sink

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erations are still necessary.

Use large PCB copper areas for high current path, in- cluding VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capaci- tors next to the VD, PGND and VOUT pins to minimize high frequency noise.
Place a dedicated power ground layer underneath the unit.
Use round corners for the PCB copper layer to minimize the radiated noise.
T o minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. Do not put vias directly on pads. If vias are placed onto the pads, the the vias must be capped.
Interstitial via placement can also be used if necessary
Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout.

Figure 17. Recommended PCB Layout

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Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency Figure 18. Typical 22V to 36VIN, 12V at 5A Design

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Figure 21. 2-Phase, Parallel 12V at 10A Design Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency

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Figure 22. 2-Phase, 12V and 10V at 5A Design

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Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency

V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN Pin Assignment Tables (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 J11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 INTV CC PLLIN TRACK/SS RUN COMP MPGM B10 B11 B12 V D RUN MPGM f SET C10 C11 C12 V D DRV CC MARG1 MARG0 D10 D11 D12 SGND COMP MARG1 E10 E11 E12 DRV CC DRVCC F10 F11 F12 V FB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB package DescripTion

133-Lead (15mm × 15mm × 2.82mm) (Reference L TM DWG # 05-08-1766 Rev Ø) L K J H G F E D C BM A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES DETAIL A 0.630 ±0.025 SQ. 133x S Y X eee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 1107 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1”

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 03/10 Changes to Title and Description Changes to Absolute Maximum Ratings Changes to Electrical Characteristics Text Changes to Operation Section Text Changes to Applications Information Section Changes to Figures 18, 19, 20, 21, 22 Changes to Related Parts 2, 3 12, 14 19, 20, 21, 22 B 05/11 Changes to the Title, Description, Features and Typical Application sections. Changes to “The l denotes...” statement and Note 2. Changes to the Pin Functions. Changes to the Block Diagram. Text changes to the Operation section. Text changes to the Applications Information section. Changes to Figures 17, 19, 21, 22. Changes to the Related Parts. 2, 3, 4 7, 8 10–20 20, 21, 22, 23

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2008 LT 0511 REV B • PRINTED IN USA relaTeD parTs package phoTograph

4612 F24

2.8mm PART NUMBER DESCRIPTION COMMENTS L TM4606 EN55022B Compliant 6A, DC/DC µModule Regulator EN55022B Compliant with PLL, Output T racking and Margining, L TM4612 Pin Compatible L TM4613 EN55022B Compliant 36V , 8A, Step-Down µModule Regulator with PLL, Output T racking 5V ≤ V IN ≤ 36V , 3.3V ≤ VOUT ≤ 15V , 15mm × 15mm × 4.3mm LGA Package L TM4601/L TM4601A 12A DC/DC µModule Regulator with PLL, Output T racking/Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version Has No Remote Sensing, LGA Package L TM4604A Low V IN 4A DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm LGA Package L TM4608A Low V IN 8A DC/DC µModule Regulator 2.7V ≤ VIN ≤ 5.5V , 0.6V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.8mm LGA Package L TM8022/L TM8023 36V IN, 1A and 2A DC/DC µModule Regulator Pin Compatible, 4.5V ≤ V IN ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package L TM4627 20VIN, 15A DC/DC Step-Down µModule Regulator 4.5V ≤ V IN ≤ 20V , 0.6V ≤ VOUT ≤ 5V , 15mm × 15mm × 4.3mm LGA Package L TM4618 26VIN, 6A DC/DC Step-Down µModule Regulator with PLL, Output T racking 4.5V ≤ VIN ≤ 26.5V , 0.8V ≤ VOUT ≤ 5V , Synchronizable, 9mm × 15mm × 4.3mm LGA Package L TM8033 EN55022B Compliant 36VIN, 3A DC/DC Step-Down µModule Regulator 3.6V ≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 24V , Synchronizable, 11.25mm × 15mm × 4.3mm LGA Package

Summary

EN55022B Compliant 58V, 24W Inverting-Output DC/DC 關Module Regulator

Description