LTM4603_15 LINER | Alldatasheet

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Technical content

20V, 6A DC/DC µModule Regulator with PLL, Output Tracking and Margining n Telecom and Networking Equipment n Servers n Industrial Equipment n Point of Load Regulation n Complete Switch Mode Power Supply n Wide Input Voltage Range: 4.5V to 20V n 6A DC Typical, 8A Peak Output Current n 0.6V to 5V Output Voltage n Output Voltage T racking and Margining n Remote Sensing for Precision Regulation (L TM4603 Only) n Typical Operating Frequency: 1MHz n PLL Frequency Synchronization n 1.5% Regulation n Current Foldback Protection (Disabled at Start-Up) n Pin Compatible with the L TM4601 n Pb-Free (e4) RoHS Compliant Package with Gold Finish Pads n Ultrafast T ransient Response n Current Mode Control n Up to 93% Efficiency at 5VIN, 3.3VOUT n Programmable Soft-Start n Output Overvoltage Protection n Small Footprint, Low Profile (15mm × 15mm × 2.82mm) Surface Mount LGA Package 1.5V/6A Power Supply with 4.5V to 20V Input Efficiency vs Load Current with 12VIN The L TM®4603 is a complete 6A step-down switch mode DC/DC µModule® regulator with onboard switching con- troller , MOSFETs, inductor and all support components. The device is housed in a small surface mount 15mm × 15mm × 2.82mm LGA package. Operating over an input voltage range of 4.5V to 20V , the L TM4603 supports an output voltage range of 0.6V to 5V as well as output volt- age tracking and margining. The high efficiency design delivers 6A continuous current (8A peak). Only bulk input and output capacitors are needed to complete the design. The low profile (2.82mm) and light weight (1.7g) package easily mounts on the unused space on the back side of PC boards for high density point of load regulation. The µModule regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase ® operation for high load currents. A high switching frequency and adaptive on-time current mode architecture deliver a very fast transient response to line and load changes without sacrificing stability. An onboard remote sense amplifier can be used to accurately regulate an output voltage independent of load current. The onboard remote sense amplifier is not available in the L TM4603-1. The L TM4603/L TM4603-1 are pin compatible with the 12A L TM4601/L TM4601-1. L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule and PolyPhase are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD RUN COMP INTV CC DRVCC MPGM TRACK/SSPLLIN L TM4603 ON/OFF 392k 40.2k MARGIN CONTROL COUT

4603 TA01a

1.5V CLOCK SYNC TRACK/SS CONTROL 100pF CIN VIN fSETPGNDSGND 5% MARGIN VIN 4.5V TO 20V LOAD CURRENT (A) EFFICIENCY (%)60 100 2 4 5

4603 TA01b

12VIN, 1.2VOUT 12VIN, 1.5VOUT 12VIN, 1.8VOUT 12VIN, 2.5VOUT 12VIN, 3.3VOUT 12VIN, 5VOUT DescriptionFeatures

applications

INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V PLLIN, TRACK/SS, MPGM, MARG0, MARG1, 0.3V to 5V Operating Temperature Range (Note 2)....–40°C to 85°C 25°C 55°C to 125°C (Note 1) The l denotes the specifications which apply over the –40°C to 85°C operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V , per typical application (front page) configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 4.5 20 V VOUT(DC) Output Voltage CIN = 10µF ×2, COUT = 2× 100µF X5R Ceramic VIN = 5V , VOUT = 1.5V , IOUT = 0A VIN = 12V , VOUT = 1.5V , IOUT = 0A l l 1.478 1.478 1.5 1.5 1.522 1.522 V V Input Specifications V IN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4 V IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A. VOUT = 1.5V VIN = 5V VIN = 12V 0.6 0.7 A A LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE† L TM4603EV#PBF L TM4603EV#PBF L TM4603V 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C L TM4603IV#PBF L TM4603IV#PBF L TM4603V 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C L TM4603EV-1#PBF L TM4603EV-1#PBF L TM4603V-1 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C L TM4603IV-1#PBF L TM4603IV-1#PBF L TM4603V-1 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . †See Note 2. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ pin conFigurationabsolute MaxiMuM ratings MARG1 DRVCC VFB PGOOD SGND V OSNS+/NC2* DIFFVOUT/NC3* VOUT_LCL VOSNS–/NC1* VIN PGND VOUT fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 118-LEAD (15mm × 15mm × 2.82mm) TOP VIEW TJMAX = 125°C, θJA = 15°C/W , θJC = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS, WEIGHT = 1.7g *L TM4603-1 ONL Y orDer inForMation

electrical characteristics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN,NOLOAD) Input Supply Bias Current VIN = 12V , No Switching VIN = 12V , VOUT = 1.5V , Switching Continuous VIN = 5V , No Switching VIN = 5V , VOUT = 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V 3.8 2.5 mA mA mA mA µA I S(VIN) Input Supply Current VIN = 12V , VOUT = 1.5V , IOUT = 6A VIN = 12V , VOUT = 3.3V , IOUT = 6A VIN = 5V , VOUT = 1.5V , IOUT = 6A 0.92 1.83 2.12 A A A INTV CC VIN = 12V , RUN > 2V No Load 4.7 5 5.3 V Output Specifications IOUTDC Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 5) 0 6 A ∆VOUT(LINE) VOUT Line Regulation Accuracy VOUT = 1.5V , IOUT = 0A, VIN = 4.5V to 20V l 0.3 % ∆VOUT(LOAD) VOUT Load Regulation Accuracy V OUT = 1.5V , IOUT = 0A to 6A (Note 5) VIN = 12V , with Remote Sense Amp VIN = 12V , L TM4603-1 l l 0.25 0.5 VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2× 100µF X5R Ceramic VIN = 12V , VOUT = 1.5V VIN = 5V , VOUT = 1.5V mV P-P mVP-P fS Output Ripple Voltage Frequency I OUT = 3A, VIN = 12V , VOUT = 1.5V 1000 kHz ΔVOUT(START) Turn-On Overshoot COUT = 200µF , VOUT = 1.5V , IOUT = 0A, TRACK/SS = 10nF VIN = 12V VIN = 5V mV mV t START Turn-On Time COUT = 200µF , VOUT = 1.5V , TRACK/SS = Open, IOUT = 1A Resistive Load VIN = 12V VIN = 5V 0.5 0.5 ms ms ΔV OUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 2 × 22µF Ceramic, 470µF 4V Sanyo POSCAP V IN = 12V VIN = 5V mV mV t SETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 10% of Full Load VIN = 12V µs IOUTPK Output Current Limit COUT = 2× 100µF X5R Ceramic VIN = 12V , VOUT = 1.5V VIN = 5V , VOUT = 1.5V A A Remote Sense Amp (L TM4603 Only, Not Supported in the L TM4603-1) (Note 3) V OSNS+, VOSNS– CM Range Common Mode Input Voltage Range V IN = 12V , RUN > 2V 0 INTVCC – 1 V DIFFVOUT Range Output Voltage Range VIN = 12V , DIFFVOUT Load = 100k 0 INTVCC – 1 V VOS Input Offset Voltage Magnitude 1.25 mV AV Differential Gain 1 V/V GBP Gain Bandwidth Product 3 MHz SR Slew Rate 2 V/µs The l denotes the specifications which apply over the –40°C to 85°C operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V , per typical application (front page) configuration.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RIN Input Resistance VOSNS+ to GND 20 kW CMRR Common Mode Rejection Ratio 100 dB Control Stage VFB Error Amplifier Input Voltage Accuracy IOUT = 0A, VOUT = 1.5V l 0.594 0.6 0.606 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ITRACK/SS Soft-Start Charging Current V TRACK/SS = 0V –1 –1.5 –2 µA tON(MIN) Minimum On Time (Note 4) 50 100 ns tOFF(MIN) Minimum Off Time (Note 4) 250 400 ns RPLLIN PLLIN Input Resistance 50 kW IDRVCC Current into DRVCC Pin VOUT = 1.5V , IOUT = 1A, DRVCC = 5V 20 27 mA RFBHI Resistor Between VOUT_LCL and VFB 60.098 60.4 60.702 kW VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD Output ΔVFBH PGOOD Upper Threshold VFB Rising 7 10 13 % ΔVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 % ΔVFB(HYS) PGOOD Hysteresis VFB Returning (Note 4) 1.5 3 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4603/L TM4603-1 is tested under pulsed load conditions such that T J ≈ TA. The L TM4603E/L TM4603E-1 are guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4603I/L TM4603I-1 are guaranteed over the –40°C to 85°C operating temperature range. Note 3: Remote sense amplifier recommended for ≤3.3V output. Note 4: 100% tested at wafer sort only. Note 5: See output current derating curves for different V IN, VOUT and TA. The l denotes the specifications which apply over the –40°C to 85°C operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V , per typical application (front page) configuration.

typical perForMance characteristics Efficiency vs Load Current with 5VIN Efficiency vs Load Current with 12VIN Efficiency vs Load Current with 20V IN 1.2V T ransient Response 1.5V T ransient Response 2.5V T ransient Response 3.3V T ransient Response (See Figure 18 for all curves) 1.8V T ransient Response LOAD CURRENT (A) EFFICIENCY (%) 100 2 4 5

4603 G01

5VIN, 0.6VOUT 5VIN, 1.2VOUT 5VIN, 1.5VOUT 5VIN, 1.8VOUT 5VIN, 2.5VOUT 5VIN, 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%)60 100 2 4 5

4603 G02

12VIN, 1.2VOUT 12VIN, 1.5VOUT 12VIN, 1.8VOUT 12VIN, 2.5VOUT 12VIN, 3.3VOUT 12VIN, 5VOUT LOAD CURRENT (A) EFFICIENCY (%) 2 4 5

4603 G03

20VIN, 1.5VOUT 20VIN, 1.8VOUT 20VIN, 2.5VOUT 20VIN, 3.3VOUT 20VIN, 5VOUT LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G04

1.2V AT 3A/µs LOAD STEP COUT: 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G05

1.5V AT 3A/µs LOAD STEP C OUT: 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G06

1.8V AT 3A/µs LOAD STEP C OUT: 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G07

2.5V AT 3A/µs LOAD STEP C OUT: 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G08

3.3V AT 3A/µs LOAD STEP C OUT: 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP

Start-Up, IOUT = 6A (Resistive Load)Start-Up, IOUT = 0A VIN to VOUT Step-Down Ratio Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, I OUT = 6A VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4603 G09

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4603 G10

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 2A/DIV 100µs/DIV

4603 G11

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 2A/DIV 100µs/DIV

4603 G12

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF INPUT VOL TAGE (V) OUTPUT VOL TAGE (V) 3.0 4.0 5.5 5.0

4603 G13

2.0 1.0 2.5 3.5 4.5 1.5 0.5 4 2 8 6 12 14 1810 20 3.3V OUTPUT WITH 82.5k FROM VOUT TO fSET 5V OUTPUT WITH 150k RESISTOR ADDED FROM fSET TO GND 5V OUTPUT WITH NO RESISTOR ADDED FROM fSET TO GND 2.5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT typical perForMance characteristics(See Figure 18 for all curves)

pin Functions(See Package Description for Pin Assignment) VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. See Figure 15. PGND (Bank 2): Power ground pins for both input and output returns. V OSNS– (Pin M12): (–) Input to the Remote Sense Ampli- fier . This pin connects to the ground remote sense point. The remote sense amplifier is used for V OUT ≤ 3.3V . Tie to INTVCC if not used. NC1 (Pin M12): No internal connection on the L TM4603-1. VOSNS+ (Pin J12): (+) Input to the Remote Sense Ampli- fier . This pin connects to the output remote sense point. The remote sense amplifier is used for V OUT ≤ 3.3V . Tie to ground if not used. NC2 (Pin J12): No internal connection on the L TM4603-1. DIFFV OUT (Pin K12): Output of the Remote Sense Ampli- fier . This pin connects to the VOUT_LCL pin. Leave floating if remote sense amplifier is not used. NC3 (Pin K12): No internal connection on the L TM4603-1. DRV CC (Pin E12): This pin normally connects to INTV CC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 50mA capability, or an external circuit shown in Figure 16. This improves efficiency at the higher input voltages by reducing power dissipation in the module. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator . PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock with a high level above 2V and below INTV CC. See the Applications Information section. TRACK/SS (Pin A9): Output Voltage T racking and Soft- Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn on as a stand alone regulator . Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pin A12): Programmable Margining Input. A re- sistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k W will equal a value in millivolts that is a per centage of the 0.6V refer- ence voltage. See Applications Information. To parallel L TM4603s, each requires an individual MPGM resistor . Do not tie MPGM pins together . MARG1 DRVCC VFB PGOOD SGND V OSNS+ (NC2, L TM4603-1) DIFFVOUT (NC3, L TM4603-1) VOUT_LCL VOSNS– (NC1, L TM4603-1) VIN BANK 1 PGND BANK 2 A B C D E F G H J K L M V OUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS 1 2 3 4 5 6 7 TOP VIEW 8 9 10 11 12

fSET (Pin B12): Frequency Set Internally to 1MHz. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. V FB (Pin F12): The Negative Input of the Error Ampli- fier . Internally, this pin is connected to V OUT_LCL with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between VFB and SGND pins. See the Applications Information section. MARG0 (Pin C12): This pin is the LSB logic input for the margining function. Together with the MARG1 pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. MARG1 (Pin D12): This pin is the MSB logic input for the margining function. Together with the MARG0 pin it will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pin H12): Signal Ground. This pin connects to PGND at output capacitor point. COMP (Pin A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. RUN (Pin A10): Run Control Pin. A voltage above 1.9V will turn on the module, and when below 1V , will turn off the module. A programmable UVLO function can be accomplished by connecting to a resistor divider from V IN to ground. See Figure 1. This pin has a 5.1V Zener to ground. Maximum pin voltage is 5V . Limit current into the RUN pin to less than 1mA. V OUT_LCL (Pin L12): VOUT connects directly to this pin to bypass the remote sense amplifier , or DIFFVOUT connects to this pin when the remote sense amplifier is used. VOUT_LCL can be connected to V OUT on the L TM4603-1. VOUT is internally connected to VOUT_LCL through 50W in the L TM4603-1. pin Functions(See Package Description for Pin Assignment)

Figure 1. Simplified L TM4603/L TM4603-1 Block Diagram TA = 25°C, VIN = 12V . Use Figure 1 configuration.

4603 F01

The L TM4603 is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 6A of DC output current with few external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6V DC to 5.0VDC over a 4.5V to 20V wide input voltage. The typical application schematic is shown in Figure 18. The L TM4603 has an integrated constant on-time current mode regulator , ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 1MHz at full load. With current mode control and internal feedback loop compensation, the L TM4603 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while V FB drops. Internal overvolt- age and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output ripple voltage. When DRV CC pin is connected to INTV CC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at the high end of the input voltage range. The L TM4603 has a very accurate differential remote sense amplifier with very low offset. This provides for very accurate output voltage measurement at the load. The MPGM pin, MARG0 pin and MARG1 pin are used to support voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. operation

mined by the maximum load current and output voltage. for a particular application. down ratio that can be achieved for a given input voltage. The PWM controller has an internal 0.6V reference voltage. Table 1. RSET Standard 1% Resistor Values vs VOUT PGM resistor on the MPGM pin programs the current.

  • 10k where RPGM is the resistor value to place on the MPGM pin to ground. The margining voltage, V OUT(MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN Input Capacitors L TM4603 module should be connected to a low AC imped- ance DC source. Input capacitors are required to be placed adjacent to the module. In Figure 18, the 10µF ceramic input capacitors are selected for their ability to handle the large RMS current into the converter . An input bulk capacitor of 100µF is optional. This 100µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. For a buck converter , the switching duty-cycle can be estimated as: D = VOUT VIN Without considering the inductor ripple current, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D •(1− D) In the above equation, η% is the estimated efficiency of the power module. C IN can be a switcher-rated electrolytic aluminum capacitor , OS-CON capacitor or high value ce- ramic capacitor . Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor , applications inForMation

current for the external input capacitors. The L TM4603 is designed for low output ripple voltage. voltage droop and overshoot during a 2.5A/µs transient. capacitance to maximize transient performance. output at 21% duty cycle is ~3A in Figure 3. Figure 2. Normalized Input RMS Ripple Current Figure 3. Inductor Ripple Current vs Duty Cycle

4603 F02

4603 F03

is chosen at a duty cycle of 21%, then 0.6 is the ratio. ripple current reduction as a function of paralleled phases. series resistance (ESR) of the output bulk capacitance. f is frequency and m is the number of parallel phases. steady-state operation but also in response to transients. of its full current limit value. Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI

4603 F04

that is the same as the slave regulator’s feedback divider . output tracking characteristics. voltage will reach its final value before the master output. = 75k. Solve for RB to equal 51.1k. Figure 5. Coincident T racking Schematic Figure 6. Coincident Output T racking Characteristics

4603 F06

4603 F05

The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with a logic input not to exceed 5V . The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = R1+ R2 R2 • 1.5V See the Simplified Block Diagram (Figure 1). Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output volt- ages. Table 2 is provided for most application requirements. L TpowerCAD is available for control loop optimization. PLLIN The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector . This allows the internal top MOSFET turn-on to be locked to the rising edge of an external clock. The frequency range is ±30% around the operating frequency of 1MHz. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns and the amplitude at least 2V . The PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. During start-up of the regulator , the phase-locked loop function is disabled. INTV CC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRV CC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the L TM4603 can be directly powered by Vin. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA • (VIN – 5V) The L TM4603 also provides the external gate driver voltage pin DRV CC. If there is a 5V rail in the system, it is recom- mended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRV CC pin. A 5V output can be used to power the DRVCC pin with an external circuit as shown in Figure 16. Parallel Operation of the Module The L TM4603 device is an inherently current mode con- trolled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. The voltage feedback equation changes with the variable n as modules are paralleled: VOUT = 0.6V 60.4k n + RFB RFB or equivalently, RFB = 60.4k n VOUT 0.6V − 1 where n is the number of paralleled modules. Thermal Considerations and Output Current Derating The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 12, and Figures 13 to 14 for calculating an approximate θ JA for the module with various heat sinking methods. Thermal models are derived from several tem- perature measurements at the bench and thermal modeling analysis. Thermal Application Note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. Tables 3 and 4 provide a summary of the equivalent θ JA for the noted conditions. These equivalent θJA parameters are correlated to the measured values, applications inForMation

4603 F11

Figure 11. No Heat Sink 12VIN Figure 12. BGA Heat Sink 12VIN Figure 13. 12VIN, 3.3VOUT No Heat Sink Figure 14. 12VIN, 3.3VOUT BGA Heat Sink

4603 F10

4603 F12

4603 F13

4603 F14

4603 F09

4603 F07

4603 F08

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18)

maintained at 100°C or below for the derating curves. to a total of 124°C at the junction of the device. to be provided to protect each unit from catastrophic failure. PCB conduction loss and thermal stress.

  • Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
  • Place a dedicated power ground layer underneath the unit.
  • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
  • Do not put vias directly on pads.
  • If vias are placed onto the pads, the the vias must be capped.
  • Interstitial via placement can also be used if necessary.
  • Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Figure 15 gives a good example of the recommended layout. Frequency Adjustment The L TM4603 is designed to typically operate at 1MHz across most input conditions. The f SET pin is typically left open. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 1MHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V IN to 3.3VOUT, and produce excessive inductor ripple currents for lower duty cycle applications such as 20V IN to 5V OUT. The 5V OUT and 3.3V OUT drop out curves are modified by adding an external resistor on the f SET pin to allow for lower input voltage operation, or higher input voltage operation. SIGNAL GND VOUT VIN GND COUT CIN CIN COUT

4603 F15

Figure 15. Recommended Layout

L TM4603 minimum on-time = 100ns tON = [(VOUT • 10pF)/IfSET], for VOUT > 4.8V use 4.8V L TM4603 minimum off-time = 400ns tOFF = t – tON, where t = 1/Frequency Duty Cycle = tON/t or VOUT/VIN Equations for setting frequency: IfSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 201µA, tON = [(4.8 • 10pF)/IfSET], tON = 239ns, where the internal RfSET is 33.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20 • 239ns)) ~ 1MHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor . This is noted in the Inductor Ripple Current vs Duty Cycle graph at ~5A at 25% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f SET to ground to increase the switching frequency. A 3A ripple current is chosen, and the total peak current is equal to 1/2 of the 3A ripple current plus the output current. The 5V output current is limited to 5A, so total peak current is less than 6.5A. This is below the 7A peak specified value. A 150k resistor is placed from f SET to ground, and the parallel combination of 150k and 33.2k equates to 27.2k. The I fSET calculation with 27.2k and 20V input voltage equals 245µA. This equates to a tON of 196ns. This will increase the switching frequency from 1MHz to ~1.28MHz for the 20V to 5V conversion. The minimum on time is above 100ns at 20V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10V for the 1.28MHz operation due to the 400ns minimum off time. Equation: t ON = (VOUT/VIN)

  • (1/Frequency) equates to a 382ns on time, and a 400ns off time. The V IN to VOUT Step-Down Ratio curve reflects an operating range of 10V to 20V for 1.28MHz operation with a 150k resistor to ground, and an 8V to 16V operation for f SET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off time. Example for 3.3V Output L TM4603 minimum on-time = 100ns tON = [(VOUT • 10pF)/IfSET] L TM4603 minimum off-time = 400ns tOFF = t – tON, where t = 1/Frequency Duty Cycle (DC) = tON/t or VOUT/VIN Equations for setting frequency: IfSET = [VIN/(3 • RfSET)], for 20V operation, IfSET = 201µA, tON = [(3.3 • 10pF)/IfSET], tON = 164ns, where the internal RfSET is 33.2k. Frequency = [V OUT/(VIN • t ON)] = [3.3V/ (20•164ns)] ~ 1MHz. The minimum on-time and minimum off-time are within specification at 164ns and 836ns. However , the 4.5V input to 3.3V output circuit will not meet the minimum off-time specification of 400ns (t ON = 733ns, Frequency = 1MHz, tOFF = 267ns). Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band included. The duty cycle for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t OFF, or (1 – 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. t ON = DC/frequency, or 1.35µs. The fSET pin voltage is 1/3 of VIN, and the IfSET current equates to 45µA with the internal 33.2k. The IfSET current needs to be 24µA for 540kHz operation. A resistor can be placed from V OUT to fSET to lower the effective IfSET current out of the fSET pin to 24µA. The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V , therefore 82.5k will source 21µA into the f SET node and lower the I fSET current to 24µA. This enables the 540kHz operation and the 4.5V to 20V input operation for down converting to 3.3V output. The frequency will scale from 540kHz to 1.2MHz over this input range. This provides for an effective output current of 5A over the input range. applications inForMation

Figure 17. 3.3V at 5A Design Figure 16. 5V at 5A Design Without Differential Amplifier

4603 F17

4603 F16

Figure 19. 2-Phase, 2.5V and 1.2V at 6A with Coincident T racking Figure 18. Typical 4.5V to 20VIN, 1.5V at 6A Design *C11 OPTIONAL TO REDUCE LC RINGING.

4603 F19

4603 F18

4-Phase, Four Outputs (3.3V , 2.5V , 1.8V and 1.5V) with Coincident T racking VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4603 392k R11 100k R10 100k R18 19.1k C16 22µF 6.3V C14 10µF 25V 3.3V 2.5V AT 6A R23 60.4k C15 470µF 6.3VMARGIN CONTROL CLOCK SYNC 2 C18 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 3.3V 8V TO 16V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4603 R14 392k R16 100k R15 100k R13 40.2k C16 22µF 6.3V C14 10µF 25V 3.3V R25 60.4k C15 470µF 6.3VMARGIN CONTROL 1.5V AT 6A CLOCK SYNC 4 C24 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V3.3V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4603 392k 100k 100k R12 30.1k 22µF 6.3V 10µF 25V 3.3V R21 60.4k R19 30.1k 470µF 6.3VMARGIN CONTROL 1.8V AT 6A CLOCK SYNC 3 C8 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V ON/OFF R17 59k C26 0.1µF L TC6902 4-PHASE OSCILLATOR 3.3V AT 5A DIV PH OUT1 OUT2 SET MOD GND OUT4 OUT3 VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4603 R27 392k 100k 100k 13.3k 22µF 6.3V 0.15µF 10µF 25V C11 100µF 35V OPT C10 470µF 6.3VMARGIN CONTROL TRACK/SS CONTROL CLOCK SYNC 1 C12 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 3.3V OR APPROPRIATE 3.3V 8V TO 16V 8V TO 16V ON/OFF INTERMEDIATE BUS –48V INPUT R24 19.1k R26 40.2k typical application

NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 118 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.03 2.72 – 2.92 DETAIL BDETAIL A DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 2 3 4 5 6 7 8 9 10 11 BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES SUGGESTED SOLDER PAD LAYOUT TOP VIEW A B C D E F G H K J L M DETAIL A 0.60 – 0.66 0.60 – 0.66 M Y X eee 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 118 0306 REV Ø 118-Lead (15mm × 15mm) (Reference L TC DWG # 05-08-1801 Rev Ø) package Description Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER B 8/11 Updated Note 2 test parameters. Updated the usage of Remote Sense Amplifier pins. Updated the fSET pin description. Updated the Simplified Block Diagram. Added additional information for the tracking applications. Updated the Frequency Adjustment section and equations. Updated the example circuits. Added a package photo. Updated the Related Parts information. 19, 20 22, 23 (Revision history begins at Rev B)

 LINEAR TECHNOLOGY CORPORA TION 2007 LT 0811 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com relateD parts PART NUMBER DESCRIPTION COMMENTS L TM4628 Dual 8A, 26V , DC/DC µModule Regulator 0.6V ≤ VOUT ≤ 5V , Remote Sense Amplifier , Internal Temperature Sensing Output, 15mm × 15mm × 4.32mm LGA L TM4627 20V , 15A DC/DC µModule Regulator 0.6V ≤ VOUT ≤ 5V , PLL Input, Remote Sense Amplifier , VOUT T racking, 15mm × 15mm × 4.32mm LGA L TM4618 26V , 6A DC/DC µModule Regulator 0.8V ≤ VOUT ≤ 5V , PLL Input, VOUT T racking, 9mm × 15mm × 4.32mm LGA L TM4606 28V , 6A EN55022 Class B DC/DC µModule Regulator 0.6V ≤ V OUT ≤ 5V , PLL Input, VOUT T racking and Margining, 15mm × 15mm × 2.82mm LGA L TM4601AHV 28V , 12A DC/DC µModule Regulator 0.6V ≤ VOUT ≤ 5V , PLL Input, Remote Sense Amplifier , VOUT T racking and Margining, 15mm × 15mm × 2.82mm LGA L TM8025 36V IN, 3A DC/DC µModule Regulator 0.8V ≤ VOUT ≤ 24V , CLK Input, 9mm × 15mm × 4.32mm LGA Package L TM6908 50kHz to 10MHz Dual Output Oscillator 90° or 180° Phase Shift Between Outputs, Optional Spread Spectrum Frequency Modulation, 2mm × 3mm DFN typical application 3.3V at 5A, L TM4603-1 (No Remote Sense Amplifier) VOUT VFB MARG0 MARG1 VOUT_LCL NC3 NC2 NC1 PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4603-1 392k 100k 100k RSET 13.3k RfSET 82.5k MARGIN CONTROL 100µF 6.3V

4603 TA05

3.3V TRACK/SS CONTROL 100pF 10µF 35V 10µF 35V V IN fSETPGNDSGND 5% MARGIN VIN 4.5V TO 20V REVIEW TEMPERATURE DERATING CURVE +PGOOD package photograph 15mm 15mm 2.82mm