LTM4602HV

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Technical content

24V, 15A Monolithic Step Down Regulator with Differential Output Sensing The L TC®3613 is a monolithic synchronous step-down switching regulator capable of regulating outputs from 0.6V to 5.5V with up to 15A output current. The controlled on-time constant frequency valley current mode architecture allows for both fast transient response and constant frequency switch- ing in steady-state operation, independent of V IN, VOUT and load. This also provides excellent current sharing capability. Differential output voltage sensing along with a precision internal reference combine to offer ±0.67% output regula- tion, even if the output ground reference deviates from local ground by 500mV. The switching frequency can be programmed from 200kHz to 1MHz with an external resis- tor . The switching frequency is also phase synchronizable to an external clock in applications where switching noise/ EMI reduction is crucial. Very low t ON and tOFF times allow for near 0% and near 100% duty cycles, respectively. Voltage tracking soft start-up is provided for tracking and sequencing applications. Safety fea- tures include output overvoltage protection, programmable current limit with foldback, and power good monitoring. High Efficiency High Power Step-Down Converter Efficiency and Power Loss vs Load Current

APPLICATIONS

n Wide VIN Range: 4.5V to 24V; VOUT Range: 0.6V to 5.5V at up to 15A n 0.67% Output Voltage Accuracy n Controlled On-Time Valley Current Mode Architecture, Excellent Current Sharing Capability n Frequency Programmable from 200kHz to 1MHz and Synchronizable to External Clock n RSENSE or Inductor DCR Current Sensing With Accurate Current Limit n Fast T ransient Response n Differential Output Voltage Sensing Allowing 500mV Common Mode Remote Ground n t ON(MIN) = 65ns; tOFF(MIN) = 105ns n Overvoltage Protection and Current Limit Foldback n Power Good Output Voltage Monitor n Voltage T racking Start-Up n External V CC Input for Bypassing Internal LDO n Micropower Shutdown: I Q = 15μA n 7mm × 9mm 56-pin QFN Package n Distributed Power System n Point-of-Load Converters n Servers VRNG SVIN PVIN MODE/PLLIN VOUTPGOOD RUN SENSE– SENSE+ 100k 10Ω 10Ω INTVCC L TC3613 15k 10k 330μF 0.47μH 1.5mΩ 0.1μF 4.7μF 82μF VOUT 1.5V 15A

3613 TA01

4.5V TO 24V 0.1μF 1000pF TRACK/SS ITH RT 115k 270pF 47pF 0.1μF 21k EXTVCC SGND BOOST SW INTVCC PGND VOSNS+ VOSNS– L, L T , L TC, L TM, OPTI-LOOP , Linear Technology and the Linear logo are registered trademarks and Hot Swap and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5487554, 6580258, 6304066, 6476589, 6774611. LOAD CURRENT (A) 0.01 EFFICIENCY (%) 100 0.1 1

3613 TA01a

0.5 1.0 1.5 2.0 POWER LOSS (W)2.5 3.0 3.5 VIN = 12V VOUT = 1.5V PULSE-SKIPPING MODE FORCED CONTINUOUS MODE

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS INTV CC, EXTVCC, (BOOST-SW), MODE /PLLIN, Operating Junction Temperature Range (Note 1) TOP VIEW WKH PACKAGE 56-LEAD (7mm × 9mm) MULTIPAD QFN PVIN 1 PVIN 2 PVIN 3 PVIN 4 PVIN 5 PVIN 6 PVIN 7 PVIN 8 PVIN 9 SW 10 BOOST 11 SGND 12 PGOOD 13 SNS+ 14 SNS– 15 SGND 16

44 PGND

43 PGND

42 PGND

41 PGND

40 PGND

39 PGND

38 PGND

37 PGND

36 PGND

34 INTV

33 INTVCC

32 SVIN

31 MODE/PLLIN

30 EXTV

29 SGND

VOSNS– 20 VOSES+ 21 TRACK/SS 22 ITH 23 VRNG 24 RT 25 RUN 26 NC 27 SGND 28

56 PVIN

55 PVIN

54 PVIN

53 PVIN

TJMAX = 125°C, θJA = 29°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3613EWKH#PBF L TC3613EWKH#TRPBF L TC3613WKH 56-Lead (7mm × 9mm) Plastic QFN –40°C to 125°C L TC3613IWKH#PBF L TC3613IWKH#TRPBF L TC3613WKH 56-Lead (7mm × 9mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop VIN Input Voltage Operating Range l 4.5 24 V VOUT Output Voltage Operating Range l 0.6 5.5 V IQ Input DC Supply Current Normal Shutdown Supply Current MODE/PLLIN = INTV CC RUN = 0V mA μA VREG Regulated Differential Feedback Voltage OSNS+ – VOSNS–) ITH = 1.2V (Note 3) T A = 25°C T A = 0°C to 85°C T A = –40°C to 125°C l l 0.5985 0.596 0.594 0.6 0.6 0.6 0.6015 0.604 0.606 V V V Regulated Differential Feedback Voltage Over Line, Load and Common Mode OSNS+ – VOSNS–) VIN = 4.5V to 24V , ITH = 0.5V to 1.9V , VOSNS– = ±500mV (Note 3) T A = 0°C to 85°C T A = –40°C to 125°C l l 0.594 0.591 0.6 0.6 0.606 0.609 V V t ON(MIN) Minimum On-Time 65 ns tOFF(MIN) Minimum Off-Time 105 ns gm(EA) Error Amplifier T ransconductance ITH = 1.2V (Note 3) l 1.4 1.7 2 mS VSENSE(MAX) Valley Current Sense Threshold, V SENSE+ – VSENSE–, Peak Current = Valley + Ripple VRNG = 2V , VFB = 0.57V VRNG = 0V , VFB = 0.57V VRNG = INTVCC, VFB = 0.57V l l l 100 120 mV mV mV V SENSE(MIN) Minimum Current Sense Threshold,VSENSE+ – VSENSE–, Force Continuous Operation VRNG = 2V , VFB = 0.63V VRNG = 0V , VFB = 0.63V VRNG = INTVCC, VFB = 0.63V –50 –15 –25 mV mV mV V SENSE(CM) SENSE+, SENSE– Voltage Range (Common Mode) l –0.5 5.5 V ISENSE SENSE+, SENSE– Input Bias Current V SENSE(CM) = 0.6V VSENSE(CM) = 5V ±50 nA μA V RUN(TH) RUN Pin On Threshold VRUN Rising l 1.1 1.2 1.3 V VRUN(HYS) RUN Pin Hysteresis 80 mV ISS Soft-Start Charging Current VTRACKSS = 0V 1.0 μA UVLO INTVCC Undervoltage Lockout INTVCC Undervoltage Lockout Release Falling Rising l l 3.4 3.65 4.2 4.0 4.5 V V I VOSNS+ VOSNS+ Input Bias Current VFB = 0.6V ±5 ±25 nA IVOSNS– VOSNS– Input Bias Current VFB = 0.6V –15 –50 μA The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. SVIN = 15V , VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. SVIN = 15V , VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: T J is calculated from the ambient temperature, TA, and power dissipation, PD, as follows: T J = TA + (PD • 29°C/W) (θJA is simulated per JESD51-7 high effective thermal conductivity test board) θ JC =1°C/W (θJC is simulated when heat sink is applied at the bottom of the package.) Note 3: The L TC3613 is tested in a feedback loop that adjusts V FB = VOSNS+ – VOSNS– to achieve a specified error amplifier output voltage (ITH). Note 4: The L TC3613 is tested under pulsed load conditions such that TJ ≈ TA. The L TC3613E is guaranteed to meet specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3613I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 5: Delay times are measured using 50% levels. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator and Clock Synchronization fOSC Free Running Switching Frequency RT = 205k RT = 80.6k RT = 38.8k 175 450 900 200 500 1000 225 550 1100 kHz kHz kHz CLK IH Clock Input High Level Into Mode/PLLIN 2 V CLKIL Clock Input Low Level Into Mode/PLLIN 0.5 V Internal VCC Regulator and External VCC INTVCC Internal VCC Voltage 6V < VIN < 24V 5.1 5.3 5.55 V INTVCC(%) Internal VCC Load Regulation ICC = 0mA to 50mA –1 –2 % EXTVCC(TH) EXTVCC Switchover Voltage EXTVCC Rising 4.4 4.6 4.75 V EXTVCC(HYS) EXTVCC Switchover Hysteresis 200 mV ΔINTVCC EXTVCC Voltage Drop VEXTVCC = 5V . ICC = 50mA 200 mV PGOOD Output PGDOV PGOOD Upper Threshold VFB Rising (With Respect to Regulated Feedback Voltage VREG) 5 7.5 10 % PGDUV PGOOD Lower Threshold VFB Falling (With Respect to Regulated Feedback Voltage VREG) –10 –7.5 –5 % PGDHYS PGOOD Hysteresis VFB Returning 2 % VPGD(LO) PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V tPGD(FALL) Delay from OV/UV Fault to PGOOD Falling (Note 5) 20 μs tPGD(RISE) Delay from OV/UV Recovery to PGOOD Rising (Note 5) 10 μs RDS(ON) RDS(ON) Top Switch On-Resistance Bottom Switch On-Resistance 7.5 5.5 mohm mohm

TYPICAL PERFORMANCE CHARACTERISTICS Output Regulation vs Input Voltage Output Regulation vs Load Current Output Regulation vs Temperature Switching Frequency vs Input Voltage Switching Frequency vs Load Current Non-Synchronized Switching Frequency vs Temperature Overcurrent Protection Short-Circuit Protection Overvoltage Protection 4ms/DIV 7.5A

3613 G10VIN = 12V

VOUT = 1.5V FIGURE 10 CIRCUIT VOUT 1V/DIV LOAD-STEP TRIGGER ILOAD 10A/DIV VOUT DROOPS DUE TO REACHING CURRENT LIMIT NOTE 200μs/DIV 3613 G11VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT VOUT 1V/DIV ILOAD 10A/DIV SHORT- CIRCUIT TRIGGER NOTE: INDUCTOR CURRENT REACHES CURRENT LIMIT BEFORE FOLDBACK AND DURING SHORT-CIRCUIT RECOVERY SHORT-CIRCUIT REGION 20μs/DIV 3613 G12VIN = 12V VOUT = 1.5V FIGURE 10 CIRCUIT NOTE: SW IS FORCED LOW FOR EXTENDED PERIODS TO REMOVE OVERVOL TAGE V OUT 200mV/DIV IL 10A/DIV SW 20V/DIV OVERVOL TAGE TRIGGER OVERVOL TAGE REGION INPUT VOLTAGE (V) –0.5 ΔVOUT ERROR (%) –0.3 –0.1 0.1 0.3 0.5

3613 G13

VIN = 12V ILOAD = 5A FIGURE 10 CIRCUIT LOAD CURRENT (A) ΔVOUT ERROR (%) 0.3 0.1

3613 G14

–0.1 –0.3 –0.5 3 6 9 15 0.5 VIN = 12V ILOAD = 4A FIGURE 10 CIRCUIT TEMPERATURE (°C) –50 –0.2 NORMALIZED ΔVOUT (%) –0.1 0.1 0.2 –25 0 25 50

3613 G15

VIN = 12V ILOAD = 0A VOUT NORMALIZED AT TA = 25°C FIGURE 10 CIRCUIT VIN (V) –1.0 NORMALIZED Δf (%) –0.5 0.5 1.0 8 16 24

3613 G16

1.5 2.0 4 12 20 VIN = 12V ILOAD = 5A FIGURE 10 CIRCUIT LOAD CURRENT (A) NORMALIZED Δf (%) –0.1 0.1 0.3

3613 G17

–0.3 –0.5 3 6 9 15 0.5 VIN = 12V ILOAD = 4A FIGURE 10 CIRCUIT TEMPERATURE (°C) –50 –2.0 NORMALIZED Δf (%) –1.5 –1.0 –0.5 05 0 100 150

3613 G18

0.5 1.0 –25 25 75 125 VIN = 12V ILOAD = 0A FREQUENCY NORMALIZED AT TA = 25°C FIGURE 10 CIRCUIT TA = 25°C unless otherwise noted

TYPICAL PERFORMANCE CHARACTERISTICS Error Amplifier T ransconductance vs Temperature Current Sense Voltage vs ITH Voltage Maximum Current Sense Voltage vs Temperature RUN Thresholds vs Temperature Input Undervoltage Lockout Thresholds vs Temperature RUN and TRACK/SS Pull-Up Currents vs Temperature TEMPERATURE (°C) –50

1.50 TRANSCONDUCTANCE (mS)

1.55 1.60 1.65 1.70 05 0 100 150

3613 G22

1.75 1.80 –25 25 75 125 ITH VOLTAGE (V) –60 CURRENT SENSE VOLTAGE (mV) –40 1 2 2.5 120

3613 G23

–20 0.5 1.5 100 VRNG = 0.6V VRNG = 0.9V VRNG = 1.3V VRNG = 1.6V VRNG = 2.0V TEMPERATURE (°C) MAXIMUM CURRENT SENSE VOLTAGE (mV) 05 0 100 150

3613 G24

–25 25 75 125 VRNG = 2V VRNG = 1V VRNG = 0.6V TEMPERATURE (°C) –50 RUN PIN THRESHOLDS (V) 0.8 1.2 150

3613 G25

0.4 0 50 100–25 25 75 125 1.6 0.6 1.0 0.2

1.4 SWITCHING REGION

TEMPERATURE (°C) –50 3.3 UVLO THRESHOLDS (V) 3.5 3.7 3.9 4.1 05 0 100 150

3613 G26

4.3 4.5 –25 25 75 125 UVLO RELEASE (INTVCC RISING) UVLO LOCK (INTVCC FALLING) TEMPERATURE (°C) –50 0.6 CURRENT (μA) 0.8 1.0 1.2 1.4 05 0 100 150

3613 G27

1.6 1.8 RUN –25 25 75 125 TRACK/SS TA = 25°C unless otherwise noted

PVIN (Pins 1-9, 53-56, 57 Exposed Pad): Power Supply Inputs. These pins connect to the drain of the internal power MOSFETS. The PVIN exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. The supply voltage can range from 4.5V to 24V. The voltage on this pin is also used to adjust the TG on-time in order to maintain constant frequency operation. SW (Pins 10, 35, 45-51, 58 Exposed Pad): Switch Node Connection. The (–) terminal of the bootstrap capacitor , C B, connects to this node. This pin swings from a diode voltage below ground up to VIN. The SW exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. BOOST (Pin 11): Boosted Driver Supply Connection. The (+) terminal of the bootstrap capacitor, C B, as well as the cathode of the Schottky diode, D B, connects to this node. This node swings from INTVCC – VSCHOTTKY to VIN + INTVCC – VSCHOTTKY. SGND (Pins 12, 16, 17, 19, 28, 29, 59 Exposed Pad): Signal Ground Connection. The SGND exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. All small-signal components should be connected to the signal ground. Connect signal ground to power ground only at one point using a single PCB trace. PGOOD (Pin 13): Power Good Indicator Output. This open-drain logic output is pulled to ground when the output voltage is outside of a ±7.5% window around the regulation point. SENSE + (Pin 14): Differential Current Sensing (+) Input. For R SENSE current sensing, Kelvin (4-wire) connect SENSE+ and SENSE– pins across the sense resistor . For DCR sensing, Kelvin connect SENSE + and SENSE– pins across the sense filter capacitor . SENSE – (Pin 15): Differential Current Sensing (–) Input. For RSENSE current sensing, Kelvin (4-wire) connect the SENSE+ and SENSE– pins across the sense resistor. For DCR sensing, Kelvin connect the SENSE+ and SENSE– pins across the sense filter capacitor . VOUT (Pin 18): Output voltage sense for adjusting the on-time for constant frequency operation. Tying this pin to the local output (instead of the remote output) is recom- mended for most applications. This pin can be programmed as needed for achieving the steady-state on-time required for constant frequency operation. V OSNS– (Pin 20): Differential Output Sensing (–) Input. Connect this pin to the negative terminal of the output capacitor. There is a bias current of 35μA (typical) flowing out of this pin. V OSNS+ (Pin 21): Differential Output Sensing (+) Input. Connect this pin to the feedback resistor divider between the positive and negative output capacitor terminals. In normal operation the L TC3613 will regulate the differen- tial output voltage which is divided down to 0.6V by the feedback resistor divider. TRACK/SS (Pin 22): External T racking and Soft-Start Input. The L TC3613 regulates the differential feedback voltage OSNS+ − VOSNS–) to the smaller of 0.6V or the voltage on the TRACK/SS pin. An internal 1.0μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to the final regulated output voltage. Alternatively, another voltage supply connected through a resistor divider to this pin allows the output to track the other supply during start-up. ITH (Pin 23): Current Control Voltage and Switching Regu- lator Compensation Point. The current sense threshold increases with this control voltage which ranges from 0V to 2.4V. V RNG (Pin 24): Current Sense Voltage Range Input. The maximum allowed sense voltage between SENSE + and SENSE– is equal to 0.05 • VRNG. If VRNG is tied to SGND, the device operates with a maximum sense voltage of 30mV. If VRNG is tied to INTVCC, the device operates with a maximum sense voltage of 50mV. RT (Pin 25): Switching Frequency Programming Pin. Connect an external resistor from RT to signal ground to program the switching frequency between 200kHz and 1MHz. An external clock applied to MODE/PLLIN must be within ±30% of this free-running frequency to ensure frequency lock.

RUN (Pin 26): Digital Run Control Input. RUN self biases high with an internal 1.3μA pull-up. Forcing RUN below 1.2V disables switching. Taking RUN below 0.75V shuts down all bias and places the L TC3613 into micropower shutdown mode of approximately 15μA. EXTV CC (Pin 30): External VCC Input. When EXTVCC exceeds 4.6V , an internal switch connects this pin to INTVCC and shuts down the internal regulator so that the controller and gate drive power is drawn from EXTVCC. EXTVCC should not exceed VIN. MODE/PLLIN (Pin 31): External Clock Synchronization Input and/or Forced Continuous Mode Input. When an external clock is applied to this pin, the rising switching cycle will be synchronized with the rising edge of the external clock. Additionally, this pin determines operation under light load conditions. When either a clock input is detected or MODE/PLLIN is tied to INTV CC, forced continu- ous mode operation is selected. Tying this pin to SGND allows discontinuous pulse-skipping mode operation at light loads. SV IN (Pin 32): Signal Input Supply. This pin powers the internal control circuitry. INTV CC (Pins 33, 34): Internal 5.3V Regulator Output. The driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7μF ceramic capacitor (C VCC). The anode of the Schottky diode, DB, connects to this pin. PGND (Pins 36-44): Power Ground Connection. Connect this pin as close as practical to the (–) terminal of C VCC and the (–) terminal of CIN.

– + – + ICMP EA (gm(EA) = 1.7mS) 0.645V 0.555V 0.6V 1μA IREV LOGIC CONTROL PLL SYSTEM ONE-SHOT TIMER CLOCK DETECT OSCILLATOR LDO OUT EN IN SVIN 4.2V TIME ADJUST STOP START1.2V 0.75V DA (A = 1) RPGD PGOOD MODE/PLLIN VRNG ITH VOSNS– VOSNS+ TRACK/SS SENSE– SENSE+ PGND SW EXTVCC BO0ST INPUT SUPPL Y DB CBMT MB L COUT RFB2 RFB1 RSENSE PVIN INTVCC INTVCC SGND RITH CITH1 INTVCC INTVCC 3.65V UVLO 4.6V VOUT RT RT RUN 1.3μA CVCC VIN CIN VOUT CIN CSS 3613 FD UV OV TG DRV BG DRV CLOCK OPERATION Main Control Loop The L TC3613 uses valley current mode control to regulate the output voltage in a monolithic, all N-channel MOSFET DC/DC step-down converter. Current control is achieved by sensing the inductor current across SENSE + and SENSE–, either by using an explicit resistor connected in series with the inductor or by implicitly sensing the inductor’s resis- tive (DCR) voltage drop through an RC filter connected across the inductor. In normal steady-state operation, the top MOSFET is turned on for a fixed time interval proportional to the delay in the one-shot timer . The PLL system adjusts the delay in the one-shot timer until the top MOSFET turn-on is synchro- nized either to the internal oscillator or the external clock input if provided. As the top MOSFET turns off, the bottom MOSFET turns on with a small time delay (dead time) to avoid shoot-through current. The next switching cycle is initiated when the current comparator , I CMP, senses that inductor current has reached the valley threshold point (Refer to Functional Diagram)

OPERATION (Refer to Functional Diagram) and turns the bottom MOSFET off immediately and the top MOSFET on. Again in order to avoid shoot-through current there is a small dead time delay before the top MOSFET turns on. The voltage on the ITH pin sets the I CMP valley threshold point. The error amplifier , EA, adjusts this ITH voltage by comparing the differential feedback signal, V OSNS+ − VOSNS–, to a 0.6V internal reference voltage. Consequently, the L TC3613 regulates the output voltage by forcing the differential feedback voltage to be equal to the 0.6V internal reference. The difference amplifier, DA, converts the dif- ferential feedback signal to a single-ended input for the EA. If the load current increases, it causes a drop in the differential feedback voltage relative to the reference. The EA forces ITH voltage to rise until the average inductor current again matches the load current. Differential Output Sensing The output voltage is resistively divided externally to create a feedback voltage for the controller. The internal difference amplifier , DA, senses this feedback voltage along with the output’s remote ground reference to create a differential feedback voltage. This scheme overcomes any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. The L TC3613 allows for remote output ground deviations as much as ±500mV with respect to local ground. INTV CC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. Power on the INTVCC pin is derived in two ways: if the EXTV CC pin is below 4.6V , then an internal 5.3V low dropout linear regulator, LDO, supplies INTV CC power from PVIN; if the EXTVCC pin is tied to an external source larger than 4.6V , then the LDO is shut down and an internal switch shorts the EXTV CC pin to the INTVCC pin, thereby powering the INTVCC pin with the external source and helping to increase overall efficiency and decrease internal self heating through power dissipated in the LDO. This external power source could be the output of the step-down switching regulator itself if the output is programmed to higher than 4.6V . The top MOSFET driver is biased from the floating boot- strap capacitor , C B, which normally recharges during each off cycle through an external Schottky diode when the top MOSFET turns off. If the V IN voltage is low and INTVCC drops below 3.65V, undervoltage lockout circuitry disables the external MOSFET driver and prevents the power switches from turning on. Shutdown and Start-Up The L TC3613 can be shut down using the RUN pin. Pull- ing this pin below 1.2V prevents switching, and less than 0.75V disables most of the internal bias circuitry, including the INTV CC regulator . When RUN is less than 0.75V , the shutdown IQ is about 15μA. Pulling the RUN pin between 0.75V and 1.2V enables the controller into a standby mode where all internal circuitry is powered-up except for the MOSFET driver. The standby I Q is about 2mA. Releasing the RUN pin from ground allows an internal 1.3μA current to pull the pin above 1.2V and fully enable the controller including the MOSFET driver . Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. When pulled up by a resistor to an external voltage, the RUN pin will sink about 35μA of current before reaching 6V . If the external voltage is above 6V (e.g., V IN), select a large enough resistor value so that the voltage on RUN will not exceed 6V. The start-up of the output voltage, V OUT, is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the 0.6V internal reference, the L TC3613 regulates the differential feedback voltage to the TRACK/SS voltage instead of the 0.6V reference. This allows the TRACK/SS pin to be used for programming a ramp-up time for V OUT by connecting an external capacitor from the TRACK/SS pin to SGND. An internal 1μA pull-up current charges this capacitor , creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises from 0V to 0.6V (and beyond), the L TC3613 forces the output voltage, V OUT , to ramp up smoothly to its final value. Alternatively, the TRACK/SS pin can be used to track the start-up of V OUT to another external supply as in a master slave configuration. Typically, this requires connecting a resistor divider from the master supply to the TRACK/SS pin (see Soft-Start and T racking).

When the RUN pin is pulled low to disable the controller or when INTVCC drops below its undervoltage lockout thresh- old of 3.65V, the TRACK/SS pin is pulled low internally. Light Load Current Operation When the DC load current is less than 1/2 of the peak- to-peak inductor current ripple, the inductor current can drop to zero or become negative. If the MODE/PLLIN pin is connected to SGND, the L TC3613 will transition into discontinuous mode operation (also called pulse-skipping mode), where a current reversal comparator , I REV , detects and prevents negative inductor current by shutting off the bottom MOSFET , MB. In this mode, both switches remain off with the output capacitor supplying the load current. As the output capacitor discharges and the output volt- age droops lower , the EA will eventually move the ITH voltage above the zero current level to initiate another switching cycle. If the MODE/PLLIN pin is tied to INTV CC or an external clock is applied to MODE/PLLIN, the L TC3613 will be forced to operate in continuous mode (forced continuous mode) and not transition into discontinuous mode. In this case the current reversal comparator , I REV , is disabled, allowing the inductor current to become negative and thus maintain constant frequency operation. Frequency Selection and External Clock Synchronization The steady-state switching frequency of the L TC3613 is set by an internal oscillator . The frequency of this internal oscillator can be programmed from 200kHz to 1MHz by connecting a resistor from the RT pin to SGND. The RT pin is forced to 1.2V internally. A phase-locked loop (PLL) system synchronizes the turn-on of the switching cycle to this internal oscillator when no external clock is provided. For applications with stringent frequency or interfer- ence requirements, an external clock source connected to the MODE/PLLIN pin can be used to synchronize the switching cycle turn-on to the rising edge of the clock. The L TC3613 operates in forced continuous mode when it is synchronized to the external clock. The external clock frequency has to be within ±30% of the internal oscillator frequency for successful synchronization and the clock input levels should be greater than 2V for HI and less than 0.5V for LO. The MODE/PLLIN pin has an internal 600kΩ pull-down resistor. Power Good and Fault Protection The power good pin, PGOOD, is connected internally to an open-drain N-channel MOSFET . An external pull-up resistor to a voltage supply of up to 6V (or INTV CC) completes the power good detection scheme. Overvoltage and undervolt- age comparators OV and UV turn on the MOSFET and pull the PGOOD pin low when the differential feedback voltage is outside a ±7.5% window of the 0.6V reference voltage. The PGOOD pin is also pulled low when the L TC3613 is in the soft-start or tracking phase, when in undervoltage lockout, or when the RUN pin is low (shut down). When the differential feedback voltage is within the ±7.5% requirement, the open-drain NMOS is turned off and the pin is pulled up by an external resistor. There is an internal delay of 10μs before the PGOOD pin will indicate power good once the differential feedback voltage is within the ±7.5% window. When the feedback voltage goes out of the ±7.5% window, there is an internal 20μs delay before PGOOD is pulled low. In an overvoltage condition, MT is turned off and MB is turned on immediately without any delay and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As the differential feedback voltage drops, the current threshold voltage on the ITH pin is pulled down and clamped to 1.2V. This reduces the inductor valley current level to one-fourth of its maximum value as the differential feedback approaches 0V. Foldback current limiting is disabled at start-up.

differential output voltage is 5.5V . Figure 1. Setting Output Voltage

3613 F01

the power and ground lines due to parasitic elements. in the output’s power and ground lines.

3613 F02

Figure 2. Differential Output Sensing Used to Correct Line Loss Variations tion range of ±30% around this programmed frequency. Frequency Synchronization for further details. gate charge losses and top MOSFET transition losses.

The inductor value has a direct effect on ripple current. The inductor ripple current, ΔI L, decreases with higher inductance or frequency and increases with higher VIN: ΔIL= VOUT f•L •1 – VOUT VIN Accepting larger values of ΔIL allows the use of low induc- tances, but results in higher output voltage ripple, higher ESR losses in the output capacitor , and greater core losses. A reasonable starting point for setting ripple current is ΔI L = 0.4 • I OUT(MAX) where I OUT(MAX) is the maximum output current for the application. The maximum ΔI L occurs at the maximum input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L= VOUT f•Δ IL(MAX)

• 1– VOUT VIN(MAX) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot tolerate the core loss of low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mμ cores. Ferrite core material saturates hard, meaning that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! A variety of inductors designed for high current, low volt- age applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay, Pulse and Würth. Current Sense Pins and Current Limit Programming Inductor current is sensed through the SENSE + and SENSE– pins and fed into the internal current compara- tors. The common mode input voltage range of the cur- rent comparators is –0.5V to 5.5V. Both SENSE pins are high impedance inputs. When the common mode range is between –0.5V to 1.1V , there is no input bias current, and when between 1.4V and 5.5V , there is less than 1μA of current flowing into the pins. Between 1.1V and 1.4V , the input bias current will be zero if the common mode voltage is ramped up from 1.1V and less than 1μA if the common mode voltage is ramped down from 1.4V. The high impedance inputs to the current comparator allow accurate DCR sensing. However , care must be taken not to float these pins during normal operation. The maximum allowed sense voltage V SENSE(MAX) between SENSE+ and SENSE– is set by the voltage applied to the VRNG pin and is given by: V SENSE(MAX) = 0.05 • VRNG The current mode control loop does not allow the induc- tor current valleys to exceed 0.05 • VRNG. The maximum output current is given by: IOUT(MAX) = VSENSE(MAX) RSENSE + 1 2 ΔIL The VSENSE(MAX) is shown in the figure “Maximum Current Sense Voltage vs Temperature” in the Typical Performance Characteristics. Note that ITH is close to 2.4V when in current limit. An external resistive divider from INTV CC can be used to set the voltage on the V RNG pin between 0.6V and 2V , resulting in maximum sense voltages between 30mV and 100mV. The wide voltage sense range allows for a variety of applications. The V RNG pin can also be tied to either SGND or INTVCC to force internal defaults. When VRNG is tied to SGND, the device operates with a maximum sense voltage of 30mV. When the V RNG pin is tied to INTVCC, the device operates with a maximum sense voltage of 50mV . When setting current limit, ensure that the junction temperature does not exceed the rating of 125°C.

be built into these calculations. capacitor , resulting in a time constant of 20ns. The filter components need to be placed close to the IC. efficiency compared to DCR sensing.

3613 F03

Figure 3. RSENSE Current Sensing

3613 F04

Figure 4. DCR Current Sensing

The inductor DCR is sensed by connecting an RC filter across the inductor. This filter typically consists of one or two resistors (R1 and R2) and one capacitor (C1) as shown in Figure 4. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR multiplied by R2/(R1 + R2). Therefore, R2 may be used to scale the voltage across the sense terminals when the DCR is greater than the target sense resistance. With the ability to program current limit through the V RNG pin, R2 may be optional. C1 is usually selected to be in the range of 0.01μF to 0.47μF. This forces R1|| R2 to around 2k to 4k, reducing error that might have been caused by the sense pins’ input bias currents. The first step in designing DCR current sensing is to determine the DCR of the inductor . Where provided, use the manufacturer’s maximum value, usually given at 25°C. Increase this value to account for the temperature coef- ficient of resistance, which is approximately 0.4%/°C. A conservative value for inductor temperature T L is 100°C. The DCR of the inductor can also be measured using a good RLC meter , but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ datasheets for detailed information. From the DCR value, V SENSE(MAX) is calculated as: VSENSE(MAX) =DCRMAX at 25°C• 1+0.4% TL(MAX) –25°C()⎡⎣ ⎤

• I OUT(MAX) –ΔIL /2⎡⎣ ⎤ If VSENSE(MAX) is within the maximum sense voltage of the L TC3613 as programmed by the VRNG pin (30mV to 100mV), then the RC filter only needs R1. If VSENSE(MAX) is higher , then R2 may be used to scale down the maximum sense voltage so that it falls within range. The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS R1() = VIN(MAX) –VOUT() • VOUT Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or R SENSE sensing. Light load power loss can be modestly higher with a DCR network than with a sense resistor due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor , reduces conduc- tion losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal-to-noise ratio for the current sense signal, use a minimum ΔV SENSE of 10mV . For a DCR sensing application, the actual ripple voltage will be determined by: ΔVSENSE = VIN –VOUT R1•C1 • VOUT VIN • f Operating Multiple Units in Parallel The L TC3613’s current mode control architecture makes it straightforward to parallel multiple units for higher output current. Figure 13 shows an example circuit of two L TC3613s placed in parallel to provide 30A at 1.2V from a 6V to 24V input. The signals at MODE/PLLIN are 180° out of phase, to reduce stress on the input and output capacitors. Since the ITH pin voltage determines the cycle-by-cycle valley inductor current, sharing is achieved by connecting the ITH pins together. Because the ITH pin is sensitive to noise, a small 22pF to 47pF decoupling capacitor should

be placed close to each ITH pin. If a compensation scheme is stable on a single phase application, a polyphase ap- plication with N phases should be compensated as: C ITH1 = N • C ITH(SINGLE), C ITH2 = N • C ITH2(SINGLE) and RITH = RITH(SINGLE)/N. The TRACK/SS pins should be connected together so that all L TC3613s start up with the same slew rate. The V OSENSE+ pins of paralleled L TC3613s should be connected together to prevent any false triggering of overvoltage and short circuit protection. Only one divider is necessary. The remote output and ground traces should be routed together as differential pairs and terminated at the same remote sensing location (preferably Kelvin connected across the bulk capacitors at the remote output point). The smaller value ceramic input and output capacitors, however , should be in close proximity to the ICs. C IN and COUT Selection In continuous mode, the current into PVIN is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor cur- rent is given by: IRMS ≅IOUT(MAX) • VOUT VIN

• VIN VOUT This formula has a maximum at VIN = 2VOUT , where IRMS = IOUT(MAX)/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Note that capacitor manufactur- ers’ ripple current ratings for electrolytic and conductive polymer capacitors are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. The selection of C OUT is primarily determined by the effec- tive series resistance, ESR, to minimize voltage ripple. The output ripple, ΔVOUT , in continuous mode is determined by: ΔVOUT ≤ΔIL RESR + 1 8• f•COUT The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the peak-to-peak current ripple requirement. The choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezo- electric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When using ceramic input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the regulator. For high switching frequencies, reducing output ripple and better EMI filtering may require small-value capacitors that have low ESL (and correspondingly higher self resonant frequencies) to be placed in parallel with larger value capacitors that have higher ESL. This will ensure good noise and EMI filtering in the entire frequency spectrum of interest. Even though ceramic capacitors generally have good high frequency performance, small ceramic capacitors may still have to be parallel connected with large ones to optimize performance.

Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor , CB, connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to V IN and the BOOST pin rises to approximately PVIN + INTVCC. The boost capacitor needs to store approximately 100 times the gate charge required by the top MOSFET . In most applications a 0.1μF to 0.47μF , X5R or X7R dielectric capacitor is adequate. It is recommended that the BOOST capacitor be no larger than 10% of the INTV CC capacitor , CVCC, to ensure that the CVCC can supply the upper MOSFET gate charge and BOOST capacitor under all operating conditions. Variable frequency in response to load steps offers superior transient performance but requires higher instantaneous gate drive. Gate charge demands are greatest in high frequency low duty factor applications under high dI/dt load steps and at start-up. In order to minimize SW node ringing and EMI, connect a 5Ω to 10Ω resistor in series with the BOOST pin. Make the C B and DB connections on the other side of the resistor . This series resistor helps to slow down the SW node rise time, limiting the high dI/dt current through the top MOSFET that causes SW node ringing. INTV CC Regulator and EXTVCC Power The L TC3613 features a PMOS low dropout linear regulator (LDO) that supplies power to INTVCC from the SVIN supply. INTVCC powers much of the L TC3613’s internal circuitry. The LDO regulates the voltage at the INTVCC pin to 5.3V . The LDO can supply a maximum current of 50mARMS and must be bypassed to ground with a minimum of 4.7μF ceramic capacitor . Good bypassing is needed to supply the high transient currents required by the power MOSFET gate drivers. APPLICATIONS INFORMATION When the voltage applied to EXTVCC pin rises above 4.6V , the INTVCC LDO is turned off and the EXTVCC is connected to INTVCC with an internal switch. This switch remains on as long as the voltage applied to EXTV CC remains above 4.4V . Using the EXTVCC allows the MOSFET driver and control power to be derived from the L TC3613’s switching regulator output during normal operation and from the LDO when the output is out of regulation (e.g., start-up, short circuit). If more than 50mA RMS current is required through EXTVCC, then an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that this external voltage source is less than SVIN. Significant efficiency and thermal gains can be realized by powering INTV CC from the switching regulator output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). The following list summarizes the four possible connec- tions for EXTV CC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.3V LDO resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to switching regulator output VOUT > 4.6V. This provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 4.6V or greater external supply is available, it may be used to power EXTV CC provided that the external supply is suf- ficient enough for MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage converters, efficiency gains can still be realized by connecting EXTV CC to an output-derived voltage that has been boosted to greater than 4.6V .

too low due to the dropout voltage. to ensure that an adequate gate-drive voltage is present. lations when there are disturbances on INTVCC. reaching about 35μA for RUN = 6V. with a capacitor or track the output of an external supply. to the ramp rate on the TRACK/SS pin. the TRACK/SS pin to scale the ramp rate appropriately. a different ratio than the differential feedback (Figure 7). small enough to make this offset error negligible.

3613 F05

Figure 5. Setup for VIN ≤ 5V

Figure 6. T wo Different Modes of Output T racking Figure 7. Setup for Coincident and Ratiometric T racking

3613 F07

if the pin is left floating.

tion and therefore maintain constant frequency operation. Off-Time and Dropout Operation.

3613 F08

Figure 8. Phase and Frequency Locking Behavior During T ransient Load Conditions lock can still be maintained. free-running frequency) for normal and heavy loads.

Minimum On-Time, Minimum Off-Time and Dropout Operation The minimum on-time is the smallest duration of time in which the L TC3613 can keep its top power MOSFET in its on state. This minimum on-time is 65ns for the L TC3613 and is achieved when the V OUT pin is tied to its minimum value of 0.6V while the PVIN is tied to its maximum value of 24V. For larger values of V OUT or smaller values of PVIN, the minimum on-time achievable will be longer than 65ns. The minimum on-time will have a dependency on the operating conditions of the switching regulator , but is intended to be smaller for high step-down ratio applica- tions that will require low on-times. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: D MIN = f • tON(MIN) where tON(MIN) is the minimum on-time for the switching regulator . As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. If the application requires a smaller than minimum duty cycle, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value or lose frequency synchronization if using an external clock. Depending on the application, this may not be of critical importance. The minimum off-time is the smallest duration of time that the top power MOSFET can be turned off and then immediately turned back on. The minimum off-time that the L TC3613 can achieve is 105ns. The minimum off-time limit imposes a maximum duty cycle of: D MAX = 1 – f • tOFF(MIN) where tOFF(MIN) is the minimum off-time of the switching regulator . Reducing the operating frequency alleviates the maximum duty cycle constraint. If the maximum duty cycle is reached, due to a drooping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT DMAX At the onset of dropout, there is a region of PV IN about 500mV that generates two discrete off-times, one being the minimum off-time and the other being an off-time that is about 40ns to 60ns larger than the minimum off-time. This secondary off-time is due to the longer delay in trip- ping the internal current comparator . The two off-times average out to the required duty cycle to keep the output in regulation with the output ripple remaining the same. However , there is higher SW node jitter , especially appar- ent when synchronized to an external clock. Depending on the application, this may not be of critical importance. Fault Conditions: Current Limiting and Overvoltage The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the L TC3613, the maximum sense voltage is controlled by the voltage on the V RNG pin. With valley current mode control, the maximum sense voltage and the sense re- sistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSENSE(MAX) RSENSE + 1 2 •Δ IL The current limit value should be checked to ensure that ILIMIT(MIN) > I OUT(MAX). The current limit value should be greater than the inductor current required to produce maximum output power at the worst-case efficiency. Worst-case efficiency typically occurs at the highest PV IN and highest ambient temperature.

To further limit current in the event of a short circuit to ground, the L TC3613 includes foldback current limiting. If the output fails by more than 50%, then the maximum sense voltage is progressively lowered to about one-fourth of its full value. If the output exceeds 7.5% of the programmed value, then it is considered as an overvoltage (OV) condition. In such a case, the top MOSFET is immediately turned off and the bottom MOSFET is turned on indefinitely until the OV condition is removed. Current limiting is not ac- tive during an OV. If the output returns to a nominal level, then normal operation resumes. If the OV persists a long time, the current through the inductor could exceed its maximum rating. OPTI-LOOP Compensation OPTI-LOOP compensation, through the availability of the ITH pin, allows the transient response to be optimized for a wide range of loads and output capacitors. The ITH pin not only allows optimization of the control loop behavior but also provides a test point for the step-down regulator ’s DC-coupled and AC-filtered closed-loop response. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at this pin. The ITH series R ITH-CITH1 filter sets the dominant pole-zero loop compensation. Additionally, a small capacitor placed from the ITH pin to SGND, CITH2, may be required to at- tenuate high frequency noise. The values can be modified to optimize transient response once the final PCB layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The general goal of OPTI-LOOP compensation is to realize a fast but stable ITH response with minimal output droop due to the load step. For a detailed explanation of OPTI-LOOP compensation, refer to Application Note 76. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT im- mediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT . ΔILOAD also begins to charge or discharge COUT , generating a feedback error signal used by the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem. Connecting a resistive load in series with a power MOSFET, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condi- tion. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated feedback loop response. The gain of the loop increases with R ITH and the bandwidth of the loop increases with decreasing C ITH1. If R ITH is increased by the same factor that CITH1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor , C FF , can be added to improve the high frequency response, as shown in Figure 1. Capacitor C FF provides phase lead by creating a high frequency zero with RFB2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate overall performance of the step-down regulator.

In some applications, a more severe transient can be caused by switching in loads with large (>10μF) input capacitors. If the switch connecting the load has low resistance and is driven quickly, then the discharged input capacitors are effectively put in parallel with C OUT , causing a rapid drop in VOUT . No regulator can deliver enough current to prevent this problem. The solution is to limit the turn-on speed of the load switch driver . A Hot Swap™ controller is designed specifically for this purpose and usually incorporates cur- rent limiting, short-circuit protection and soft starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percent- age of input power . Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses: 1. I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows though the inductor L, but is chopped between the top and bottom MOSFETs. 2. T ransition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V . 3. INTV CC current. This is the sum of the MOSFET driver and control currents. The MOSFET driver current re- sults from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from INTV CC to ground. The resulting dQ/dt is a current out of INTV CC that is typically much larger than the controller IQ current. Supplying INTV CC power through EXTV CC could save several points of efficiency, especially for high VIN ap- plications. Connecting EXTV CC to an output-derived source will scale the VIN current required for the driver and controller circuits by a factor of Duty Cycle/Effi- ciency. For example, in a 20V to 5V application, 10mA of INTV CC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from V IN) to only a few percent. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator . It must have a very low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in cabling, fuses or batteries. Other losses, which include the C OUT ESR loss, bottom MOSFET reverse-recovery loss and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current there is no change in efficiency. Power losses in the switching regulator will reflect as a longer than ideal on-time. This efficiency accounted on- time in continuous mode can be calculated as: tON(REAL) ≈ tON(IDEAL) Efficiency

feedback resistor is also 20k. Select the nearest standard value of 115k. Select 0.56μH, which is the nearest standard value.

3613 F10

3613 F10a

Figure 9. 1.2V , 15A, 350kHz Step-Down Converter

The resulting maximum ripple current is: ΔIL = 1.2V 350kHz•0.56μH • 1– 1.2V 24V ⎝⎜ ⎞ ⎠⎟ ≈ 5.8A Often in high power applications, DCR current sensing is preferred over RSENSE in order to maximize efficiency. In order to determine the DCR filter values, first the induc- tor manufacturer has to be chosen. For this design, the Vishay IHLP-4040DZ-01 model is chosen with a value of 0.56μH and DCR MAX =1.8mΩ. This implies that: VSENSE(MAX) = DCRMAX at 25°C • [1 + 0.4% (TL(MAX) – 25°C)] • [I OUT(MAX) – ΔIL/2] [15A – 5.8A/2] ≈ 28.3mV The maximum sense voltage is within the range that L TC3613 can handle without any additional scaling. There- fore, the DCR filter consists of a simple RC filter across the inductor . If the C is chosen to be 0.1μF , then the R can be calculated as: RDCR = L DCRMAX •CDCR = 0.56μH 1.8mΩ• 0.1μF ≈ 3.11k The closest standard value is 3.09k. The resulting value of V RNG with a 50% design margin factor is: V RNG = VSENSE(MAX)/0.05 • MF To generate the V RNG voltage, connect a resistive divider from INTVCC to SGND with RDIV1 = 52.3k and RDIV2 = 10k. Select CIN to give an RMS current rating greater than 7A at 75°C. The output capacitor C OUT is chosen for a low ESR of 4.5mΩ to minimize output voltage changes due to inductor ripple current and load steps. The output voltage ripple is given as: ΔV OUT(RIPPLE) = ΔIL(MAX) • ESR = (5.8A)(4.5mΩ) ≈ 26mV However , a 0A to 10A load step will cause an output change of up to: ΔVOUT(STEP) = ΔILOAD • ESR = (10A)(4.5mΩ) = 45mV Optional 100μF ceramic output capacitors are included to minimize the effect of ESR and ESL in the output ripple and to improve load step response. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the L TC3613.

• Multilayer boards with dedicated ground layers are preferable for reduced noise and for heat sinking pur- poses. Use wide rails and/or entire planes for V IN, VOUT and PGND nodes for good filtering and minimal copper loss. Flood unused areas of all layers with copper for better heat sinking.
• Keep signal and power grounds separate except at the point where they are shorted together . Short signal and power ground together only at a single point with a nar- row PCB trace (or single via in a multilayer board). All power train components should be referenced to power ground and all small-signal components (e.g., C ITH1, RT , CSS etc.) should be referenced to signal ground.
• Place CIN, inductor , sense resistor (if used), and primary COUT capacitors close together in one compact area. The SW node should be compact but be large enough to handle the inductor currents without large copper losses. Connect PV IN as close as possible to the (+) plate of CIN capacitor(s) that provides the bulk of the AC current (these are normally the ceramic capaci- tors), and connect PGND as close as possible to the (–) terminal of the same C IN capacitor(s). The high dI/ dt loop formed by C IN, the top MOSFET , and the bot- tom MOSFET should have short leads and PCB trace lengths to minimize high frequency EMI and voltage stress from inductive ringing. The (–) terminal of the primary C OUT capacitor(s) which filter the bulk of the inductor ripple current (these are normally the ceramic capacitors) should also be connected close to the (–) terminal of C IN.

• Place the BOOST, PVIN, SW , and PGND pins facing the power train components. Keep high dV/dt signals on BOOST and SW away from sensitive small-signal traces and components. For RSENSE current sensing, place the sense resistor close to the inductor on the output side. Use a Kelvin (4-wire) connection across the sense resistor and route the traces together as a differential pair . RC filter the differential sense signal close to SENSE +/SENSE– pins, placing the filter capacitor as close as possible to the pins. For DCR sensing, Kelvin connect across the inductor and place the DCR sensing resistor closer to the SW node and further away from the SENSE SENSE– pins. Place the DCR capacitor close to the SENSE+/SENSE– pins.
• Place the resistive feedback divider R FB1/2 as close as possible to VOSNS+/VOSNS– pins and route the remote output and ground traces together as a differential pair and terminate as close to the regulation point as possible (preferably Kelvin connect across the capacitor at the remote output point).
• Place the ceramic C VCC capacitor as close as possible to the INTVCC and PGND pins. Likewise, the CB capacitor should be as close as possible to BOOST and SW pins. These capacitors provide the gate charging currents for the onboard power MOSFETs.
• Place small-signal components as close to their respec- tive pins as possible. This minimizes the possibility of PCB noise coupling into these pins. Give priority to V OSNS+/VOSNS–, SENSE+/SENSE–, ITH, RT and V RNG pins. Use sufficient isolation when routing a clock signal into MODE/PLLIN pin so that the clock does not couple into sensitive small-signal pins.
• Filter the SV IN input to the L TC3613 with a simple RC filter close to the pin. The RC filter should be referenced to signal ground.

3833 F11

Figure 10. 1.5V , 15A, 350kHz High Current Step-Down Converter

3613 F11a

3613 TA02

3613 TA03

Figure 11. 5V , 8A, 200kHz High Efficiency Step-Down Converter

Figure 12. 0.6V , 10A, 200kHz Low Output Voltage Step-Down Converter

3613 TA04

3613 TA05

3613 TA12

Figure 13. 2 Phase, 1.2V , 30A, 350kHz Step-Down Converter

LOAD CURRENT (A) 0.1 EFFICIENCY (%)

3613 TA013

VIN = 12V VOUT = 1.2V FORCED CONTINUOUS MODE 20μs/DIV 3613 TA14 VOUT(AC) 100mV/DIV ILOAD 10A/DIV LOAD STEP = 0A TO 30A V IN = 12V Efficiency T ransient Response

7.00 BSC 9.00 BSC 17 1928 BOTTOM VIEW (BOTTOM METALLIZATION DETAILS) TOP VIEW

0.50 BSC

0.90 ± 0.10 // ccc C 0.00 – 0.05 MLP56 QFN REV Ø 0310 NX b SEATING PLANE 0.08 C aaa C aaa C M ACBbbb NX A B NOTE: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES (°)

3 THE LOCATION OF THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING

CONVENTION CONFORMS TO JEDEC PUBLICATION 95 SPP-002

4 DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.20mm AND 0.30mm FROM THE TERMINAL TIP . IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

5 COPLANARITY APPLIES TO THE TERMINALS AND ALL OTHER SURFACE

6 DRAWING SHOWN ARE FOR ILLUSTRATION ONLY

0.15 0.10 0.10 PAD 1 CORNER RECOMMENDED SOLDER PAD LAYOUT TOP VIEW 2.90 REF2.63 REF 1.97 ± 0.10 1.97 ± 0.05 3.15 ± 0.10 3.15 ± 0.05 PIN 1 ID 7.50 ± 0.05 9.50 ± 0.05 PACKAGE OUTLINE 0.40 ± 0.05 4.06 ± 0.10

3.82 REF

4.06 ± 0.05 4.76 ± 0.10

1.50 REF

1.78 REF 4.27 ± 0.10 4.27 ± 0.05 1.35 ± 0.05 2.25 ± 0.10 0.25 ± 0.05 1.78 REF 1.35 ± 0.05 0.25 ± 0.05 0.40 ± 0.05 2.63 REF2.90 REF 4.76 ± 0.05 0.58 ± 0.05 0.95 REF 56-Lead QFN Multipad (7mm × 9mm) (Reference LTC DWG # 05-08-1870 Rev Ø) 2.25 ± 0.05 Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 07/12 Clarified Electrical Characteristics Clarified PIn Functions Modified Application Circuit 3, 4

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2011 LT 0712 REV A • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION RDIV1 SVIN PVIN VOUT EXTVCCVRNG RUN SENSE– SENSE+ RPGD 100kINTVCC RITH 20k RT 40.2k CSS 0.1μF CITH1 220pF L TC3613 RFB2 147k CFF 22pF RFB1 20k COUT1 22μF 1.2μH RSENSE 10mΩ CB 0.1μF CIN1 47μF 35V

3613 TA10

4.7μF CVCC 4.7μF DB TRACK/SS ITH RT MODE/PLLIN PGOOD SGND BOOST SW INTVCC INTVCC PGND VOSNS+ VOSNS– RVIN 2.2Ω RF1 10Ω RF2 10Ω CVIN 0.1μF CF 1000pF CIN1: KEMET T521X476M035ATE070 DB: DIODES, INC. SDM10K45 L1: WÜRTH 744313120 High Frequency 5V , 4A, 1MHz Step-Down Converter LOAD CURRENT (A) 100

3613 TA11

EFFICIENCY (%) 0.01 100.10 1 FORCED CONTINUOUS MODE PULSE- SKIPPING MODE VIN = 12V VOUT = 5V Efficiency PART NUMBER DESCRIPTION COMMENTS L TC3602 2.5A (I OUT), 3MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 10V , VOUT(MIN) = 0.6V , IQ = 75μA, ISD <1μA, 4mm × 4mm QFN-20, TSSOP-16E Packages L TC3608 18V , 8A (I OUT), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 18V , VOUT(MIN) = 0.6V , IQ = 900μA, ISD <15μA, 7mm × 8mm QFN-52 Package L TC3610 24V , 12A (I OUT), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 24V , VOUT(MIN) = 0.6V , IQ = 900μA, ISD <15μA, 9mm × 9mm QFN-64 Package L TC3611 32V , 10A (I OUT), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 32V , VOUT(MIN) = 0.6V , IQ = 900μA, ISD <15μA, 9mm × 9mm QFN-64 Package L TC3414/ L TC3416 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V , VOUT(MIN) = 0.8V , IQ = 64μA, ISD <1μA, L TC3415 7A (I OUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V , VOUT(MIN) = 0.6V , IQ = 450μA, ISD <1μA, 5mm × 7mm QFN-38 Package L TC3418 8A (I OUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V , VOUT(MIN) = 0.8V , IQ = 380μA, ISD <1μA, 5mm × 7mm QFN-38 Package L TM4600HV 10A Complete Switch Mode Power Supply 92% Efficiency, V IN: 4.5V to 28V , VOUT: 0.6V , T rue Current Mode Control, Ultrafast T ransient Response L TM4601HV 12A Complete Switch Mode Power Supply 92% Efficiency, V IN: 4.5V to 28V , VOUT: 0.6V , T rue Current Mode Control, Ultrafast T ransient Response L TM4602HV 6A Complete Switch Mode Power Supply 92% Efficiency, V IN: 4.5V to 28V , VOUT: 0.6V , T rue Current Mode Control, Ultrafast T ransient Response L TM4603HV 6A Complete Switch Mode Power Supply 93% Efficiency, V IN: 4.5V to 28V , with PLL, Output T racking and Margining