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Technical content

Features

 1.3V Start-up Input Voltage  Output up to 1.5A  Zero Shutdown Mode Supply Current  94% Efficiency  Up to 1.2MHz Switching Frequency  Using Internal Power Switches  Small SOT23-6 Package Typical Application Circuit Pin Configurations LP6205sB6F VDD PGND SW FBGND EN 10uH 100K 1uF Vout_5V 33K 1uF 22pF 110 K + Cout 22uF*3 22pF 22uF SS24 Vin(3.6-5V) ON/OFF S O T 2 3 - 6 TOP View

Preliminary Datasheet LP6205S Functional Pin Description Pin Number Pin Name Function SOT23-6 1 GND Ground. 2 SW Switch pin. 3 GND Ground.

4 FB Feedback

5 VDD Power pin.

6 EN Enable pin

Preliminary Datasheet LP6205S Absolute Maximum Ratings ESD Susceptibility Recommended Operating Conditions

Electrical Characteristics

(VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified) Parameter Test Conditions Min Typ Max Units Start-UP Voltage IL = 1mA 2.5 V Operating VDD Range VDD pin voltage 2.5 6.5 V No Load Current I (VIN) V IN = 2V, VOUT = 6V 26 μA Feedback Reference Voltage Close Loop, VDD = 3.3V 1.25 V Switching Frequency VDD = 3.3V 1200 KHz Maximum Duty VDD = 3.3V 95 % SW ON Resistance VDD = 3.3V 200 m Ω Current Limit Setting VDD = 3.3V 1.5 A Line Regulation V IN = 1.5 ~ 2.5V, IL = 1mA 55 mV/V Load Regulation V IN = 2.5V, IL = 1 ~ 100mA 0.2 mV/mA Temperature Stability for VOUT 50 ppm/ ℃ Thermal Shutdown 165 ℃ Thermal Shutdown Hysterises 10 ℃ Maximum VRS VRS 145 mV

Preliminary Datasheet LP6205S

Application Information

Referring to Typical application circuits, the output voltage of the switching regulator(Vout) can be set with Equation(1): Vout=(1+R1/R2) X 1.25 V Feedback Loop Design Referring to the typical application circuits, the selection of R1 and R2 based on the trade-off between quiescent current consumption and interference immunity is stated below: For applications without standby or suspend modes, lower values of R1 and R2 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1 and R2 are needed. Such high impedance, which requires careful PCB layout and avoid any interference. Especially to FB pin. To improve the system stability a proper value capacitor between FB pin and GND pin is suggested. An empirical suggestion is around 220pF. PCB Layout Guide PCB Layout shall follow these guidelines for better system stability: 1. A full GND plane without any gap break. 2. VDD to GND bypass Cap-The 1uF MLCC noise bypass cap pin4 shall have short and wide connections. 3. Vin to GND bypass Cap-Add a Cap close to the inductor when Vin is not an idea voltage source. 4. Minimize the FB node copper area and keep it far away from noise sources. 5. I follow Equation(1) 6. I Higher R reduces the quiescent current(Path current=1.25V/R2),however resistors beyond 5M/W are not recommended.

Preliminary Datasheet LP6205S Packaging Information S O T 2 3 - 6