LM8333_07 NSC | Alldatasheet
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Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface
1.0 General Description
The LM8333 Mobile I/O Companion offloads the burden of keyboard scanning from the host, while providing extremely low power consumption in both operational and standby modes. It supports keypad matrices up to 8 × 8 in size (plus another 8 special-function keys), for portable applications such as cellphones, PDAs, games, and other handheld ap- plications. Key press and release events are encoded into a byte format and loaded into a FIFO buffer for retrieval by the host pro- cessor. An interrupt output (IRQ) is used to signal events such as keypad activity, a state change on either of two interrupt- capable general-purpose I/O pins, or an error condition. In- terrupt and error codes are available to the host by reading dedicated registers. Four general-purpose I/O pins are available, two of which have interrupt capability. A pulse-width modulated output based on a host-programmable internal timer is also avail- able, which can be used as a general-purpose output if the PWM function is not required. To minimize power, the LM8333 automatically enters a low- power standby mode when there is no keypad, I/O, or host activity. The device is packaged in a 32–pin Leadless Leadframe package (LLP) and a 49-pin MICRO-ARRAY . Both are chip- scale packages.
2.0 Features
■ 8 × 8 standard keys ■ 8 special function keys (SF keys) providing a total of 72 keys for the maximum keyboard matrix ■ ACCESS.bus (I2C-compatible) communication interface to the host ■ Four general purpose host programmable I/O pins with two optional (slow) external Interrupts ■ 16 byte FIFO buffer to store key pressed and key released events ■ Error control with error reports on (FIFO overrun, Keypad overrun, invalid command) ■ Host programmable PWM ■ Host programmable active time and debounce time
3.0 Applications
■ Mobile phones ■ Personal Digital Assistants (PDAs) ■ Smart handheld devices ■ Personal media players
4.0 Block Diagram
I2C® is a registered trademark of Phillips Corporation. © 2007 National Semiconductor Corporation 202106 www.national.com LM8333 Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface
5.0 Ordering Information
NSID Spec. No. of Pins Package Type Temperature Package Method LM8333FLQ8X NOPB 32 LLP −40 to + 85°C 2500 pcs Tape & Reel LM8333FLQ8Y NOPB 32 LLP −40 to + 85°C 250 pcs Tape & Reel LM8333GGR8 NOPB 49 Micro-array −40 to + 85°C 1000 pcs Tape & Reel NOPB = No PB (No Lead)
6.0 Pin Assignments
Leadless Leadframe Package See NS Package Number LQA32A 20210602 Top View See NS Package Number GRA49A www.national.com 2 LM8333
3 www.national.com LM8333
7.0 Signal Descriptions
Name 32 Pins 49 Pins I/O Description WAKE_IN0 29 D7 Input Wake-up input/Keyboard scanning input 0 WAKE_IN1 30 C7 Input Wake-up input/Keyboard scanning input 1 WAKE_IN2 27 E7 Input Wake-up input/Keyboard scanning input 2 WAKE_IN3 28 D6 Input Wake-up input/Keyboard scanning input 3 WAKE_IN4 31 B6 Input Wake-up input/Keyboard scanning input 4 WAKE_IN5 32 A7 Input Wake-up input/Keyboard scanning input 5 WAKE_IN6 1 A6 Input Wake-up input/Keyboard scanning input 6 WAKE_IN7 2 B5 Input Wake-up input/Keyboard scanning input 7 K_OUT0 21 G3 Output Keyboard scanning output 0 K_OUT1 22 F4 Output Keyboard scanning output 1 K_OUT2 23 G4 Output Keyboard scanning output 2 K_OUT3 24 G5 Output Keyboard scanning output 3 K_OUT4 3 A5 Output Keyboard scanning output 4 K_OUT5 4 B4 Output Keyboard scanning output 5 K_OUT6 5 A4 Output Keyboard scanning output 6 K_OUT7 6 A3 Output Keyboard scanning output 7 GEN_IO_0 12 D2 I/O General-purpose I/O 0 GEN_IO_1 13 D1 I/O General-purpose I/O 1 GEN_IO_2 7 B3 I/O General-purpose I/O 2 GEN_IO_3 8 A2 I/O General-purpose I/O 3 SDA 25 F7 I/O ACCESS.bus data signal SCL 26 E6 Input ACCESS.bus clock signal IRQ 17 F2 Output Interrupt request output PWM 16 F1 Output Pulse-width modulated output WD_OUT 18 G1 Output Watchdog timer output (connect to RESET input) RESET 20 F3 Input Reset input CLK_IN 11 B1 Input Clock input (connect to ground through a 68k ohm resistor) VCC 15 E1, E2 n.a. Vcc GND 9, 10, 14 A1, B2, C3, C4, C5, D3, D4, D5, E3, E4, E5 n.a. Ground NC 19 B7, C1, C2, C6, F5, F6, G2, G6, G7 n.a. No connect www.national.com 4 LM8333
8.0 Typical Application
FIGURE 1. Typical Keypad Configuration
8.1 FEATURES
- 8 x 8 standard keys.
- 8 special function keys (SF keys) with wake-up capability by forcing a WAKE_INx pin to ground. Pressing a SF key overrides any other key in the same row.
- A total of 72 keys can be scanned.
- ACCESS.bus (I2C-compatible) interface for communication with the host.
- The watchdog timer is mandatory, so WD_OUT must be connected to RESET.
8.2 I/O EXPANSION OPTIONS
- One host-programmable PWM output which also may be used as a general-purpose output.
- Four host-programmable general-purpose I/O pins, GEN_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. GEN_IO_0 and GEN_IO_1 can also be configured for “slow” interrupts, in which any transition will trigger a hardware interrupt event to the host.
8.3 WATCHDOG TIMER
the timer, connect the WD_OUT output to the RESET input.
8.4 HALT MODE
sumption to the minimum level.
and the host should then repeat the cycle. shares the bus with peripherals that are continuously active. tivity after system initialization.
8.5 KEYPAD SCANNING
tected, the keypad is rescanned after a debounce delay. coded and written to the FIFO buffer. stored in the FIFO or discard them. The SF keys connect the WAKE_INx pins directly to ground.
8.6 COMMUNICATION INTERFACE
MSB (7-bit address mapped to bits 7:1, rather than bits 6:0). Bit 0 is a direction bit (0 on write, 1 on read). serting the IRQ interrupt request.
8.6.1 Interrupts Between the Host and LM8333
sending a Start Condition on the ACCESS.bus interface.
8.6.2 Interrupt Sources
- Any new key-event.
- Any error condition, which is indicated by the error code.
- Any enabled interrupt on either of the GEN_IO_0 or GEN_IO_1 pins that can be configured as external interrupt inputs. When enabled, any rising or falling edge triggers an interrupt. The IRQ output remains asserted until the interrupt code is read.
9.0 Device Operation
9.1 EVENT CODE ASSIGNMENT
After power-on reset, the LM8333 starts scanning the keypad. imize power consumption (<2 µA standby current). released, the MSB of the code is clear. TABLE 1. Keypad Matrix Code Assignments codes loaded into the FIFO buffer.
TABLE 2. Example Sequence of Events FIGURE 2. Example Event Codes Loaded in FIFO Buffer
9.2 I/O EXPANSION
9.2.1 PWM Output with Programmable Duty Cycle
shown in Figure 3. The period TPD is the sum of THI and TLO. 4 shows the command formats. FIGURE 3. Programmable PWM FIGURE 4. PWM Control Commands for Arbitrary Duty Cycle
TABLE 3. Summary of PWM Control Bits
9.2.2 General-Purpose I/O (GPIO)
FIGURE 5. General-Purpose I/O Control Commands put, it can only be configured as an input with a weak pullup. TABLE 4. General Purpose I/O Pin Configuration
9.2.3 External Interrupts
mode, it also wakes up into Active mode. FIGURE 6. SET_EXT_INT Command Data Byte
TABLE 5. Interface Commands for Controlling the LM8333 Read an event from the FIFO. Maximum 14 event codes stored in the FIFO. for example to retry a read after an error. Maximum 14 event codes stored in the FIFO. DEBOUNCE 0x22 W 8 nnnn nnnn Default is 10 ms. Valid range 1–255. GEN_IO_IN 0x30 R 8 0000 nnnn Read port data. GEN_IO_DIR 0x32 W 8 0000 nnnn Select port direction (input or output). PWM_HI 0x40 W 16 (n+1) × tC Sets the low pulse time of the PWM signal. PWM_LO 0x41 W 16 (n+1) × tC Sets the high pulse time of the PWM signal. PWM_CTL 0x42 W 8 0000 0nnn Activate, reactivate, or stop PWM. deasserts the IRQ output, and clears the code. READ_STAT 0xE0 R 8 000n nnnn Status Information. time must be greater than the debounce time. READ_ERROR 0xF0 R 8 0nnn nnnn Reads and clears the error code.
9.3 HOST COMMAND EXECUTION
9.3.1 Command Structure
bytes, and Stop condition for reading the interrupt code. FIGURE 7. Typical Command Sequence from Host
reads from the slave to the host. (0xD0) reads the interrupt code. bit is changed. In this case, the direction bit is changed. The data is sent from the slave to the host in the fourth byte. edgement (NA) to indicate the end of the data.
9.4 HOST WRITE COMMANDS
listed in Figure 9. The SET_EXT_INT command is 0xD1. GEN_IO_0 as an external interrupt input. FIGURE 8. Host Write Command
9.5 HOST READ COMMANDS
address byte, and a data byte. to indicate a write transaction of the command to the LM8333. this case, the direction bit is changed. The data is sent from the slave to the host in the fourth byte. indicate the end of the data. FIGURE 9. Host Read Command
9.6 WAKE-UP FROM HALT MODE
period, so that it can be driven by the LM8333. FIGURE 10. LM8333 Responds with NACK, Host Retries Command
10.0 Interrupts
10.1 INTERRUPT CODE
set when an interrupt occurs. TABLE 6. Interrupt Code ERROR An error condition occurred. EX_1 A rising or falling edge was detected on GEN_IO_1. EX_0 A rising or falling edge was detected on GEN_IO_0. KEYPAD A key-press or key-release event occurred.
10.2 ERROR CODE
the format of the error code. TABLE 7. Error Code
0 FIFOOVR 0 NOINT 0 KEYOVR CMDUNK CMDOVR
FIFOOVR Key event occurred while the FIFO was full. NOINT Interrupt deasserted before it could be serviced. KEYOVR More than two keys were pressed simultaneously. CMDOVR Command received before it could be accepted, e.g. after wake-up.
10.3 STATUS CODES
the status code, for example to synchronize after an error. TABLE 8. Status Codes Reset 0000 0000 Default after reset. Wake Up Interrupt 0000 0010 Wake-up caused by external interrupt. Ack 0000 0110 Last host command was successful. NoAck 0001 0101 Last host command was not successful.
10.4 INTERRUPT PROCESSING
command to read the error code, as shown in Figure 11. FIGURE 11. Interrupt Processing
10.5 COMMAND EXECUTION SUMMARY
- With the interrupt, status, and error codes, the LM8333 provides the features needed to support a reliable key- scan functionality.
- Up to 14 key-scan events can be stored in an internal FIFO buffer. The end of buffer is indicated with the 00 (empty character) code.
- The host can repeatedly read the FIFO without modifying the FIFO pointer using the RPT_FIFO_READ command (0x21), for example if an error is encountered during a read.
- The LM8333 asserts the IRQ output low when a new character is pressed after the last interrupt acknowledge from the host. The IRQ output will be deasserted after the host has acknowledged the interrupt by reading the interrupt code using the READ_INT command (0xD0).
- The host can synchronize with the LM8333 by reading the status code with the READ_STAT command (0xE0). The status code verifies whether the last command was successfully completed.
- Two GPIO pins on the LM8333 may be configured as external interrupt inputs. A rising or falling edge on an enabled interrupt input triggers wake-up from Halt mode and asserts an interrupt to the host by pulling the IRQ output low.
- The host can change the debounce time from the default time of 10 ms. This can be used for reliable scanning of keyboards with noisy contacts. The debounce time can be set to about 1 second in steps of 4 milliseconds. The debounce time is set with the DEBOUNCE command (0x22).
- The host can change the active time permitted before entering Halt mode from the default period of 500 ms. The active time is the time during which the keypad is scanned after the last key is released, before entering Halt mode. The active time must be longer than the debounce time.
- The host can program the direction and output state of four general-purpose I/O pins. The host can also read the states on these pins.
- The host can program a 16-bit timer for generating a PWM output. If the PWM function is not used, the PWM pin can be used as a general-purpose output. 13 www.national.com LM8333
11.0 Absolute Maximum Ratings (Note
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 3.5V Voltage at Any Pin -0.3V to VCC +0.3V Maximum Input Current Without Latchup ±100 mA ESD Protection Level Human Body Model 2 kV Machine Model 200V Total Current into VCC Pin (Source) 80 mA Total Current out of GND Pin (Sink) 60 mA Storage Temperature Range −65°C to +140°C
12.0 DC Electrical Characteristics
(Temperature: -40°C ≤ TA ≤ +85°C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min (Note 2) Typ Max (Note 2) Units VCC Operating Voltage 2.25 2.9 V Power Supply Rise Time from 0.0V 20 µs 10 ms (On Chip Power-On Reset Selected) IDD Supply Current (Note 3) RC Clock = 10 MHz, 6 mA VCC = 2.75V, TC = 1 µs (Note IHALT Standby Mode Current (Note 5) VCC = 2.75V, TC = 0 µs, (Note 4), TA = 25°C <2 15 µA VIL Logical 0 Input Voltage 0.25 VCC V VIH Logical 1 Input Voltage 0.8 VCC V Hi-Z Input Leakage (TRI-STATE Output) VCC = 2.75V -0.1 0.1 µA Input PullupCurrent VCC = 2.75V, VIN = 0V -15 -120 µA Port Input Hysteresis (Note 6) 0.1 V Output Current Source (Weak Pull-Up) VCC = 2.25V, VOH = 1.7V -10 -80 µA Output Current Source (Push-Pull Mode) VCC = 2.25V, VOH = 1.7V -10 mA Output CurrentSink (Push-Pull Mode) VCC = 2.25V, VOL = 0.4V 10 mA Allowable Sink and Source Current per Pin 16 mA CPAD Input Capacitance 8.5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables. Note 2: Data sheet minimum and maximum limits are guaranteed by design, test, or statistical analysis. Note 3: Supply current is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 4: TC = instruction cycle time (min. 0.7 µs). Note 5: In Halt mode, the internal clock is switched off. Supply current in Halt mode is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 6: Guaranteed by design, not tested. www.national.com 14 LM8333
13.0 AC Electrical Characteristics
(Temperature: -40°C ≤ TA ≤ +85°C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions Min (Note 7) Typ Max (Note 7) Units Internal Oscillator External R from CLK_IN to Gnd (R = 68 kohm) 0.75 µs 2.25V ≤ VCC ≤ 2.75V System Oscillator (mclk) External R from CLK_IN to Gnd (R = 68 kohm) 2.25V ≤ VCC ≤ 2.75V 75 ns System Oscillator and Internal Frequency Variation 2.25V ≤ VCC ≤ 2.75V ±30 % Input Pulse Width Low 0.7 µs Input Pulse Width High 0.7 µs ACCESS.bus Input Timing (Note 8) tBUFi Bus free time between Stop and Start Condition tSCLhigho tCSTOHsi SCL setup time Before Stop Condition 8 mclk tCSTRHhi SCL hold time After Start Condition 8 mclk tDHCsi Data High setup time Before SCL Rising Edge (RE) 2 mclk tDLCsi Data Low setup time Before SCL RE 2 mclk tSCLlowi SCL low time After SCL Falling Edge (FE) 12 mclk tSCLhighi SCL high time After SCL RE 12 mclk tSDAhi SDA hold time After SCL FE 0 ns tSDAsi SDA setup time Before SCL RE 2 mclk ACCESS.bus Output Timing (Note 8) tBUFo Bus free time between Stop and Start Condition tSCLhigho tCSTOso SCL setup time Before Stop Condition tSCLhigho tCSTRho SCL hold time After Start Condition tSCLhigho tCSTRso SCL setup time Before Start Condition tSCLhigho tDHCso Data High setup time Before SCL RE tSCLhigho tDLCso Data Low setup time Before SCL RE tSCLhigho tSCLlowo SCL low time After SCL FE 16 mclk tSCLhigho SCL high time After SCL RE 16 mclk tSDAho SDA hold time After SCL FE 7 mclk tSDAvo SDA valid time Before SCL FE 7 mclk Note 7: Data sheet minimum and maximum limits are guaranteed by design, test, or statistical analysis. Note 8: The ACCESS.bus interface of the LM8333 device implements and meets the timing necessary for interface to the I2C bus and SMBus protocol at logic levels. The bus drivers are designed with open-drain output as required for bidirectional operation. The LM8333 device will not meet the AC timing and current/ voltage requirements of the full bus specification. 15 www.national.com LM8333
FIGURE 12. ACCESS.bus Start and Stop Condition Timing
14.0 Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package Order Number LM8333FLQ8X or LM8333FLQ8Y Micro Array Package Order Number LM8333GGR8 17 www.national.com LM8333
LM8333 Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com