7492A NSC | Alldatasheet

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DESCRIPTION — The ’92 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divide-by-six. HIGH signals on the Master Reset (MR) inputs override the clocks and force all outputs to the LOW state. ORDERING CODE: See Section 9 PKGS Plastic DIP (P) Ceramic DIP (D) Flatpak (F ) PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, Ta = 0°C to +70° C 7492APC, 74LS92PC 7492ADC, 74LS92DC 7492AFC, 74LS92FC MILITARY GRADE Vcc = +5.0 V ±10%, Ta = -55° C to +125°C 5492ADM, 54LS92DM 5492AFM, 54LS92FM PKG TYPE CONNECTION DIAGRAM PINOUT A LOGIC SYMBOL 67 1 2 1 1 9 Vcc = Pin 5 GND = Pin 10 NC = Pins 2, 3, 4, 13 INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PIN NAMES DESCRIPTION 54/74 (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH/LOW CPo +2 Section Clock Input (Active Falling Edge) 2.0/2.0 0.125/1.5 CPi -K$ Section Clock Input (Active Falling Edge) 3.0/3.0 0.250/2.0 MRi, MR2 Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 0.5/0.25 Qo -i-2 Section Output* 20/10 10/5.0 (2.5) I 6 -j-6 Section Outputs 20/10 10/5.0 (2.5) ‘The Qo output is guaranteed to drive the full rated fan-out plus the CPi input.

FUNCTIONAL DESCRIPTION — The ’92 is a 4-bit ripple type divide-by-twelve counter. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divideby-six section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to- LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Qo output of each device is designed and specified to drive the rated fan-out plus the CPi input of the device. A gated AND asynchronous Master Reset (MRi, MR 2) is provided which overrides the clocks and resets (clears) all the flip-flops. Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes: A. Modulo 12, Divide-By-Twelve Counter —The CP 1 input must be externally connected to the Qo output. The CPo input receives the incoming count and Q 3 produces a symmetrical divide-by-twelve square wave output. B. Divide-By-Two and Divide-By-Six Counter— No external interconnections are required. The first flip- flop is used as a binary element for the divide-by-two function. The CP 1 input is used to obtain divide-by-three operation at the Q 1 and Q 2 outputs and divide-by-six operation at the Q 3 output. MODE SELECTION TABLE RESET INPUTS OUTPUTS MR1 MR2 CO C\\J H H L H H L L L L L L L Count Count Count H = HIGH Voltage Level L = LOW Voltage Level TRUTH TABLE COUNT OUTPUT Qo Q1 02 03

0 L L L L

1 H L L L

2 L H L L

3 H H L L

4 L L H L

5 H L H L

6 L L L H

7 H L L H

8 L H L H

9 H H L H

10 L L H H

11 H L H H

NOTE: Output Qo connected to CP1 LOGIC DIAGRAM Qo Q1 0 2 03

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS Min Max Min Max IlH Input HIGH Current, CPo 1.0 0.2 mA Vcc = Max, V in = 5.5 V IlH Input HIGH Current, CPi 1.0 0.4 mA Vcc = Max, V in = 5.5 V lee Power Supply Current 39 15 mA Vcc = Max AC CHARACTERISTICS: Vcc = 5.0 V, T a = 25°C (See Section 3 for waveforms and load configurations) SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONSCl = 15 pF Rl = 400 n Cl = 15 pF Min Max Min Max fmax Maximum Count Frequency, CPo Input 32 32 MHz Figs. 3-1, 3-9 fmax Maximum Count Frequency, CPi Input 16 16 MHz Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPo to Qo 18 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPo to Q3 50 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Qi 21 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Q 2 21 ns Figs. 3-1, 3-9 tPLH tPHL Propagation Delay CPi to Q 3 35 ns Figs. 3-1, 3-9 tPHL Propagation Delay, MR to Qn 40 40 ns Figs. 3-1, 3-17 AC OPERATING REQUIREMENTS: Vcc = 5.0 V, T a = 25°C SYMBOL PARAMETER 54/74 54/74LS UNITS CONDITIONS Min Max Min Max tw (H) CPo Pulse Width HIGH 15 15 ns Fig. 3-9 tw (H) CPi Pulse Width HIGH 30 30 ns tw (H) MR Pulse Width HIGH 15 15 ns Fig. 3-17 tree Recovery Time, MR to CP 25 25 ns