LM1101N5 CYSTEKEC | Alldatasheet

Document overview

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Technical content

Features

  • Ultra Fast Response in Line/Load Transient ●Ultra Low Output Noise Voltage 100μV(RMS)
  • Wide VIN Range from 2.5V to 5.5V ●Low Shutdown Current < 1μA
  • Adjustable Output Voltage from 0.8V to 4.5V ●Only 1μF Ceramic Capacitor required for stability
  • Ultra Low Dropout Voltage: 200mV @300mA ●Over Temperature Protection
  • High Power Supply Rejection Ratio ●Current Limit Protection ■70dB at 1kHz ●RoHS Compliant and 100% Lead (Pb)-Free ■60dB at 10kHz

Applications

  • Cellular Handsets ●Hand-Held Instruments
  • Battery-Powered Equipment ●PCMCIA Cards
  • Laptop, Palmtops, Notebook Computers ●Portable Information Applications

Ordering Information

Part Number Package Shipping LM1101N5 SOT-23-5L (RoHS compliant package) 3000 pcs / Tape & Reel Pin Configuration

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 2/10 LM1101N5 CYStek Product Specification Typical Application Circuit Pin Name Pin No. Pin Function EN 1 Chip Enable Input (Active high). GND 2 Ground. VIN 3 Input Voltage. This is the source input to the power device that supplies current to the output pin. VOUT 4 Output Voltage. VOUT is power output pin. An internal pull low resistance exists when the device is disabled. Minimum 1μF low ESR ceramic capacitor is required at this pin for stabilizing VOUT voltage. FB 5 Feedback Voltage. FB is the non-inverting input to the error amplifier. A resistor divider from the output to GND is used to set the regulation voltage as VOUT= 0.8 * (1+R1/R2 )(V) . This pin has high impedance and should be kept from non-inverting input to noisy source to guarantee stable operation. Pin Assignment Function Block Diagram

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 3/10 LM1101N5 CYStek Product Specification Absolute Maximum Ratings (Note 1)

  • ESD susceptibility (Note3) Recommended Operating Conditions (Note4) Electrical Characteristics @VIN=5V, TA=25 , unless otherwise specified℃ Parameter Symbol Test Conditions Min Typ Max Units Supply Input Section Power Input Voltage VIN VOUT= VREF 2.5 - 5.5 V POR Threshold VPORTH - 2.0 2.4 V POR Hysteresis VPORHYS - 0.1 - V Quiescent Current IQ VIN=VEN=5V, IOUT=0A - 90 130 μA Shutdown Current ISD VIN=5V,VEN=0V - 0.1 1 μA Output Voltage Output Voltage Accuracy VOUT VIN=VEN=5V, IOUT=1mA -1.5 - 1.5 % Line Regulation VOUT(LINE) 2.5V<VIN<5.0V, IOUT=1mA, VOUT=VREF - - 0.2 %/V Load Regulation VOUT(LOAD) 1mA<IOUT<300mA,VIN=VOUT+0.5V - 0.5 1 %/A Output Voltage Noise 10Hz to 100kHz, COUT=1μF - 100 - μV(RMS) IOUT=10mA,1kHz - 70 - IOUT=10mA,10kHz - 60 - Power Supply Rejection Ratio PSRR IOUT=10mA,100kHz - 40 - dB Dropout Voltage VDROP IOUT=300mA, 2.5V < VOUT < 3.3V - 200 300 mV Enable Enable High Level VEN 1.4 - - V Disable Low Level VSD - - 0.4 V Enable Input Current IEN VEN=5V or 0V -1 0 1 μA Output Voltage Ramp Up Time - 600 - μs

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 4/10 LM1101N5 CYStek Product Specification Parameter Symbol Test Conditions Min Typ Max Units Over Current Protection OCP Threshold Level IOCP VIN=VEN=5V, VOUT=VREF 360 600 - mA Thermal Protection Thermal Shutdown Temperature TSD VIN=VEN=5V, IOUT=0A, VOUT=VREF - 160 - °C Thermal Shutdown Hysteresis TSDHYS VIN=VEN=5V, IOUT=0A, VOUT=VREF - 30 - Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA=25°C on a low effective thermal conductivity test board (single layout, 1S) of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 5/10 LM1101N5 CYStek Product Specification Typical Operating Characteristics Power On from VIN Power Off from VIN VOUT=3.3V，CIN=COUT=1μF，ROUT=15Ω VOUT=3.3V，CIN=COUT=1μF，ROUT=15Ω Turn On from EN Turn Off from EN VOUT=3.3V，CIN=COUT=1μF，ROUT=15Ω VOUT=3.3V，CIN=COUT=1μF，ROUT=15Ω Load Transient Response Line Transient Response VOUT=3.3V，CIN=COUT=1μF VOUT=2.5V，CIN=COUT=1μF，VIN=3.5V to 4.5V VIN VOUT VIN VOUT IOUT IOUT VIN VOUT IOUT VIN VOUT IOUT

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 6/10 LM1101N5 CYStek Product Specification

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 7/10 LM1101N5 CYStek Product Specification

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 8/10 LM1101N5 CYStek Product Specification Functional Description Enable Function LM1101 is enabled if the voltage of the EN pin is greater than 1.4V. If the voltage of the EN pin is less than 0.4V, the IC will be disabled. POR – Power ON Reset To let LM1101 start to operation, input voltage must be higher than its POR voltage even when EN voltage is pulled higher than enable high voltage. Typical POR voltage is 2.0V. VOUT Voltage Adjustment The VOUT voltage of LM1101 can be adjusted by external voltage divider. Refer to typical application circuit, VOUT voltage is calculated by the following equation: Over Current Limit Function LM1101 features over current limiting function which can limit its output current to 600mA. Input and Output Capacitor Selection For VIN pin, 1μF or larger ceramic capacitor is required to provide bypass path in transient current demand. VOUT pin is also recommended to have 1μF or larger ceramic capacitor to be stable and reduce the VOUT voltage dip when fast loading transient is happened. Power Dissipation The max power depends on some conditions, including of thermal impedance, PCB layout, airflow, and so on. The max power dissipation can be calculated by the formula as below: PD(max)=(TJ(max)-TA) / θJA TJ(max) is the max junction temperature; θJA is the thermal impedance from junction to ambient. The thermal impedance θJA of SOT23-5 is package design and PCB design dependent. For recommended specification of LM1101, the max junction temperature is 125 degree C. The θJA of SOT23-5 is 250°C/W on the standard JEDEC 51-3 thermal test board. The max power dissipation (at 25°C ambient) can be calculated as below: PD (max at 25°C)=(125°C – 25°C) / (250°C/W) = 0.4W

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 9/10 LM1101N5 CYStek Product Specification Recommended wave soldering condition Soldering Time Product Peak Temperature Pb-free devices 5 +1/-1 seconds 260 +0/-5 °C Recommended temperature profile for IR reflow Pb-free Assembly Profile feature Sn-Pb eutectic Assembly Average ramp-up rate 3°C/second max. 3°C/second max. (Tsmax to Tp) Preheat 100°C 150°C −Temperature Min(TS min) −Temperature Max(TS max) 150°C 200°C −Time(ts min to ts max) 60-120 seconds 60-180 seconds 183°C 60-150 seconds Time maintained above: −Temperature (TL) − Time (tL) 217°C 60-150 seconds Peak Temperature(TP) 240 +0/-5 °C 260 +0/-5 °C Time within 5°C of actual peak temperature(tp) 10-30 seconds 20-40 seconds Ramp down rate 6°C/second max. 6°C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface.

CYStech Electronics Corp. Spec. No. : C552N5 Issued Date : 2010.10.26 Revised Date : Page No. : 10/10 LM1101N5 CYStek Product Specification SOT-25 Dimension Style: Pin 1: Enable Pin 2: Ground Pin 3: V IN Pin 4: VOUT Pin 5: Feedback Marking: 5-Lead SOT-23-5L Plastic Surface Mounted Package CYStek Package Code:N5 Device Code Date Code *:Typical B1 1.60* 0.0630* F - 1.45 - 0.0571 Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material :

  • Lead :Pure tin plated.
  • Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0. Important Notice:
  • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
  • CYStek reserves the right to make changes to its products without notice.
  • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
  • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.