LH7A400 SHARP | Alldatasheet
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Preliminary Data Sheet 12/8/03 1 LH7A400 Preliminary Data Sheet 32-Bit System-on-Chip
FEATURES
- ARM922T™ Core: – 32-bit ARM9TDMI™ RISC Core – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE Enabled) High Performance (200 MHz) 80KB On-Chip Memory External Bus Interface – 100 MHz – Asynchronous SRAM/ROM/Flash – Synchronous DRAM/Flash – PCMCIA – CompactFlash Clock and Power Management – 32.768 kHz and 14.7456 MHz Oscillators – Programmable PLL Low Power Modes – Run (147 mA), Halt (41 mA), Standby (42 µA) Programmable LCD Controller – Up to 1,024 × 768 Resolution – Supports STN, Color STN, AD-TFT, HR-TFT, TFT – Up to 64,000 Colors and 15 Gray Shades DMA (10 Channels) –A C 9 7 –M M C –U S B USB Device Interface (USB 1.1) Synchronous Serial Port (SSP) – Motorola SPI™ – Texas Instruments SSI – National MICROWIRE™ Three Programmable Timers Three UARTs – Classic IrDA (115 kbit/s) Smart Card Interface (ISO7816) DC-to-DC Converters MultiMediaCard™ Interface AC97 Codec Interface Smart Battery Monitor Interface Real Time Clock (RTC) Up to 60 General Purpose I/Os Programmable Interrupt Controller Watchdog Timer JTAG Debug Interface and Boundary Scan Operating Voltage – 1.8 V Core – 3.3 V Input/Output (1.8 V I/O Optional 5 V Tolerant Inputs (except oscillator pins2) Operating Temperature – 0°C to +70°C Commercial – -40°C to +85°C Industrial (With Clock Frequency Reduction 256-Ball PBGA or 256-Ball CABGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com- plete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall sys- tem costs, reduces development cycle time and accel- erates product introduction. Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. Windows CE is a trademark of Microsoft Corporation. NOTES: 1. Under development. Results pending further characterization. 2. Oscillator pins R13, T13, P15, and P16 are 1.8 V ±10%
Figure 1. LH7A400 Block Diagram
Table 1. Functional Pin List
to XTAL32IN leaving XTAL32OUT open. Table 1. Functional Pin List (Cont’d)
edge triggered and are internally debounced. or edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced.
CompactFlash) in single or dual card mode. Card for decoding low and high byte accesses. CompactFlash) in single or dual card mode. Card for decoding low and high byte accesses. CompactFlash) in single or dual card mode. nals to the appropriate PC Card.
NOTES: *Signals beginning with ‘n’ are Active LOW. mode, leave open. For JTAG mode, tie to GND. and JTAG mode, leave open. See Table 2. Table 2. nTest Pin Function
- The Intensity bit is identically generated for all three colors.
Table 3. LCD Data Multiplexing
Table 4. 256-Ball PBGA Package Numerical Pin List
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d)
prior to entering the Standby state.
Table 5. 256-Ball CABGA Package Numerical Pin List
current power saving mode selected. the only clock in the LH7A400 that runs permanently. is used in the Real Time Clock counter. 48 MHz for the USB peripheral. Figure 2. Application Diagram
operates in all three modes. after which software can then take appropriate actions. high-performance, high clock frequency system modules. buffers and bus holders, and simplifies bus arbitration. Figure 3. Clock and State Controller Block Diagram
14.7456 MHz
wide, high speed gateway to external memory devices. given to the Synchronous Memory Controller interface. the LCD bus is given priority. The LH7A400 system has a 32-bit-wide address bus. these eight banks are designed for PCMCIA systems. AHB and APB. The rest is unused. (nSCS0) is mapped into memory location zero. system for the two boot modes. set the interrupt vector table. the priority must be resolved in software. bits are cleared, therefore masking all interrupts. software after a power-on-reset. Table 6. Boot Modes
sion buffer in Synchronous Memory for large displays. and the embedded SRAM frame buffer. existing access has been completed. See Figure 5. bits per pixel, equivalent to 70KB of information. Half-Word and Word accesses are permissible. external (off-chip) memory devices. endian or big-endian operation. fast-boot block flash memory. Figure 4. Memory Mapping for Each Boot Mode
1000.0000 ASYNCHRONOUS MEMORY (nCS1)
Figure 5. External Bus Interface Block Diagram
LH7A400 32-Bit System-on-Chip 30 12/8/03 Preliminary Data Sheet The Asynchronous Memory Controller has six main functions: Memory bank select Access sequencing Wait states generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing. Synchronous Memory Controller The Synchronous memory controller provides a high speed memory interface to a wide variety of Synchro- nous memory devices, including SDRAM, Synchro- nous Flash and Synchronous ROMs. The key features of the controller are: LCD DMA port for high bandwidth Up to four Synchronous Memory banks that can be independently set up Special configuration bits for Synchronous ROM operation Ability to program Synchronous Flash devices using write and erase commands On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset Data is transferred between the controller and the SDRAM in quad-word bursts. Longer transfers within the same page are concatenated, forming a seam- less burst Programmable for 16- or 32-bit data bus size Two reset domains are provided to enable SDRAM contents to be preserved over a ‘soft’ reset Power saving Synchronous Memory SCKE and external clock modes provided. MultiMediaCard (MMC) The MMC adapter combines all of the requirements and functions of an MMC host. The adapter supports the full MMC bus protocol, defined by the MMC Defini- tion Group’s specification v.2.11. The controller can also implement the SPI interface to the cards. INTERFACE DESCRIPTION AND MMC OVERVIEW The MMC controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the MMC card, and to configure and acquire status information from the card’s registers. MMC bus lines can be divided into three groups: Power supply: VDD and VSS Data Transfer: MMCCMD, MMCDATA Clock: MMCLK. MULTIMEDIACARD ADAPTER The MultiMediaCard Adapter implements MultiMedia- Card specific functions, serves as the bus master for the MultiMediacard Bus and implements the standard inter- face to the MultiMediaCard Cards (card initialization, CRC generation and validation, command/response transactions, etc.). Smart Card Interface (SCI) The SCI (ISO7816) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES Supports asynchronous T0 and T1 transmission protocols Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported Eight-character-deep buffered Tx and Rx paths Direct interrupts for Tx and Rx FIFO level monitoring Interrupt status register Hardware-initiated card deactivation sequence on detection of card removal Software-initiated card deactivation sequence on transaction complete Limited support for synchronous Smart Cards via registered input/output. PROGRAMMABLE PARAMETERS Smart Card clock frequency Communication baud rate Protocol convention Card activation/deactivation time Check for maximum time for first character of Answer to Reset - ATR reception Check for maximum duration of ATR character stream Check for maximum time of receipt of first character of data stream Check for maximum time allowed between characters Character guard time Block guard time Transmit/receive character retry.
32-Bit System-on-Chip LH7A400 Preliminary Data Sheet 12/8/03 31 Direct Memory Access Controller (DMA) The DMA Controller interfaces streams from the fol- lowing three peripherals to the system memory: USB (1 Tx and 1 Rx DMA Channel) MMC (1 Tx and 1 Rx DMA Channel) AC97 (3 Tx and 3 Rx DMA Channels). Each has its own bi-directional peripheral DMA bus capable of transferring data in both directions simulta- neously. All memory transfers take place via the main system AHB bus. DMA Specific features are: Independent DMA channels for Tx and Rx Two Buffer Descriptors per channel to avoid poten- tial data under/over-flows due to software introduced latency No Buffer wrapping Buffer size may be equal to, greater than or less than the packet size. Transfers can automatically switch between buffers. Maskable interrupt generation Internal arbitration between DMA Channels and external bus arbiter. For DMA Data transfer sizes, byte, word and quad- word data transfers are supported. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. A system interrupt is gen- erated when any or all of the DMA channels wish to inform the processor that a new buffer needs to be allo- cated. The DMA controller services three peripherals using ten DMA channels, each with its own peripheral DMA bus capable of transferring data in both directions simultaneously. The MMC and USB peripherals each use two DMA channels, one for transmit and one for receive. The AC97 peripheral uses six DMA channels (three trans- mit and three receive) to allow different sample fre- quency data queues to be handled with low software overheads. The DMA Controller does not support memory to memory transfers. USB Device The features of the USB are: Fully compliant to USB 1.1 specification Provides a high level interface that shields the firm- ware from USB protocol details Compatible with both OpenHCI and Intel’s UHCI standards Supports full-speed (12 Mbps) functions Supports Suspend and Resume signalling. Color LCD Controller The LH7A400’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400’s LCD Controller incorporates the timing con- version logic from TFT to HR-TFT, allowing a direct interface to HR-TFT and minimizing external chip count. The Color LCD Controller features support for: Up to 1,024 × 768 Resolution 16-bit Video Bus STN, Color STN, AD-TFT, HR-TFT, TFT panels Single and Dual Scan STN panels Up to 15 Gray Shades Up to 64,000 Colors AC97 Advanced Audio Codec Interface The AC97 Advanced Audi o Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 LINK is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the Audio Codec and an interface to the AMBA APB. Its main features include: Serial-to-parallel conversion for data received from the external codec Parallel-to-serial conversion for data transmitted to the external codec Reception/Transmission of control and status infor- mation via the AMBA APB interface Supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored indepen- dently in both transmit and receive modes. The out- going data for the FIFOs can be written via either the APB interface or with DMA channels 1 - 3.
LH7A400 32-Bit System-on-Chip 32 12/8/03 Preliminary Data Sheet Audio Codec Interface (ACI) The ACI provides: A digital serial interface to an off-chip 8-bit CODEC All the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the CODEC device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchroniza- tion output signal that is synchronous with the bit clock. Synchronous Serial Port (SSP) The LH7A400 SSP is a master-only interface for synchronous serial communication with device periph- eral devices that has either Motorola SPI, National Semiconductor MICROWIRE or Texas Instruments Synchronous Serial Interfaces. The LH7A400 SSP performs serial-to-parallel con- version on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A400 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usu- ally be determined by peripheral devices. UART/IrDA The LH7A400 contains three UARTs, UART1, UART2, and UART3. The UART performs: Serial-to-Parallel conversion on data received from the peripheral device Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths are buffered with inter- nal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: Four individually maskable interrupts from the receive, transmit and modem status logic blocks A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is pre- vented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Timers Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be decremented on the next active clock edge to arrive after the write. When the timer underflows, it will immediately assert its appropriate interrupt. The timers can be read at any time. The clock source and mode is selectable by writing to various bits in the system control register. Clock sources are 508 kHz and 2 kHz. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. It has the same register arrangement as Timer 1 and Timer 2, pro- viding a load, value, control and clear register. Once the timer has been enabled and is written to, unlike the Timer 1 and Timer 2, will decrement the timer on the next rising edge of the 7.3728 MHz clock after the data register has been updated. All the timers can operate in two modes, free running mode or pre-scale mode. FREE-RUNNING MODE In free-running mode, the timer will wrap around to 0xFFFF when it underflows and continue counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a pro- grammable frequency to drive the buzzer or generate a periodic interrupt.
32-Bit System-on-Chip LH7A400 Preliminary Data Sheet 12/8/03 33 Real Time Clock (RTC) The RTC can be used to provide a basic alarm func- tion or long time-base counter. This is achieved by gen- erating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC. Battery Monitor Interface (BMI) The LH7A400 BMI is a serial communication inter- face specified for two types of Battery Monitors/Gas Gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. A brief overview of these two interface types are given here. SINGLE WIRE INTERFACE The Single Wire Interface performs: Serial-to-parallel conversion on data received from the peripheral device Parallel-to-serial conversion on data transmitted to the peripheral device Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a WriteData/Command word to the Battery Monitor. This word will always contain the Command section, which tells the Single Wire Interface device the location for the current transaction. The most signifi- cant bit of the Command determines if the transaction is Read or Write. In the case of a Write transaction, then the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The SMBus Interface performs: Serial-to-Parallel conversion on data received from the peripheral device Parallel-to-Serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multi- master bus (the SMBus), meaning that more than one device capable of controlling the bus can be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data pro- vided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus. DC-to-DC Converter The features of the DC-DC Converter interface are: Dual drive PWM outputs, with independent closed loop feedback Software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. Output polarity (for positive or negative voltage gen- eration) is hardware-configured during power-on reset via the polarity select inputs Each PWM output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The WDT features are: Driven by the system clock 16 programmable time-out periods: 2 16 through 231 clock cycles Generates a system reset (resets LH7A400) or a FIQ Interrupt whenever a time-out period is reached Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes Protection mechanism guards against interrupt-service-failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset. General Purpose I/O (GPIO) The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and GPI- OFEOI registers are used to control edge-triggered Interrupts on Port F. The PINMUX register controls what signals are output of Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and H.
LH7A400 32-Bit System-on-Chip 34 12/8/03 Preliminary Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operat ing Conditions NOTES: 1. Core Voltage should never exceed I/O Voltage. 2. USB is not functional below 3.0 V. 3. Using 14.756 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal. 4. VDDC = 1.62 V to 1.98 V. 5. VDD = 3.0 V to 3.6 V. PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) -0.3 V 2.4 V DC I/O Supply Voltage (VDD) -0.3 V 4.6 V DC Analog Supply Voltage (VDDA) -0.3 V 2.4 V Storage Temperature -55°C 125°C PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.62 V 1.8 V 1.98 V 1 DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 2 DC Analog Supply Voltage for PLLs (VDDA) 1.62 V 1.8 V 1.98 V Clock Frequency (Commercial) 10 MHz 200 MHz 3, 4, 5 Clock Frequency (Industrial) 10 MHz 195 MHz 3, 4, 5 Operating Temperature (Commercial) 0°C 25°C 70°C Operating Temperature (Industrial) -40°C 25°C +85°C
32-Bit System-on-Chip LH7A400 Preliminary Data Sheet 12/8/03 35 DC/AC SPECIFICATIONS (COMMERCIAL AND INDUSTRIAL) Unless otherwise noted, all data provided under commercial DC/AC specifications are based on -40°C to +85°C, VDDC = 1.62 V to 1.98 V, VDD = 3.0 V to 3.6 V, VDDA = 1.62 V to 1.98 V. DC Specifications NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized. AC Test Conditions SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS NOTES VIH CMOS and Schmitt Trigger Input HIGH Voltage 2.0 V VIL CMOS and Schmitt Tri gger Input LOW Voltage 0.8 V VHST Schmitt Trigger Hysteresis 0.25 V VIL to VIH VOH CMOS Output HIGH Voltage, Output Drive 1 2.6 V IOH = -2 mA Output Drive 2 2.6 V IOH = -4 mA Output Drive 3 2.6 V IOH = -8 mA Output Drive 4 and 5 2.6 V IOH = -12 mA 1 VOL CMOS Output LOW Voltage, Output Drive 1 0.4 V IOL = 2 mA Output Drive 2 0.4 V IOL = 4 mA Output Drive 3 0.4 V IOL = 8 mA Output Drive 4 0.4 V IOL = 12 mA Output Drive 5 0.4 V IOL = 20 mA 1 IIN Input Leakage Current -10 10 µA VIN = VDD or GND IOZ Output Tri-state Leakage Current -10 10 µA VOUT = VDD or GND ISTARTUP Startup Current 50 µA2 CIN Input Capacitance 4 pF COUT Output Capacitance 4 pF PARAMETER RATING UNIT DC I/O Supply Voltage (VDD) 3.0 to 3.6 V DC Core Supply Voltage (VDDC) 1.62 to 1.98 V Input Pulse Levels VSS to 3 V Input Rise and Fall Times 2 ns Input and Output Timing Reference Levels VDD/2 V
Maximum specified ambient temperature. current is supplied by the 1.8 V power supply. Table 7. Current Consumption by Mode Table 8. Peripheral Current Consumption
Table 9. AC Signal Characteristics
- ‘nC’ in the MIN./MAX. columns indicates the number of system clock (HCLK) periods after valid address.
- For Output Drive strength specifications, refer to Table 1.
Table 9. AC Signal Characteristics (Cont’d)
Figure 12. PCMCIA Write Transfer
- Precharge time, access time, and hold
time are programmable wait-state times.
Figure 22. 14.7456 MHz External Oscillator Components and Schematic
- Y1 is a parallel-resonant type crystal. (See table)
- The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
- The values for C1 and C2 are dependent upon
- R1 must be in the circuit.
- Ground connections should be short and return
processor's core ground pins.
- Tolerance for R1, C1, C2 is ≤ 5%.
14.7456 MHz Crystal
supply analog power to the PLLs. capacitor near each VDDx, VSSx pair on the chip. quickly transition through the entire input voltage range. through the series resistor to the board power supply. capacitor must be kept as short as possible. high frequency cap as short as possible. nally, to tie the signal to its inactive state. not require external conditioning. larly applies to the address and data buses. and proximity to ground and power planes. ground return paths also increase. ground, but only to the filter components. Figure 23. VDDA, VSSA Filter Circuit
Figure 24. 256-Ball PBGA Package Specification
0.50 R, 3 PLACES
4 PLACES
Figure 25. 256-Ball CABGA Package Specification
LH7A400 32-Bit System-on-Chip 52 12/8/03 Preliminary Data Sheet
ORDERING INFORMATION
NOTE: *Requires Factory Approval. CONTENT REVISIONS This document contains the following changes to content, causing it to differ from previous versions. Table 11. Ordering Information Table 12. Record of Revisions
1 Features 256-ball CABGA package added
12 Table 3 Signal ordering corrected
39 Figure 7 and Figure 8 ‘CSx’ added to figures
44 Table 10 and
49 Figure 23 Figure added for CABGA package
2 Figure 1 Updated to show ALI Interface
Operating Conditions’Broke out “Commercial” and “Industrial” speed ranges. 37-38 Table 9 Minor corrections to type. 39 Table 9 Added ACI timing. 49 Figure 24 PBGA package drawing added.
51 Table 11 Added ordering information
32-Bit System-on-Chip LH7A400 ©2003 by SHARP Corporation Reference Code SMA01012 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3
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