LH75400 SHARP | Alldatasheet
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Preliminary Data Sheet 6/4/03 1 LH75400/01/10/11 Preliminary Data Sheet System-on-Chip
DESCRIPTION
The SHARP BlueStreak LH75400/01/10/11 family consists of four low-cost 16/32-bit System-on-Chip (SoC) devices.
- LH75401 — contains the superset of features. LH75411 — similar to LH75401, without CAN 2.0B. LH75400 — similar to LH75401, but with a Gray- scale LCDC only. LH75410 — similar to LH75400, without CAN 2.0B. COMMON FEATURES Highly Integrated System-on-Chip ARM7TDMI-S™ Core High Performance (70 MHz CPU Speed) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz 32KB On-chip SRAM – 16KB Tightly Coupled Memory (TCM) SRAM – 16KB Internal SRAM Clock and Power Management – Low Power Modes: Standby, Sleep, Stop Eight Channel, 10-bit Analog-to-Digital Converter Integrated Touch Screen Controller Serial interfaces – Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of 14.756 MHz). – One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of 70 MHz). Synchronous Serial Port – Motorola SPI™ – National Semiconductor Microwire™ – Texas Instruments SSI Real-Time Clock (RTC) Three Counter/Timers – Capture/Compare/PWM Compatibility – Watchdog Timer (WDT) Low-Voltage Detector JTAG Debug Interface and Boundary Scan Single 3.3 V Supply 5 V Tolerant Inputs 144-pin LQFP Package - 4 0°C to +85°C Operating Temperature Unique Features of the LH75401 Color and Grayscale Liquid Crystal Display (LCD) Controller – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palletized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. CAN Controller that supports CAN version 2.0B. Unique Features of the LH75411 Color and Grayscale LCD Controller (LCDC) – 12-bit (4,096) Direct Mode Color, up to VGA – 8-bit (256) Direct or Palletized Color, up to SVGA – 4-bit (16) Direct Mode Color/Grayscale, up to XGA – 12-bit Video Bus – Supports STN, TFT, HR-TFT, and AD-TFT Displays. Unique Features of the LH75400 Grayscale LCDC – 4-bit (16 Level) Grayscale, up to XGA – 8-bit Video Bus – Supports STN Displays. Controller Area Network (CAN) Controller that sup- ports CAN version 2.0B. Unique Features of the LH75410 Grayscale LCDC – 4-bit (16 Level) Grayscale, up to XGA – 8-bit Video Bus – Supports STN Displays. NOTES: ARM7 Thumb, and ARM7TDMI-S are trademarks of ARM LTD. Motorola SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. VGA and XGA modes require 66 MHz CPU speed.
Figure 1. LH75401 Block Diagram
4 CHANNEL
8 CHANNEL
Figure 2. LH75411 Block Diagram
Figure 3. LH75400 Block Diagram
Figure 4. LH75410 Block Diagram
Figure 5. LH75401 Pin Diagram
Table 1. LH75401 Numerical Pin List
1 PA7 D15 I/O 8 mA Bidirectional 1
2 PA6 D14 I/O 8 mA Bidirectional 1
3 VDD Power None
4 PA5 D13 I/O 8 mA Bidirectional 1
5 PA4 D12 I/O 8 mA Bidirectional 1
6 PA3 D11 I/O 8 mA Bidirectional 1
7 PA2 D10 I/O 8 mA Bidirectional 1
8 VSS Ground None
9 PA1 D9 I/O 8 mA Bidirectional 1
10 PA0 D8 I/O 8 mA Bidirectional 1
11 VDDC Power None
12 D7 I/O 8 mA Bidirectional
13 D6 I/O 8 mA Bidirectional
14 VSSC Ground None
15 D5 I/O 8 mA Bidirectional
16 D4 I/O 8 mA Bidirectional
17 VDD Power None
18 D3 I/O 8 mA Bidirectional
19 D2 I/O 8 mA Bidirectional
20 D1 I/O 8 mA Bidirectional
21 D0 I/O 8 mA Bidirectional
24 PB5 nWAIT 8 mA Bidirectional Pull-up 1, 3
25 PB4 nBLE1 8 mA Bidirectional Pull-up 1, 3
26 VSS Ground None
27 PB3 nBLE0 8 mA Bidirectional Pull-up 1, 3
28 PB2 nCS3 8 mA Bidirectional Pull-up 1, 3
29 PB1 nCS2 8 mA Bidirectional Pull-up 1, 3
30 PB0 nCS1 8 mA Bidirectional Pull-up 1, 3
32 PC7 A23 8 mA Bidirectional Pull-down 1
33 PC6 A22 8 mA Bidirectional Pull-down 1
34 VDD Power None
35 PC5 A21 8 mA Bidirectional Pull-down 1
36 PC4 A20 8 mA Bidirectional Pull-down 1
37 PC3 A19 8 mA Bidirectional Pull-down 1
38 PC2 A18 8 mA Bidirectional Pull-down 1
39 PC1 A17 8 mA Bidirectional Pull-down 1
40 PC0 A16 8 mA Bidirectional Pull-down 1
41 VSS Ground None
42 VDD Power None
43 A15 8 mA Output
44 A14 8 mA Output
45 A13 8 mA Output
46 A12 8 mA Output
47 A11 8 mA Output
48 VSS Ground None
49 A10 8 mA Output
50 A9 8 mA Output
51 A8 8 mA Output
52 A7 8 mA Output
53 A6 8 mA Output
54 VDD Power None
55 A5 8 mA Output
56 A4 8 mA Output
57 A3 8 mA Output
58 A2 8 mA Output
59 VSS Ground None
60 A1 8 mA Output
61 A0 8 mA Output
63 TEST2 None Input Pull-up 2
64 TEST1 None Input Pull-up 2
65 TMS None Input Pull-up 2
66 RTCK 4 mA Output
67 TCK None Input
68 TDI None Input Pull-up 2
69 TDO 4 mA Output
70 LINREGEN None Input
72 PD6 INT6 DREQ 6 mA Bidirectional Pull-down 1
73 PD5 INT5 DACK 6 mA Bidirectional 1, 2
74 PD4 INT4 UARTRX1 8 mA Bidirectional Pull-up 1
75 VDDC Power None
76 PD3 INT3 UARTTX1 8 mA Bidirectional Pull-up 1
77 PD2 INT2 2 mA Bidirectional Pull-up 1
78 PD1 INT1 6 mA Bidirectional 1, 2
79 PD0 INT0 2 mA Bidirectional 1
80 VSSC Ground None
82 XTAL32IN None Output
Table 1. LH75401 Numerical Pin List (Cont’d)
83 XTAL32OUT None Output
84 VSSA_PLL Ground None
85 VDDA_PLL Power None
86 XTALIN None Input
87 XTALOUT None Output
88 VSSA_ADC Ground None
89 AN3 (LR/Y-) PJ7 None Input
90 AN4 (Wiper) PJ6 None Input
91 AN9 PJ5 None Input
92 AN2 (LL/Y+) PJ4 None Input
93 AN8 PJ3 None Input
94 AN1 (UR/X-) PJ2 None Input
95 AN6 PJ1 None Input
96 AN0 (UL/X+) PJ0 None Input
97 VDDA_ADC Power None
98 VDD Power None
99 PE7 SSPFRM 4 mA Bidirectional Pull-up 1
100 PE6 SSPCLK 4 mA Bidirectional Pull-down 1
101 PE5 SSPRX 4 mA Bidirectional Pull-up 1
102 PE4 SSPTX 4 mA Bidirectional Pull-down 1
103 PE3 CANTX UARTTX0 8 mA Bidirectional Pull-up 1
104 PE2 CANRX UARTRX0 2 mA Bidirectional Pull-up 1
105 PE1 UARTTX2 4 mA Bidirectional Pull-up 1
106 VSS Ground None
107 PE0 UARTRX2 4 mA Bidirectional Pull-up 1
108 PF6 CTCAP2B CTCMP2B 4 mA Bidirectional 2
109 PF5 CTCAP2A CTCMP2A 4 mA Bidirectional
110 PF4 CTCAP1B CACMP1B 4 mA Bidirectional 2
111 PF3 CTCAP1A CTCMP1A 4 mA Bidirectional
112 VDD Power None
113 PF2 CTCAP0E 4 mA Bidirectional 2
114 PF1 CTCAP0D 4 mA Bidirectional
115 PF0 CTCAP0C 4 mA Bidirectional 2
116 PG7 CTCAP0B CTCMP0B 4 mA Bidirectional
117 PG6 CTCAP0A CTCMP0A 4 mA Bidirectional 2
118 PG5 CTCLK 4 mA Bidirectional
119 VSS Ground None
120 PG4 LCDVEEEN LCDMOD 8 mA Bidirectional
121 PG3 LCDVDDEN 8 mA Bidirectional
122 PG2 LCDDSPLEN LCDREV 8 mA Bidirectional
123 PG1 LCDCLS 8 mA Bidirectional
124 PG0 LCDPS 8 mA Bidirectional
- Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.
- CMOS Schmitt trigger input.
- Signals preceded with ‘n’ are active LOW.
125 PH7 LCDDCLK 8 mA Bidirectional
126 VDD Power None
127 VSS Ground None
128 PH6 LCDLP LCDHRLP 8 mA Bidirectional
129 PH5 LCDFP LCDSPS 8 mA Bidirectional
130 PH4 LCDEN LCDSPL 8 mA Bidirectional
131 PH3 LCDVD11 8 mA Bidirectional
132 PH2 LCDVD10 8 mA Bidirectional
133 PH1 LCDVD9 8 mA Bidirectional
134 VDD Power None
135 PH0 LCDVD8 8 mA Bidirectional
136 PI7 LCDVD7 8 mA Bidirectional
137 PI6 LCDVD6 8 mA Bidirectional
138 PI5 LCDVD5 8 mA Bidirectional
139 PI4 LCDVD4 8 mA Bidirectional
140 VSS Ground None
141 PI3 LCDVD3 8 mA Bidirectional
142 PI2 LCDVD2 8 mA Bidirectional
143 PI1 LCDVD1 8 mA Bidirectional
144 PI0 LCDVD0 8 mA Bidirectional
Table 2. LH75401 Signal Descriptions
72 DREQ Input DMA Request 1
73 DACK Output DMA Acknowledge 1
120 LCDMOD Output HR-TFT Signal Used by the Row Driver (HR-TFT only) 1
120 LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) 1
121 LCDVDDEN Output Digital Supply Enable 1
122 LCDDSPLEN Output LCD Panel Power Enable 1
122 LCDREV Output HR-TFT Reverse Signal (HR-TFT only) 1
123 LCDCLS Output HR-TFT Clock to the Row Drivers (HR-TFT only) 1
124 LCDPS Output HT-TFT Power Save (HR-TFT only) 1
125 LCDDCLK Output LCD Panel Clock 1
128 LCDLP Output Line Synchronization Pulse (STN ), Horizontal Synchronization Pulse (TFT) 1
128 LCDHRLP Output HR-TFT Latch Pulse (HR-TFT only) 1
129 LCDFP Output Frame Pulse (STN), Ve rtical Synchronization Pulse (TFT) 1
129 LCDSPS Output HR-TFT Signal that Resets the Row Driver Counter (HR-TFT only) 1
130 LCDEN Output LCD Data Enable 1
130 LCDSPL Output HR-TFT Start Pulse Left (HR-TFT only) 1
99 SSPFRM Input SSP Serial Frame 1
100 SSPCLK Input SSP Clock 1
101 SSPRX Input SSP RXD 1
102 SSPTX Output SSP TXD 1
103 UARTTX0 Output UART0 Transmitted Serial Data Output 1
104 UARTRX0 Input UART0 Received Serial Data Input 1
74 UARTRX1 Input UART1 Received Serial Data Input 1
76 UARTTX1 Output UART1 Transmitted Serial Data Output 1
105 UARTTX2 Output UART2 Transmitted Serial Data Output 1
107 UARTRX2 Input UART2 Received Serial Data Input 1
103 CANTX Output CAN Transmitted Serial Data Output 1
104 CANRX Input CAN Received Serial Data Input 1
Table 2. LH75401 Signal Descriptions (Cont’d)
116 CTCMP0[A:B] Output Timer 0 Compare Outputs 1
118 CTCLK Input Common External Clock 1
110 CTCAP1[A:B] Input Timer 1 Capture Inputs 1
110 CTCMP1[A:B] Output Timer 1 Compare Outputs 1
108 CTCAP2[A:B] Input Timer 2 Capture Inputs 1
108 CTCMP2[A:B] Input Timer 2 Compare Outputs 1
72 INT6 Input External Interrupt Input 6 1
- These pin numbers have multiplexed functions.
- Signals preceded with ‘n’ are active LOW.
73 INT5 Input External Interrupt Input 5 1
74 INT4 Input External Interrupt Input 4 1
76 INT3 Input External Interrupt Input 3 1
77 INT2 Input External Interrupt Input 2 1
78 INT1 Input External Interrupt Input 1 1
79 INT0 Input External Interrupt Input 0 1
86 XTALIN Input Crystal Clock Input
87 XTALOUT Output Crystal Clock Output
63 TEST2 Input Test Mode Pin 2
64 TEST1 Input Test Mode Pin 1
65 TMS Input JTAG Test Mode Select Input
66 RTCK Output Returned JTAG Test Clock Output
67 TCK Input JTAG Test Clock Input
68 TDI Input JTAG Test Serial Data Input
69 TDO Output JTAG Test Data Serial Output
75 VDDC Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input)
80 VSSC Power Core VSS
70 LINREGEN Input Linear Regulator Enable
84 VSSA_PLL Power PLL Analog VSS
85 VDDA_PLL Power PLL Analog VDD Supply
88 VSSA_ADC Power A-to-D converter Analog VSS
97 VDDA_ADC Power A-to-D converter Analog VDD Supply
Figure 6. LH75411 Pin Diagram
Table 3. LH75411 Numerical Pin List
Table 3. LH75411 Numerical Pin List (Cont’d)
103 PE3 UARTTX0 8 mA Bidirectional Pull-up 1
104 PE2 UARTRX0 2 mA Bidirectional Pull-up 1
- Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.
- CMOS Schmitt trigger input.
- Signals preceded with ‘n’ are active LOW.
Table 4. LH75411 Signal Descriptions
124 LCDPS Output HR-TFT Power Save (HR-TFT only) 1
Table 4. LH75411 Signal Descriptions (Cont’d)
- These pin numbers have multiplexed functions.
- Signals preceded with ‘n’ are active LOW.
LH75400/01/10/11 System-on-Chip 26 6/4/03 Preliminary Data Sheet THE LH75400 Figure 7.LH75400 Pin Diagram PH7/LCDDCLK VDD VSS PH6/LCDLP PH5/LCDFP PH4/LCDEN PH3/LCDVD11 PH2/LCDVD10 PH1/LCDVD9 VDD PH0/LCDVD8 PI7/LCDVD7 PI6/LCDVD6 PI5/LCDVD5 PI4/LCDVD4 VSS PI3/LCDVD3 PI2/LCDVD2 PI1/LCDVD1 PI0/LCDVD0 VDD A10 VSS A11 A12 A13 A14 A15 VDD VSS PC0/A16 PC1/A17 PC2/A18 PC3/A19 PA7/D15 PA6/D14 VDD PA5/D13 PA4/D12 PA3/D11 PA2/D10 VSS PA1/D9 PA0/D8 VDDC VSSC VDD nWE nOE PB5/nWAIT PB4/nBLE1 VSS PB3/nBLE0 PB2/nCS3 PB1/nCS2 PB0/nCS1 PF6/CTCAP2B/CTCMP2B PE0/UARTRX2 VSS PE1/UARTTX2 PE2/CANRX/UARTRX0 PE3/CANTX/UARTTX0 PE4/SSPTX PE5/SSPRX PE6/SSPCLK PE7/SSPFRM VDD VDDA_ADC AN0(UL/X+)/PJ0 AN6/PJ1 AN1(UR/X-)/PJ2 AN8/PJ3 AN2(LL/Y+)/PJ4 AN9/PJ5 AN4(WIPER)/PJ6 AN3(LR/Y-)/PJ7 VSSA_ADC XTALOUT XTALIN VDDA_PLL VSSA_PLL XTAL32OUT XTAL32IN nPOR VSSC PD0/INT0 125 126 127 128 129 130 VSS PG4/LCDVEEEN PG3/LCDVDDEN PG2/LCDDSPLEN PG1 PG0 119 120 121 122 123 124 PF2/CTCAP0E PF1/CTCAP0D PF0/CTCAP0C PG7/CTCAP0B/CTCMP0B PG6/CTCAP0A/CTCMP0A PG5/CTCLK 113 114 115 116 117 118 PF5/CTCAP2A/CTCMP2A PF4/CTCAP1B/CTCMP1B PF3/CTCAP1A/CTCMP1A VDD 109 110 111 112 131 132 133 134 135 136 137 138 139 140 141 142 143 144 105 104 107 108 106 103 102 101 100 TOP VIEW LH75400-51 nRESETIN VSS RTCK TMS TEST1 TEST2 PD6/INT6/DREQ nRESETOUT LINREGEN TDO TDI TCK 144-PIN LQFP nCS0 PC7/A23 PC6/A22 VDD PC5/A21 PC4/A20 PD1/INT1 PD2/INT2 PD3/INT3/UARTTX1 VDDC PD4/INT4/UARTRX1 PD5/INT5/DACK
Table 5. LH75400 Numerical Pin List
Table 5. LH75400 Numerical Pin List (Cont’d)
120 PG4 LCDVEEEN 8 mA Bidirectional
122 PG2 LCDDSPLEN 8 mA Bidirectional
123 PG1 8 mA Bidirectional
124 PG0 8 mA Bidirectional
- Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.
- CMOS Schmitt trigger input.
- Signals preceded with ‘n’ are active LOW.
128 PH6 LCDLP 8 mA Bidirectional
129 PH5 LCDFP 8 mA Bidirectional
130 PH4 LCDEN 8 mA Bidirectional
Table 6. LH75400 Signal Descriptions
Table 6. LH75400 Signal Descriptions (Cont’d)
- These pin numbers have multiplexed functions.
- Signals preceded with ‘n’ are active LOW.
Figure 8. LH75410 Pin Diagram
Table 7. LH75410 Numerical Pin List
24 PB5 nWAIT 8 mA Bidirectional Pull-up 1
25 PB4 nBLE1 8 mA Bidirectional Pull-up 1
27 PB3 nBLE0 8 mA Bidirectional Pull-up 1
28 PB2 nCS3 8 mA Bidirectional Pull-up 1
29 PB1 nCS2 8 mA Bidirectional Pull-up 1
30 PB0 nCS1 8 mA Bidirectional Pull-up 1
Table 7. LH75410 Numerical Pin List (Cont’d)
- Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.
- CMOS Schmitt trigger input.
- Signals preceded with ‘n’ are active LOW.
Table 8. LH75410 Signal Descriptions
Table 8. LH75410 Signal Descriptions (Cont’d)
- These pins have multiplexed functions.
- Signals preceded with ‘n’ are active LOW.
frame buffer is 16KB or less. vided to access to the various APB peripherals. while the ARM core runs from local internal memory. frequency range is 98 MHz to 140 MHz. 28, 26, 24, and so on) of the PLL frequency. Figure 9. LH75401 System Application Example
when asserted. It is used as a Power-On Reset. JTAG circuitry, to their default state when asserted. The reset latency depends on the PLL lock state. A 4-stream general-purpose DMAC. Reset, Clock, and Power Controller (RCPC). of which are assigned to peripherals. Table 9. Bus Master Priority Table 10. Memory Mapping
processor as an ARM7TDMI-S bus slave. and accessible via processor, DMAC, and LCDC. does not cause a data or prefetch abort. AHB port for data transfers. – Memory to Peripheral (all streams). AHB port for data transfers. Table 11. APB Peripheral Register Mapping Table 12. DMAC Stream Assignments
System-on-Chip LH75400/01/10/11 Preliminary Data Sheet 6/4/03 49 Color LCD Controller (CLCDC) The CLCDC is an AMBA master-slave module that connects to the AHB. It translates pixel-coded data into the required formats and timings to drive single/dual monochrome and color LCD panels. Packets of pixel- coded data are fed, via the AHB interface, to two inde- pendently programmable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller (VIC) when an interrupt condition becomes true for upper/lower panel DMA FIFO underflow, base address update significa- tion, vertical compare, or bus error. NOTE: LH75401 and LH75411 microcontrollers support full-color operation. LH75400 and LH75410 microcontrollers are monochrome only. CLCDC FEATURES STN, Color STN, TFT, HR-TFT, and AD-TFT – Fully Programmable Timing Controls – Integrated Controller for displays with a low level of integration, such as HR-TFT and AD-TFT Programmable Resolution – Up to VGA (640 × 480 DPI), 12-bit Direct Mode Color – Up to SVGA (800 × 600 DPI), 8-bit Direct/Paletized Color – Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/ Grayscale – Direct or Paletized Colors Single and Dual Panels Supports Sharp and non-Sharp Panels CLCDC Outputs Available as General Purpose Inputs/Outputs (GPIOs) if LCDC is Not Needed Additional Features – Fully programmable horizontal and vertical timing for different display panels – 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM – AC bias signal for STN panels and a data-enable signal for TFT panels. Programmable Panel-related Parameters – STN mono/color or TFT display – Bits-per-pixel – STN 4- or 8-bit Interface Mode – STN Dual or Single Panel Mode – AC panel bias – Panel clock frequency – Number of panel clocks per line – Signal polarity, active HIGH or LOW – Little Endian data format – Interrupt-generation event. HR-TFT/AD-TFT Controller (HRTFTC/AD-TFT) The HRTFTC/ADTFTC is used with the CLCDC and accessed via the AMBA APB interface. The HRTFTC/ADTFTC is supplied with the standard TFT output from the LCDC and produces the neces- sary control and data signals to interface to an HR-TFT/ AD-TFT-type display. The HRTFTC/ADTFTC has two operating modes: Bypass Mode where input signals from the CLCDC pass directly to the output pins, without any signal reformatting. This is the default mode. HR-TFT/AD-TFT Mode for driving an HR-TFT/ AD-TFT display. NOTES: The HR-TFT/AD-TFT controller pertains to the LH75401 and LH75411 microcontrollers. VGA and XGA modes require 66 MHz core speed. Universal Asynchronous Receiver Transmitters (UARTs) The LH75400/01/10/11 microcontrollers incorporate three UARTs, designated UART0, UART1, and UART2. UART 0 AND 1 FEATURES Similar functionality to the industry-standard 16C550 Supported baud rates up to 921,600 baud (given an external crystal frequency of 14.756 MHz) Supported character formats: – Data bits per character: 5, 6, 7, or 8 – Parity generation and detection: Even, odd, stick, or none – Stop bit generation: 1 or 2 Full-duplex operation Separate transmit and receive FIFOs, with: – Programmable depth (1 to 16) – Programmable-service ‘trigger levels’ (1/8, 1/4, 1/2, 3/4, and 7/8) – Overrun protection. Programmable baud-rate generator that: – Enables the UART input clock to be divided by 16 to 65,535 × 16 – Generates an internal clock common to both transmit and receive portions of the UART. DMA support Support for generating and detecting breaks during UART transactions Loopback testing.
LH75400/01/10/11 System-on-Chip 50 6/4/03 Preliminary Data Sheet UART 2 FEATURES Similar functionality to the industry-standard 82510 Supported baud rates up to 3,225,600 baud (given a system clock of 51.6096 MHz) 5, 6, 7, 8, or 9 data bits per character Even, odd, HIGH, LOW, software, or no parity-bit generation and detection 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation µLAN address flag Full-duplex operation Separate transmit and receive FIFOs, with program- mable depth (1 or 4). Each FIFO has overrun protec- tion and: – Programmable receive trigger levels: 1/4, 1/2, 3/4, or full – Programmable transmit trigger levels: empty, 1/4, 1/2, 3/4. Two 16-bit baud-rate generators. One interrupt that can be triggered by transmit and receive FIFO thresholds, receive errors, control character or address marker reception, or timer timeout Generation and detection of breaks during UART transactions Support for local loopback, remote loopback, and auto-echo modes µLAN Address Mode. Timers The LH75400/01/10/11 microcontrollers have three 16-bit timers. The timers are clocked by the system clock, but have an internal scaled-down system clock that is used for the Pulse Width Modulator (PWM) and compare functions. All counters are incremented by an internal pre- scaled counter clock or external clock and can gener- ate an overflow interrupt. All three timers have separate internal prescaled counter clocks, with either a com- mon external clock or a prescaled version of the sys- tem clock. Timer 0 has five Capture Registers and two Com- pare Registers. Timer 1 and Timer 2 have two Capture and two Com- pare Registers each. The Capture Registers have edge-selectable inputs and can generate an interrupt. The Compare Registers can force the compare output pin either HIGH or LOW upon a match. The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt. The interrupt becomes active if any enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains active until all compare, capture, and overflow interrupts are cleared. Real Time Clock (RTC) The RTC is an AMBA slave module that connects to the APB. The RTC provides basic alarm functions or acts as a long-time base counter by generating an inter- rupt signal after counting for a programmed number of cycles of an RTC input. Counting in 1-second intervals is achieved using a 1 Hz clock input to the RTC. RTC FEATURES 32-bit up-counter with programmable load Programmable 32-bit match Compare Register Software-maskable interrupt that is set when the Counter and Compare Registers have identical values. Controller Area Network (CAN) The CAN 2.0B Controller is an AMBA-compliant peripheral that connects as a slave to the APB. The CAN Controller is located between the processor core and a CAN Transceiver, and is accessed through the AMBA port. CAN communications are performed serially, at a maximum frequency of 1MB/s, using the TX (transmit) and RX (receive) lines. The TX and RX signals for data transmission and reception provide the communications interface between the CAN Controller and the CAN bus. All peripherals share the TX and RX lines, and always see the common incoming and outgoing data. Bus arbitration follows the CAN 2.0A and CAN 2.0B specifications. The bus is always controlled by the node with the highest priority (lowest ID). Only after the bus has been released can the next highest priority node control it. Transmit and receive errors are han- dled according to the CAN protocol. Bus timing is critical to the CAN protocol. Therefore, the CAN Controller has two programmable Bus Timing Registers that define timing parameters. NOTE: The CAN Controller pertains to the LH75401 and LH75400 microcontrollers.
System-on-Chip LH75400/01/10/11 Preliminary Data Sheet 6/4/03 51 CAN 2.0B FEATURES Full compliance with 2.0A and 2.0B Bosch specifications Supports 11-bit and 29-bit identifiers Supports bit rates up to 1Mbit/s 64-byte receive FIFO Software-driven bit-rate detection for hot plug-in support Single-shot transmission option Acceptance filtering Listen Only Mode Reception of ‘own’ messages Error interrupt generated for each CAN bus error Arbitration-lost interrupt with record of bit position Read/write error counters Last error register Programmable error-limit warning. Analog-to-Digital Converter (ADC)/ Brownout Detector The ADC is an AMBA-compliant peripheral that con- nects as a slave to the APB. The ADC block consists of an 8-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller. The complete Touch Screen interface is achieved by combining the front-end biasing, control circuitry with analog-to-digital conversion, reference generation, and digital control. The ADC also has a programmable measurement clock derived from the system clock. The clock drives the measurement sequencer and the successive- approximation circuitry. The ADC includes a Brownout Detector. The Brown- out Detector is an asynchronous comparator that com- pares a divided version of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a Trip point, the Brownout Detector sets a status register bit. The status bit is wired to the VIC and can interrupt the processor core. This allows the Host Con- troller to warn users of an impending shutdown and may provide the ADC with sufficient time to save its state. ADC/BROWNOUT DETECTOR FEATURES 10-bit fully differential Successive Approximation Register (SAR) with integrated sample/hold 8-channel multiplexer for routing user-selected inputs to the ADC in Single Ended and Differential Modes 16-entry × 16-bit-wide FIFO that holds the 10-bit ADC output and a 4-bit tag number Front bias-and-control network for Touch Screen interface and support functions compatible with indus- try-standard 4- and 5-wire touch-sensitive panels Touch-pressure sensing circuits Pen-down sensing circuit and interrupt generator Voltage-reference generator that is independently controlled Conversion automation function to minimize control- ler interrupt overhead Brownout Detector. Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that have a Motorola SPI, National Semiconductor Microwire, or Texas Instruments DSP-compatible Synchronous Serial Interface (SSI). The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories. These memories store eight 16-bit values independently in both transmit and receive modes. During transmission: Data writes to the transmit FIFO via the APB interface. The transmit data is queued for parallel-to-serial conversion onto the transmit interface. The transmit logic formats the data into the appropri- ate frame type: – Motorola SPI – National Semiconductor Microwire – Texas Instruments DSP-compatible SSI. SSP FEATURES SSI in Master Only Mode. The SSP performs serial communications as a master device in one of three modes: – Motorola SPI – Texas Instruments DSP-compatible synchronous serial interface – National Semiconductor Microwire. Two 16-bit-wide, 8-entry-deep FIFOs, one for data transmission and one for data reception. Supports interrupt-driven data transfers that are greater than the FIFO watermark, but not an even multiple of it. Programmable clock bit rate. Programmable data frame size, from 4 to 16 bits long, depending on the size of data programmed. Each frame transmits starting with the most-significant bit. Four interrupts, each of which can be individually enabled or disabled using the SSP Control Register bits. A combined interrupt is also generated as an OR function of the individual interrupt requests. Loopback Test Mode.
tions. The timer must be reset by software periodically. Otherwise, a time-out occurs, interrupting the system. are accessed through the APB. Table 13. SSP Modes devices. Clock polarity and phase are programmable. compatible Serial Synchronous Interface devices. Microwire-compatible devices.
interrupt or a default-vectored interrupt. Two used as software interrupts. determined. On reset, all interrupts are disabled. The VIC also accepts software-generated interrupts. control as hardware-generated interrupts. 16 or more default-vectored interrupts. default-vectored interrupts. servicing is only available for IRQ interrupts. Table 14. Interrupt Channels
0 WDT Watchdog Timer
1 Not Used Available as a software interrupt
2 ARM7 DBGCOMMRX Sourced by the ARM7TDMI-S Core
3 ARM7 DBGCOMMTX Sourced by the ARM7TDMI-S Core
4 Timer0 Combined Timer0
5 Timer1 Combined Timer1
6 Timer2 Combined Timer2
7 External Interrupt 0 Sourced by the GPIO Block
8 External Interrupt 1 Sourced by the GPIO Block
9 External Interrupt 2 Sourced by the GPIO Block
10 External Interrupt 3 Sourced by the GPIO Block
11 External Interrupt 4 Sourced by the GPIO Block
12 External Interrupt 5 Sourced by the GPIO Block
13 External Interrupt 6 Sourced by the GPIO Block
14 Not Used Available as a software interrupt
15 RTC_ALARM Real Time Clock
16 ADC TSCIRQ (combined) Anal og-to-Digital Converter
17 ADC BrownOutINTR Brown Out Detector
18 ADC PenIRQ Analog-to-Digital Converter
19 LCD LCD Controller
20 SSPTXINTR Synchronous Serial Port
21 SSPRXINTR Synchronous Serial Port
22 SSPRORINTR Synchronous Serial Port
23 SSPRXTOINTR Synchro nous Serial Port
24 SSPINTR Synchronous Serial Port
25 UART1 UARTRXINTR UART1
26 UART1 UARTTXINTR UART1
27 UART1 UARTINTR UART1
28 UART0 UARTINTR UART0
29 UART2 Interrupt UART2
30 DMA DMA
31 CAN CAN (LH75401/LH75400)
Selecting the sources for various clocks. transition between the old and new frequencies. Supports external or watchdog reset status. Reset, all ports default to inputs. Table 15. Device Operating Modes Table 16. GPIO Ports
- MUSTN = Mono upper panel STN, dual and/or single panel.
- MLSTN = Mono lower panel STN, dual panel only.
Table 17. LCD Panel Signal Multiplexing Table 18. LCD External Pin Multiplexing (LH75401 and LH75411)
Table 19. LCD External Pin Multiplexing (LH75400 and LH75410)
- Linear regulator disabled; use of the on-chip linear regulator provides optimal performance.
- Linear regulator enabled.
- Will operate to DC with PLL disabled
- Processor is functional at minimum frequency, but not all peripherals may be enabled.
- The maximum operating frequency is the crystal frequency × 3.5.
Table 20. Absolute Maximum Ratings Table 21. Recommended Operating Conditions
- VIL MAX. = 0.5 V for pin TCK with 50 pF load.
- Running a Typical Application at 51.6 MHz.
- Using external 1.8 V supply, internal regulator disabled.
- Using Internal linear regulator.
Table 22. DC Characteristics Table 23. Linear Regulator DC Characteristics
ADC transfer characteristics.
- The analog section of the ADC takes 16 × A2DCLK cycles per conversion,
plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional 3 × PCLK cycles are required before being available on the APB.
- The internal voltage reference is driven to nominal value VREF = 2.0 V.
can be selected as reference voltages. The range of voltages allowed are specified above.
- The analog input pins can be driven anywhere between the power supply rails.
the A/D result will saturate appropriately at positive or negative full scale.
- Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
Table 24. ADC Electrical Characteristics at Industrial Operating Range
Figure 10. ADC Transfer Characteristics
delay and 1 wait state memory access. This is the worst case (fastest) timing. Table 25. Memory Interface Signals Table 26. Synchronous Serial Port Table 27. Power-up Stabilization
Figure 12. External Static Memory Write, One Wait State
1 WAIT STATE
- HCLK is an internal signal, provided for reference only.
- The corresponding byte lane enable(s) become active.
Figure 13. External Static Memory Write, Two Wait States
2 WAIT STATES
- HCLK is an internal signal, provided for reference only.
- The corresponding byte lane enable(s) become active.
Figure 14. External Static Memory Read, One Wait State
- HCLK is an internal signal, provided for reference only.
- The corresponding byte lane enable(s) become active.
Figure 15. External Static Memory Read, nWAIT Active
- HCLK is an internal signal, provided for reference only.
- The corresponding byte lane enable(s) become active.
Figure 16. Synchronous Serial Port Waveform
LH75400/01/10/11 System-on-Chip 68 6/4/03 Preliminary Data Sheet PACKAGE SPECIFICATIONS Figure 17.144-pin LQFP NOTE: Dimensions in mm. 22.00 NOM. 144LQFP-JEDEC 20.00 NOM. 22.00 NOM. 20.00 NOM. 0° MIN. 0-7° MIN. 1.00 REF. 0.60 ±0.15 0.20 MIN. 0.08 R. MIN. 0.08/0.20 R. 0.5 NOM. 1.40 MAX. 144LQFP (JEDEC MS-026) TOP VIEW 0.25 GAUGE PLANE
System-on-Chip LH75400/01/10/11 ©2003 by SHARP Corporation Reference Code SMA03009 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3
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