LH6V4256

LH6V4256 SHARP | Alldatasheet

Document overview

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Technical content

LH6V4256 CMOS 1M (256K × 4) Dynamic RAM FUNCTION

• • 262,144 words × 4 bit
• • Access time: 100 ns (MAX)
• • Cycle time: 190 ns (MIN)
• • Fast page mode cycle time: 60 ns (MIN)
• • Power supply: +3.3 V ±0.3 V
• • Power consumption (MAX): Operating: 126 mW Standby: 0.54 mW
• • Built-in latch circuit for row-address, column-address, and input data OE = Don’t care in early write operation
• • RAS only refresh, hidden refresh, and CAS before RAS refresh capability
• • On-chip refresh counter
• • 512 refresh cycle/8 ms
• • Packages: 20-pin, 300-mil DIP 26-pin, 300-mil SOJ 28-pin, 8 × 13 mm2 TSOP (Type I)

DESCRIPTION

The LH6V4256 is a 262,144 word × 4-bit dynamic RAM which allows fast page mode access. The LH6V4256 is fabricated on SHARP’s advanced CMOS double-level polysilicon gate technology. With its input multiplexed and packaged in the standard 20-pin DIP , 26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to realize memory systems with low power dissipation and large memory capacity. The LH6V 4256 operates on a single +3.3 V power supply and the built-in biasing voltage generator circuit. PIN CONNECTIONS 6V4256-1 TOP VIEW NC WE RAS CAS I/O4 VSS VCC OE 20-PIN DIP I/O3 I/O2 I/O1 Figure 1. Pin Connections for DIP Package

NOTE: Pin numbers apply to the 20-pin DIP. Figure 4. LH6V4256 Block Diagram

NOTE: Pin numbers apply to the 28-pin TSOP (Type I). Figure 5. LH6V4256 Block Diagram

PARAMETER RATING UNIT NOTE Applied voltage on all pins –0.5 to +5.5 V 1 Output short circuit current 50 mA Power dissipation 1.0 W Operating temperature 0 to +70 °C Storage temperature –65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to VSS . RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 3.0 3.3 3.6 V VSS 00 0 V Input voltage VIH 2.3 V CC + 0.3 V VIL –0.3 0.6 V CAPACITANCE (T A = 0 to +70°C, f = 1 MHz, VCC = 3.3 V ±0.3 V) PARAMETER CONDI TIONS SYMBOL MIN. MAX. UNIT Input capacitance A0 – A8 C IN1 6p F RAS, OE, CAS, WE C IN2 7p F Input/output capacitance I/O1 – I/O4 C OUT1 7p F DC ELECTRICAL CHARACTERIST ICS (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT NOTE Average supply current in normal operation I CC1 35 mA 1, 2, 3 Supply current in standby mode RAS = CAS ≥ VCC – 0.2 V I CC2 0.15 mA 1 Average supply current in fast page mode I CC3 30 mA 1, 2 Average supply current in CAS before RAS refresh cycle I CC4 35 mA 1, 2, 3 Average supply current in RAS only refresh cycle I CC5 35 mA 1, 2, 3 Input leakage current 0 V ≤ VIN ≤ 4.8 V

0 V except on test pins ILI –10 10 µA

Output leakage current0 V ≤ VOUT ≤ 4.8 V Output in high-impedance state ILO –10 10 µA Output ‘High’ Voltage IOUT = –200 µ A VOH 2.15 V Output ‘Low’ Voltage IOUT = 1 mA V OL 0.4 V NOTES: 1. Specified values are with outputs open. 2. ICC1 , ICC3 , ICC4 , and ICC5 depend on cycle time. 3. Cycle time is 190 ns. Address transition is once at RAS = VIH and once at RAS = VIL. LH6V4256 CMOS 1M (256K × 4) Dynamic RAM 2-18

AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4 (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) READ CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE Random read or write cycle time t RC 190 ns Access time from RAS t RAC 100 ns 5 Access time from column address t AA 50 ns 5 Access time from CAS tCAC 40 ns 5 Access time from OE tOEA 35 ns 5 Row address setup time t ASR 0n s Row address hold time tRAH 15 ns Column address setup time tASC 0n s Column address hold time (RAS) tCAH 20 ns Column address delay time (RAS) t RAD 20 50 ns 6 Column address lead time (RAS) t RAL 50 ns RAS pulse width t RAS 100 10,000 ns RAS precharge time t RP 80 ns CAS precharge time (RAS ↓ )t CRP 0n s CAS delay time (RAS) t RCD 25 60 ns 7 CAS lead time (RAS) t RSL 30 ns CAS pulse width t CAS 40 10,000 ns CAS hold time t CSH 100 ns OE lead time (RAS) t ROL 0n s Output data disable time (CAS) t OFF 30 ns Output data disable time (OE) t OEZ 30 ns Output data hold time (CAS) t SOH 0n s Output data hold time (OE) t OOH 0n s Read command setup time (CAS) t RCS 0n s Read command hold time (CAS) t RCH 10 ns 8 Read command hold time (RAS ↑)t RRHP 10 ns 8 Read command hold time (RAS ↓)t RRHN 115 ns 8 Transition time (rise and fall) t T 33 5n s Refresh time interval t REF 8m s NOTES: 1. For proper memory function, at least 200 µs of pause time should be kept after power on, followed by several dummy cycles. When RAS = VIH is continued for more than 8 ms, the same dummy cycles should be given. Usually eight ordinary refresh cycles should be given. 2. The required VCC current (ICC ) during power on depends on the input levels of RAS. If RAS = VIL during power on, the device goes into an active cycle, and ICC exhibits large current transients. It is rec- ommended that RAS tracks with VCC or be held at a valid VIH during power on. 3. AC characteristics assume tT = 5 ns. 4. AC characteristics assume the following condition (see figure at right). 5. Load condition for 1TTL + 30 pF . 6. tRAD (MAX) is the maximum point for tRAD where tRAC (MAX) is ensured, and does not represent a limit of operation. If tRAD ≥ tRAD (MAX), the access time comes under the control of tAA. 7. tRCD (MAX) is the maximum point for tRC D, where tRAC (MAX) is ensured and does not represent a limit of operation. If tRC D ≥ tRCD (MAX), the access time comes under the control of tCAC . 8. The operation is ensured when either tRRHN , tRR HP, or tRCH is satisfied. 6V4256-6 INPUT LEVEL 2.3 V 0.6 V 2.15 V 0.4 V OUTPUT JUDGMENT LEVEL CMOS 1M (256K × 4) Dynamic RAM L H6V4256 2-19

PARAMETER SYMBOL MIN. MAX. UNIT NOTE Fast page mode cycle time t PC 60 ns CAS precharge time t CP 10 ns CAS precharge access time t CACP 55 ns Read-write cycle time (page mode) tPRWC 125 ns 1 NOTE: 1. tRWC , tRWD , tAW D, tCWD , and tPRWC are not restrictive operating parameters and does not represent a limit of operation. WRITE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE EARLY WRITE Write command setup time (CAS) t WCS 0n s 1 Write command hold time (CAS) t WCH 15 ns Data input setup time t DS 0n s Data input hold time t DH 20 ns OE CONTROLLED CAS setup time t CWS 0n s 1 Write command lead time (RAS) t RWL 30 ns Write command lead time (CAS) t CWL 25 ns Write pulse width (WE) t WP 15 ns OE hold time (WE) t OEH 20 ns NOTE: 1. tWCS and tCWS are not restrictive operating parameters. If tWCS ≥ tWCS (MIN), the cycle is an early write cycle and data out buffers remain inactive until CAS rises again. READ-WRITE CYCLE/READ-MODIFY-WRITE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read-write cycle time t RWC 260 ns 1 WE delay time (RAS) t RWD 135 ns 1 Column address delay time (WE) t AWD 85 ns 1 WE delay time (CAS) tCWD 65 ns 1 OE delay time tOED 25 ns NOTE: 1. tRWC , tRWD , tAW D, tCWD , and tPRWC are not restrictive operating parameters and does not represent a limit of operation. CAS BEFORE RAS REFRESH CYCLE/HIDDEN REFRESH CYCLE PARAMETER SYMBOL MIN. MAX. UNIT CAS setup time (RAS) t CSR 0n s CAS hold time (RAS) t CHR 20 ns RAS • CAS precharge time (RAS ↑) tRPCP 10 ns RAS • CAS precharge time (RAS ↓) tRPCN 115 ns WE precharge time (RAS) t WRP 0n s LH6V4256 CMOS 1M (256K × 4) Dynamic RAM 2-20

Figure 6. Read Cycle

Figure 7. Write Cycle (Early Write)

Figure 8. Write Cycle (OE Controlled Write)

Figure 9. Read/Write Cycle

Figure 10. Fast Page Mode Read Cycle

Figure 11. Fast Page Mode Write Cycle

Figure 12. Fast Page Mode Read/Write Cycle

Figure 15. Hidden Refresh Cycle

2.54 [0.100] TYP. 7.62 [0.300] TYP. 0.56 [0.022] 0.36 [0.014] 0.51 [0.020] MIN 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 3.65 [0.144] 3.25 [0.128] 0.30 [0.012] 0.20 [0.008] 0° TO 15° 20DIP (DIP020-P-0300A) DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 20DIP-3 7.05 [0.278] 6.65 [0.262] 24.75 [0.974] 24.25 [0.955] 20-pin, 300-mil DIP 26SOJ (SOJ026-P-0300) 26SOJ-2 1.27 [0.050] TYP. 8.50 [0.335] 8.30 [0.327] 7.90 [0.311] 7.50 [0.295] 7.00 [0.276] 6.60 [0.260] 0.25 [0.010] 0.15 [0.006] 0.53 [0.021] 0.33 [0.013] 3.70 [0.146] 3.30 [0.130] 0.20 [0.008] 0.50 [0.020] 1.10 [0.043] 1.70 [0.067] 17.40 [0.685] 17.00 [0.669] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 26-pin, 300-mil SOJ LH6V4256 CMOS 1M (256K × 4) Dynamic RAM 2-30

10 100 Access Time (ns) D 20-Pin, 300-mil DIP (DIP020-P-0300A) K 26-Pin, 300-mil SOJ (SOJ026-P-0300) T 28-Pin, 8 x 13 mm

2 TSOP (Type I) (TSOP028-P-0813)

X Package - ## Speed 6V4256-17 Example: LH6V4256D-10 (CMOS 1M (256K x 4) Dynamic RAM, 100 ns, 20-Pin, 300-mil DIP) CMOS 1M (256K x 4) Dynamic RAM

ORDERING INFORMATION

DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP (TSOP028-P-0813) 28TSOP 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 12.00 [0.472] 11.60 [0.457] 13.70 [0.539] 13.10 [0.516] 8.20 [0.323] 7.80 [0.307] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 12.60 [0.496] 12.20 [0.480] 0.20 [0.008] 0.10 [0.004] 0.20 [0.008] 0.00 [0.000] 1.10 [0.043] 0.90 [0.035] 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0 - 10° DETAIL 0.425 [0.017] 28-pin, 8 × 13 mm 2 TSOP (Type I) CMOS 1M (256K × 4) Dynamic RAM L H6V4256 2-31