LH5497 SHARP | Alldatasheet
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' FEATURES PIN CONNECTIONS @ Fast Access Times: 28-PIN PDIP TOP VIEW 15/20/25/35/50/65/80 ns Woe 281 Voc @ Full CMOS Dual Port Memory Array Dot 2 271) Dy | pv; 3 261) Ds @ Fully Asynchronous Read and Write b, 4 25[] Ds @ Expandable in Width and Depth oO 5 24t) Dy do 6 23:1 FUAT @ Full, Half-Full, and Empty Status Flags xO7 20 Aas @ Read Retransmit Capability Fre a ; ads 2017) XOMF @ TTL Compatible /O Q, Cho 191) Q, @ Packages: aun 1811 2, 28-Pin, 300-mil DIP Ds U12 17) Qs 28-Pin, 600-mil DIP O13 161 Oy 32-Pin PLCC Vg [14 1sOR . . . 5497-10) @ Pin and Functionally Compatible with IDT7202 Figure 1. Pin Connections for DIP Package FUNCTIONAL DESCRIPTION The LH5497 is a dual port memory with internal ad- : dressing to implement a First-In, First-Out algorithm. S2-PIN PLOG e © o 8. w TOP VIEW Through an advanced dual port architecture, it provides eal 2sag fully asynchronous read/write operation. Empty, Full, and Half-Full status flags are provided to prevent data over- e flow and underflow. In addition, internal logic is provided 25 2917 Ds for unlimited expansion in both word size and depth. 0, U6 281) 0; , . . o, 7 2710 NC Read and Write operations automatically access se- xq — quential locations in memory in such a way that data is xt 8 26H) FURT read out in the same order that it was written, that is on a rr Oe 25) RS First-In, First-Out basis. Since the address sequence is Q Chro 240 EF internally predefined, no external address information is Q, On 2310 XOF required for the operation of this device. A ninth data bit Ne (12 22f] a, is provided for parity or control information often needed Q, C13 211) a, in communication applications. 14 15 16 17 18 19 20 Empty, Full, and Haif-Full status flags monitor the u extent to which data has been written into the FIFO, and eos ez 9° prevent improper operations (i.e. Read if the FIFO is 5407-20) empty, or Write if the FIFO is full). A retransmit feature ., 7 resets the Read address pointer to its initial position, Figure 2. Pin Connections for PLCC Package thereby allowing repetitive readout of the same data. Expansion In and Expansion Out pins implement an expansion scheme that allows individual FIFOs to be cascaded to greater depth without incurring additional latency (bubblethrough) delays. ooo, SHARP 5-31
Figure 3. LH5497 Block Diagram
ABSOLUTE MAXIMUM RATINGS ! NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the "Operating Range” of this specification is notimpled. Exposure to absolute maximum rating conditions for extended periods may affect refabilty. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. OPERATING RANGE [symeot [| _parameren | wn [wax | unrr | [ta | Temperature.ambient | o | 70 | <o | [ves | supy votawe | as [ss |v | [vss [Supply votage | o | oo | v | [vu | Logicvor mputvorage' | -o5 | os | v | [vn [tenie“rnpt vote | 20 | voo+05 |v NOTE: 1, Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) [sywpo. [PARAMETER | —TESTCONDTIONS __—(|_~MN | wax | unrr | [| Input teakage Curent | Voo=55¥.vw=0Vtevec | -10 | 10 | HA | [vou | Ovtputrigh votage | ton=-2.0ma_— | 2 | — |v | [vou | Outputtow votage | -8oma | — [oe |v [tcc | Average Supply Current’ | Measuredatt=omHz | — | 100 | ma | [toce | Average Standby Current’ | Aiinputs=vn | — | 18 | ma | [cca | Power Down Curent’ | Auinputs=Veo-o2v | — | 5 | ma | NOTE: 1. loc, lece, and Iocs are dependent upon actual output loading and cycle rates. Specified values are with outputs open. SHARP 5-33
Figure 4. Output Load Circuit
- Capacitances are maximum values at 25°C measured at 1.0MHz with Vin = 0 V.
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) [neo] PARNER aa aoe oN [inc | Readcycetime _—=«z 28 | - | 50] - [as - [4s] - [os] = [ao] - [roo] - [ ns | [wm | Accosstime __———*+| - +(| 18 - [20] - | as] - [as] - [so] - [os - [eo] ns | [tan | Read Recovertime | t0| - | so | - | vo] - | ao] - [as] - [as] - | v5 - | ns | [tapw | Read Pusewiah? | 15| - | 20| - [as| - [as] - [so] - [os] - | eo} -[ ns | [tz | Data Bus ActvetromReadtow? | 5 |-|s|-|s{-|[s|-[s|[-[s]- |r} -] ns | wiz | Data Bus Active trom witeHiGH®*| 10 | - | 10 | - [ao | = | x0] - [o[ - [io] - [aol -{ ns | [tne | Data Bus HighZtrom Read nicH® | - | 18 [ - [15] - | 1s] - [vs] - [20 - [0] - [20] ns | [we | WiteGycwtime ———=«d 25 | - | 90 | - [as] - [as] - [os] - [ao] - [roo] - [ ns | [awew | WitePusowim? _——'( 15| - | 2o| - | as| - [as] - [so] - [os] - | ool - | ns | [wn | Wite Recovery Time ‘| 10| - | 1o[ = | vo] - | ao] - Tas] - [is] - [asf = | ns | [tos | DataSouptime ___——*| to[ - | vo | = [vo] - [as | - [a0] - | ao] - [ao] - | ns | ion | Datatotime _—sitol-|o{-[ol-J;o{-Jo|-[s[-[s]-] ss | [imac | Resstoyotime ___—‘| a8] - [ao[ - [as] - [as] - [os] - [ao] - [roo] - [ ns | [tas | ResetPusewistn? + 15 - | 20] - | as| = | as| - [so] - [es] - | e0| - | ns | [tase | Resetecovey Time | t0| - | to] - | vo - [vo] - fas] - fas] - [ss] - | ns | [inns | ReadHIGHwRSHicH | 15 - | 20| - [as] - |as| - |so|- [es - [ao] - | ns | [iwass | WiteHIGHtoRSHIGH | 151 — | 20 | = [as] - | as| - [so] - [os] - [eo] -[ ns | [tare | Retranomit Gyciotime | 251 - | s0| - [a5] - [as] - [os - [eo [ = [roo] - [ rs | [tar | RetransmitPusowan® | 18 { - | 20| - | 25| = | as] - [so] - [os] - [oo] - | os | [tara | Retransmit Recovery time | to - | to] - [xo] = [vo] - fas[- [as] - [ss] - | os | [ter | Reset owio EmpyFagtow | - | 25] - [a0] - [as] - [as[- [os { - feof - [roo] ns | Reset LOW to Half-Full and Full Frm | Bemtgmapevartentrt | — [| - so] — [os] [os] - [os] oo] - [ro] os | [ter | Read LOW wEmpy Fagiow | - | 20| - [a5] - [25] = | a5] - [45] - [oo] - | eof ns | Care | Read HIGH to Ful FiaghicH | - | 20| - | as| - [25 | - | as | - [as] - [eo] - [oo] ns | [wer _| WiteHIGH to Empry FlagHiGH | - | 20| — | 25| = [as] - [as] - [as|- [eof - [oo] ns | [ower | WiteLowtoFulFlagtow | - | 20| - | 25| - | 2s | - [as | — | as | - [eof - | ol] ns | awe | Wate LOW to Hat-FullFlaglow | — | 25| - | 30 | - | a5] - | «s[ - [os | [eo[ - [too] ns | [tae | Read HIGHto Hat-Fut FlagHiGH | - | 25 | - [30 | - [a5] - [4s - [es | - [20] - [100] ns | [ior | expansionomtow —_—*«| - ‘|e | - [20 - [as] - Tas] - [so] - [es] - [eo] ns | Coxon | Expansionounich | - | 18| - | 20| = | es| = | a5 | ~ [s0[ - [es] - [eo] rs | Ca | Expansion inPuse wath | 18| - | 20| - | 25] - | as[ - [so] - [es| - [eo] - | ns | [win | Expansion in Recovery Time | 10{ - | 10| - | 10] - | vo - |so[ - [of - [ro] - | os | [us| Expansion insewp time | 7 | - | to| - | ol - [is] - [ss] - [as[ - [1s{ - | rs | NOTES: 1. All timing measurements performed at “AC Test Condition” levels. 2. Pulse widths less than minimum value are not allowed. 3. Values guaranteed by design not currently tested. 4. Only applies to read data flow-through mode. ee SHARP 5-35
OPERATIONAL DESCRIPTION The internal read and write address pointers are main- tained by the device such that consecutive read opera- Reset _ tions will access data in the same order as it was written. The device is reset whenever the Reset pin (RS) is The Empty flag is asserted (EF = LOW) after the falling taken to a LOW state. The reset operation initializes both edge of R which accesses the last available data in the the read and write address pointers to the first memory FIFO memory. EF is deasserted (EF = HIGH) after the location. The XI and FL pins are also sampled at this ime next rising edge of W loads another word of valid data. to determine whether the device is in Single mode or Depth Expansion mode. A reset pulse is required when Data Flow-Through _ the device is first powered up. The Read (R) and Write Read flow-through mode occurs when the Read (R) Ww) pins may be in any state when reset is initiated, but pin is brought LOW while the FIFO is empty, and held must be brought toa HIGH state tapw and twew before LOW in anticipation of a write cycle. At the end of the next the rising edge of RS. write cycle, the Empty flag will be momentarily deas- serted, and the data just written will become available on Write the data out pins after a maximum_time of twer + ta. __Awrite cycle is initiated on the falling edge of the Write Additional writes may occur while the R pin remains LOW, (W) pin. Data setup and hold times must be observed on but only data from the first write flows through to the the datain (Do — Dg) pins. Awrite operation is only possible outputs. Additional data, if any, can only be accessed by if the FIFO is not full, (i.e. the Full flag pin is HIGH). Writes toggling R. may occur independently of any ongoing read operations. Write flow-through mode occurs when the Write (Ww) At the falling edge of the first write after the memory is pin is brought LOW while the FIFO is full, and held LOW half filled, the Half-Full flag will be asserted (HF = LOW) in anticipation of a read cycle. At the end of the read cycle, and will remain asserted until the difference between the the Full flag will be momentarily deasserted, but then write pointer and read pointer indicates that the remaining immediately reasserted in response to W held LOW. Data data in the device is less than or equal to one half the total is written into the FIFO on the rising edge of W which may capacity of the FIFO. The Half-Full flag is deasserted occur trFF + twew after the read. (HF = HIGH) ty the appropriate rising edge of R. Retransmit The Ful flag is asserted (FF = LOW) atthe falling edge The FIFO can be made to reread previously read data of the write operation which fills the last available location h the retransmit function. Retransmit is initiated by inthe FIFO memory array. The Full flag will inhibit further “rough the retransmit Ret isi ¥ writes until cleared by a valid read. The Full flag is Pulsing RT LOW. This resets the internal read address deasserted (FF = HIGH) after the next rising edge of pointer to the first physical location in the memory while releases another memory location leaving the internal write address pointer unchanged. . Data between the read and write pointers may be reac- Read cessed by subsequent reads. Both R and W must be Atead cycle is initiated on the falling edge ofthe Read ‘inactive (HIGH) during the retransmit pulse. Retransmit a ‘ is useful if no more than 1024 writes are performed (R) pin. Read data becomes valid on the data out (Qo-Qs) R it fiect the status of EF, pins after a time ta from the falling edge of R. After R goes pee es. transmit may affect the status of EF, HIGH, the data out pins return to a high-impedance state. F and FF flags, depending onthe relocation ofthe read r : . jointer. This function is not available in depth expansion Reads may occur independent of any ongoing write p de. Operations. Areadis only possible if the FIFO is notempty mode. (EF = HIGH). Send 5-36 SHARP
required number of FIFOs in Expansion mode. In this Data In pins of all devices are tied together. this device to ground. All other devices must have their mit functions are not available in Depth Expansion mode. FL pin tied to a high level. In this mode, W and R signals. Figure 19. FIFO Depth Expansion (3072 x 9)
ORDERING INFORMATION
LH5497 x -## = [38 Device Type Package Speed 25
35 Access Time (ns)
Blank 28-pin, 600-mil DIP (DIP28-P-600) D 28-pin, 300-mil DIP (DIP28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) CMOS 1K x 9 FIFO Example: LH5497U-25 (CMOS 1K x 9 FIFO, 32-pin PLCC, 25 ns) sao7uo SHARP 5-45