LH5493 SHARP | Alldatasheet
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L H 549 3 4K x 9 Parallel-to-Serial FIFO SSS FEATURES Thus, if two LH5493s are paralleled, the combination can input 18-bit halfwords; and it can either output 18-bit © Fast Cycle Times: 30/35 ns halfwords, or else output a serial bitstream for 18-bit-to- Frequency: 33/28.5 MHz 41-bit PISO operation. This paralleling scheme extends without change to an arbitrary number of LH5493s. © Parallel Data In; Serial Data and/or Parallel Data Out The LH5493 architecture supports synchronous op- © Serial Input and Serial Shift Capability in Output eration, tied to two independent free-running clocks at the Register, for Long-Word-Length Parallel-to-Serial input and output ports respectively. However, these Operations ‘clocks’ also may be aperiodic, asynchronous ‘demand’ signals; they do not need to be synchronized with each @ Read Enable Input and Two Write Enable other in any way. Almost all control input signals and Inputs, Sampled on Rising Edge of the Appropriate status output signals are synchronized to these clocks, to Clock simplify system design. The input and output ports oper- @ Fast-Fall-Through Time Internal Architecture Based ate altogether independently of each other, except when on CMOS Dual-Port SRAM Technology, 4096 x 9 the FIFO becomes either totally full or else totally empty. ‘Two edge-sampled enable control inputs, WEN1 and ‘@ Fully Asynchronous Read and Write Operations WENa, are provided for the input port; and one such @ Full, Haf-Full, Almost-Empty/Full, and control input, REN, is provided for the output port. These Empty Flags synchronous control inputs may be used as write de- mands and read demands respectively, when an LH5493 @ Reset/Reread Capability is interfaced to continuously-clocked synchronous sys- . tems. Data flow is initiated at a port by the rising edge of © TTLCMOS-Compatible VO the clock signal corresponding to that port, and is gated © 32-Pin PLCC Package only by the appropriate edge-sampled enable control input signal(s). FUNCTIONAL DESCRIPTION The LH5493 is a FIFO (First-In, First-Out) memory PIN CONNECTIONS device, based on fully-static CMOS RAM technology, capable of containing up to 4096 nine-bit words. One 3p PIN PLCC ~ TOP VIEW LH5493 FIFO can input nine-bit bytes; and it can either oom 8888 ‘output nine-bit bytes in parallel, or else output a serial Sct $258 bitstream. Thus, a single LH5493 is capable of nine-bit- to-one-bit PISO (Parallel-In, Serial-Out) operation. . ‘An LH5493 has one 9-bit parallel input (write) port, and Gs 201) Os one nine-bit parallel output (read) port. And there is one os 28F) Dy ‘one-bit serial input, which supports paralleling LH5493s Do 7 277) 0, for greater-word-width PISO operation. This serial input RsC]s 261 Dy also allows additional control bits to be inserted at willinto Ke Oo asf) AF the serial output bitstream. There is no serial output port @ Cho 2407 a, as such; any individual bit position in the parallel output a, di 23H o, register may be chosen as the serial-output data path, a, Che 22H a according to the desired time phase of the output bit- ods nha, ‘stream. 14 15 16 17 18 19 20 ‘The LH5493 architecture supports a very convenient CoOUoUoo method of paralleling multiple FIFOs for PISO operation, 65 35 215 without any additional logic being needed, in order to seq 540340] achieve a wider ‘effective FIFO.’ The paralleled LH5493 combination remains capable of performing all of the ‘4 i operations which a standalone LH5493 can perform. Figure 1. Pin Connections for PLCC Package a 5-94 SHARP
4K x9 Parallel-to-Serial FIFO LH5493 FUNCTIONAL DESCRIPTION (cont'd) may be tied directly to WEN1 or to WENe, and the Empty ; ; flag likewise may be tied directly to REN, in order to The following FIFO status flags monitor the extent to prevent overrunning or underrunning the internal FIFO which ne intemal memory hasbeen filed: Ful. HaltFul: Boundaries, (Sae Figure 1.) Imost-Empty/Full, and Empty. The Almost-Empty/Ful Alternatively, the enabling of write or read operations flag is asserted whenever the internal memory is either 4 e ; whenever the i emory may be controlled entirely by external system logic, while within eight locations of ‘empty,’ or else within eight loca: ff ‘ " gic, wh within eight nin eigh fe flags serve strictly as system interrupts. This design tions of ‘full’ The Hall-Full flag serves to distinguish the " , ne Ha" . gush | approach works well when the input port clock and the ‘lmost-emply’ condition from the ‘almost-ull condition. a en on cach other Also, during fully-synchronous operation, the Full flag : 4Kx9 OUTPUT DATANN DUAL PORT SHIFT meet one RAM ARRAY ’ REGISTER] si ° INPUT OUTPUT wor PORT WRITE READ PORT ren , CONTROL | POINTER | POINTER CONTROL — WEN, Losic Losic LowsH Fr OHF ORE OF Per Figure 2, LH5493 Block Diagram SIGNAL PIN DESCRIPTIONS. [AS ___| Reset. An assertive-LOW input which initializes the internal address pointers and flags. Write Clock. A free-running clock input for write operations. Read Clock. A free-running clock input for read operations. [-st___| Serial Input. A serial data input to allow paralleled PISO operation of multiple devices. Data Inputs. Do ~ Ds are sampled on the rising edge of WCK, whenever both WEN and WENe are Do- Ds | Pa! being asserted.. Data Outputs. Qo — Qs are updated following the rising edge of RCK, whenever REN is being asserted. Write Enable 1. An assertive-HIGH input signal which is sampled on the rising edge of WCK to control the flow of data into the FIFO. Both WEN; and WENz2 must be asserted in order to enable awrite operation. Write Enable 2. An assertive-HIGH input signal which is sampled on the rising edge of WCK to control WEN2 | the flow of data into the FIFO. Both WEN: and WENe must be asserted in order to enable a write operation. Read Enable. An assertive-HIGH input signal which is sampled on the rising edge of RCK to control the flow of data out of the FIFO. Lo/Sr_| Read Load/Shitt. An input signal which is sampled on the rising edge of ACK to control the loading or shifting of data in the output register. Full Flag. An assertive-LOW output indicating when the FIFO is full. [HF | Half-Full Flag. An assertive-LOW output indicating when the FIFO is more than half full. ‘Almost-Empty/Full. An assertive-LOW output indicating when the FIFO either is within eight locations of full, or else is within eight locations of empty. Empty Flag. An assertive-LOW output indicating when the FIFO is empty. SHARP 5-95
LHS493 4K x 9 Parallel-to-Serial FIFO ABSOLUTE MAXIMUM RATINGS ' NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any. ‘other conditions outside those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 3. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle. OPERATING RANGE [svweoc] _panaweren [wn [wax [unc | [ta __| Temperature, ambient | 0 | 70 | °c | [Voo | Suppyvotage | 45 | 55 |v | [ vss | suppy voltage | 0 | oo | v | [vn | togietowinputvotage'[-05| 08 | Vv | [vw | togicHicHinput votage | 22 | veo+os | v | NOTE: . 1, Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) [svmpo.| PARAMETER | ___Tesrconomons | ww [ max | unr | [iu | Inputueakage Curent | Voo=55V.Vw=oVvtovec | -10 | 10 | ya | [vor | output tow vorage | la-som | S| ow | [Vow | OuptHIGH votage | ou=-20ma— | 2a | |v icc | average Supply Curent™ | Measured atfc=max |_| 180 | ma | [tece | Average Standuy Current’ | Auimous=viw |_| 28 | ma wee and Icc2 are dependent upon actual output loading and cydle rates. Specified values are with outputs open: and, for Icc, operating at minimum cycle times. a 5-96 SHARP
4K x9 Parallel-to-Serial FIFO LH5493 AC TEST CONDITIONS [panameten |RATING _ | cay] Input Pulse Levels onus : Input Rise and Fall Times (10% to.90%) | __5ns__| oewce Input Timing Reference Levels UNDER Output Reference Levels 240 OHMS 30 pF” Output Load, Timing Tests, | Figures _| CAPACITANCE *? = [paramere] mare] (nines xe no seore cnpserces en Cin (Input Capacitance) Figure 3. Output Load Circuit Co (Output Capacitance) NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25°C, measured at 1.0MHz with Vix = 0 V. SHARP 5.97
AC ELECTRICAL CHARACTERISTICS 1 (Voc = 5 V + 10%, Ta = 0°C to 70°C) [eno [ csr a ma a a | Line wie Cet cyoetine a | foo | - foe | - Lo | iT Wie cushion tine So = Pet | wf | oo | [im [wine Costtowtme Sd to f= fe fff | os | [ine | ReasGoskcyoe tine ————*d as | = | oof | os [| os | [im | Reascosenicntine «dt of = | || wf - | | ee [ee [ bata souptine ortangcex +f 10 - | of - | 0] - | we | Tien | baa Wout rom Ang Gece =i © [=| o|-]o|-| | [its | ena Soup tmeionisng cer | of - [wl - [wl -| me | [ie | Enave Hoe Tine wom Asing we | ot -o|-|o|-| =| [x | oamovpsaccestme | - tm | - || - lal | Vox | Ouptwostine tomaisnprox «dts | - | 8 | - | s | -| ms | [ier | coccwenpy Fug vas SSS to [fe | - [| os | Ler [costorurapvais Sid = ‘Pot - |e | - fas] | [ce | vsttovanrutragvea | - fas] - Tor] - | «| = | a a ee [ins | Reset use wom SSS—~i as [ - | oot - fos | - | oe | a line | ResetLowioFig vas ———SS~ = fm] - fae | - [os | os | Fe ee eee [em [Finnescaeny® —SSS~i te | - | |= | 0] | oo | Lem [rretwie taney? —SSSSSCid to | - fw [= | 20 | = | oe | earning measurements performed at ‘AC Test Condition’ levels. 2. Value guaranteed by design; not currently production tested. 3. tags need not be met unless either a rising edge of WCK occurs while WEN: and WENz both are being asserted, or else a rising edge of RCK 4, tencis the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data. 5. tewis the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successtul write. a 5-98 SHARP
4K x9 Parallel-to-Serial FIFO LH5493 OPERATIONAL DESCRIPTION (Qo — Qs) by a time ta after the rising edge of RCK. A shift of data in the output register is performed whenever REN Reset is held HIGH and LD/SHis held LOW on the rising edge The device is reset whenever the asynchronous reset of RCK. Datais shifted in the MSB-to-LSB direction, with input (RS) is asserted, ie., taken to aLOWstate. Areset data from the Serial Input (SI) replacing the contents of ‘ operation is required after power up, before the first write _bit position Qe. operation occurs. The reset operation initializes both the When an emply condition is reached, read operations read and write address pointers to the_first physical n ; , a should be ceased, until a valid write operation(s) has memory jocation. After the falling edge of RS, the status I.deq adkitional data into the FIFO. The state of the four flags (FF, HF, AEF, and EF) are updated to indicate a at - four valid empty condition. ‘Status flags has nodirect effect on read or shift operations; 7 that is, the execution of read or shift operations is gated Read, shift, and/or write operations neednotbedeac- only by REN and LD/SH, and the internal logic of the tivated during a reset operation. However, failure todo so _—LH5493 itself has no interlock to prevent underrunning requires observance of the Reset Setup Time (tnss), to _valid data after the internal read pointer catches up to the assure that the first write and/or first read following areset write pointer - and passes it, if reading is continued. operation will occur predictably. Figure 11 illustrates how such an interiock may be imple- Ifno read operations have been performed followingaa «ented by means of external connections. reset operation, then the ‘previous data’ word being held When an empty condition is reached, shift operations in the output register and seen on the output bus (Qo- may continue; but read operations should be ceased, until Qs) consists of all zeroes. a valid write operation(s) has loaded additional data into the FIFO. Following the first write to an empty FIFO, the Write Empty Flag will be deasserted (EF = HIGH). The firstread ‘Awrite operation consists of storing parallel data from operation should begin no earlier than a First Read the data inputs to the FIFO memory array. Awrite opera- Latency time (ten) from the first write to an empty FIFO, tion is initiated on the rising edge of the Write Clock input in order to ensure that correct read data is retrieved. (WCK), whenever bath of the edge-sampled Write Enable inputs (WEN; and WENz) are held HIGH for the pre- ‘Status Flags _ scribed setup times and hold times. Setup times and hold The following four status flags are included: Full FF), times must also be observed for the Data In inputs _Half-Full (HF), Almost-Empty/Full (AEF), and Empty (EF). (Do = De). These flags are updated at the boundary conditions given , , , in Table 1 (page 5-104). Flag transitions follow the appro- When a full condition is reached, write operaions ee en ei a erabiod read or ate should be ceased, in order to prevent overwriting unread ck e¢ data. The state ofthe status fags has no direct eftect on Operation. The AEF fag 's asserted whenever the FIFO write operations; that is, the execution of write operations ee . ee ie than wight locations aera omy is gated only by WEN; and WENa, and the internal logic anll boonay se Is less than eig y of the LH5493 itself has no interlock to prevent overrun- iy ning valid data after the internal write pointer ‘wraps A separate indicator for Almost-Empty may be gener- around’ and catches up to the read pointer— and passes ated by a logical NOR of AEF with the inversion of HF. it ifwriting is continued. Figure 11 illustrates how such an _An indicator for Aimost-Full may be generated by a NOR interlock may be implemented by means of external _of AEF with HF. Froman assertive-HIGH perspective, the connections. NOR gate effectively is performing an AND operation in Following the first read operation from a full FIFO, Poth of these cases. another mem locaton feedup, andthe Fulllagis Reset, Reread deasserted (FF = HIGH). The first write operation shou! a begin no earlier than a First Write Latency (trw.) after the The FIFO may be made to reread previously-read data full FIFO, in order to ensure by means ofa reset operation, which initializes the Inter. fst read operation from a tue nal read and write address pointers to the first physical that the write operation is successful. location in the FIFO memory (location zero). The status Read flags are updated to indicate an empty condition; but up Aread operation consists of loading parallel data from [0 #086 words of olé dala, which previously Nad been the FIFO memory array to the output register. A read written into and/or read from the ), Still remain in the operations initiated on the rising edge of the Read Clock e™ory array. The status flags may be ignored, and data ‘ may be reaccessed by subsequent read operations. The input (RCK), whenever both the edge-sampled Read 7 ' Enable input (REN) and the Load/Shift input (LD/SH) are _-‘FrifSt Read Latency (trAt) specification does not apply to t ‘ reset/reread operations, since no new data words are held HIGH for the prescribed setup times and hold times being written to the FIFO following the reset operation. Read data becomes valid at the Data Out outputs . SHARP 5-99
LH5493 AK x 9 Parallel-to-Serial FIFO TIMING DIAGRAMS two, 7 q tos tow oP. XXXXXXXXI ome, % C8 OXXXXXXXXXXXXXKXXKK # Lb Nk tne | " a in Qp- 5 PREVIOUS DATA 1, CK uw N2 NOTES: 1. Both WEN, and WEN, must be asserted (HIGH) to enable write operations, 2. Both REN and LO/SH must be asserted (HIGH) to enable read operations. 3. EF being asserted (LOW) does not prevent further read operations, unless it is tied to REN. 4. tent (First Read Latency) - The first read following an empty condition may begin no earlier than ten after the first write to an empty FIFO, in order to ensure that valid data is retrieved. This specification does not apply to resetreread applications, in which the status of FIFO flags is ignored. Figure 4, Write and Read Operation in a Near-Empty Condition a 5-100 SHARP
4K x9 Parallel-to-Serial FIFO LH5493 TIMING DIAGRAMS (cont'd) Wen uh IN tos ton PO XXXXXXXXXXXXXXXXA __ | ORK ORXXXXXKXXKX tem. P| tee yy INN RCK ten tes rs Re ik KK te Oo OK KY NOTES: 1, Both WEN, and WENg | must be asserted (HIGH) to enable write operations. 2. Both REN and LO/SH must be asserted (HIGH) to enable read operations. 3. FF being asserted (LOW) does not prevent further write operations, unless it is ted either to WEN, of to WEN>. 4. tewt (First Write Latency) - The first write following a full condition may begin no earlier than tay, after the first read from a fuil FIFO, in order to ensure that valid read data is retrieved. s403.5| Figure 5, Write and Read Operation ina Near-Full Condition SHARP 5-101
Figure 6. Serial ShiftRead Timing
Figure 7. Reset Timing ~
- HF is HIGH whenever the FIFO is almost-empty, since then it also is less than half-full.
- An Almost- Empty flag AE may be implemented, using external logic according to AE = AEF . HF = AEF + HF. el
Figure 8. Almost-Empty Flag Timing Table 1. Flag Definitions
125 Mt N
Figure 9. Half-Full Flag Timing
- An Aimost-Full flag AF may be implemented, using external logic according to AF = AEF -HF = AEF + HF. sss
Figure 10. Almost-Full Flag Timing
Figure 11. Synchronous Operation
Write operations and read operations may be per- timing violations. times and hold times aremaintained. the FIFO becomes _ tained. Figure 12. Asychronous Operation
LOW or HIGH signal if unused. The SI input of each _ each LH5493 has just one read enable input. and WENe, and the readenable input REN, may bemade —_ main ‘Serial Data Out output. Sl ACK = REN LDSH Q Sl ACK REN LDSH —Qy . Figure 13. Paralleled Serial Operation (4096 x 18 Bit)
4K x9 Parallel-to-Serial FIFO LH5493
ORDERING INFORMATION
LH5493 u “4 Device Type Package Speed L__{g9 Cycle Time (ns) 32-pin Plastic Leaded Chip Carrier (PLOC32-P-R450) 4K x9 Parallel-to-Serial FIFO Example: LH5493U-25 (4K x 9 Parallel-to-Serial FIFO, 32-pin PLCC, 25 ns) somo SHARP 5-109