LH5481 SHARP | Alldatasheet
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Technical content
Figure 3. LH5481/91 Block Diagram
ABSOLUTE MAXIMUM RATINGS 1,2 PARAMETER RA TING Vcc Range –0.5 V to 7 V Input Voltage Range –0.5 V to Vcc + 0.5 V (not to exceed 7 V) DC Output Current 3 ±40 mA Storage Temperature –65 oC to 150oC DC Voltage Applied To Outputs In High-Z state –0.5 V to Vcc + 0.5 V (not to exceed 7 V) Static Discharge Voltage 4 > 2000 V Power Dissipation (Package Limit) 1.0 W NOTES: 1. All voltages are measured with respect to Vss. 2. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 4. Sample tested only. OPERATING RANGE 1 PARAMETER DESCRIPTION MIN MAX UNIT TA T emperature, Ambient 0.0 70 oC VCC Supply Voltage 4.5 5.5 V Vss Ground 0.0 0.0 V VIL Input Low Voltage (Logic ‘0’) 2 – 0.5 0.8 V VIH Input High Voltage (Logic ‘1’) 2.0 Vcc + 0.5 V NOTES: 1. All voltages are measured with respect to Vss. 2. FIFO inputs are able to withstand a –1.5 V undershoot for less than 10 ns per cycle. DC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range Unless Otherwise Noted) PARAMETER DESCRIPTION TEST CON DITIONS MIN MAX UNIT ILI Input Leakage Current V CC = 5.5 V, VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current (High-Z) VCC = 5.5 V, VOUT = 0 V to VCC –10 10 µA VOH Output High Voltage V CC = 4.5 V, IOH = –4 mA 2.4 V VOL Output Low Voltage V CC = 4.5 V, IOL = 8.0 mA 0.4 V ICCQ Power Supply Quiescent CurrentV CC = 5.5 V, IOUT = 0 mA V IN ≤ VIL, VIN ≥ VIH 25 mA ICC Power Supply Current 2 fsi = 35 MHz, fso = 35 MHz 45 mA NOTES: 1. All voltages are measured with respect to Vss. 2. Icc is dependent upon actual output loading and cycle rates. Specified values are with outputs open. 64 × 8 / 64 × 9 FIFO LH5481/91
AC ELECTRICAL C HARACT ERISTICS 1 (Over Operating Range) SYMBOL PARAMETER 15MHz 25MHz 35MHz UNITS MIN MAX MIN MAX MIN MAX fO Operating Frequency 2 15 25 35 MHz tPHSI SI HIGH Time 3,8 15 11 9 ns tPLSI SI LOW Time 3,8 20 18 17 ns tSSI Data Setup to SI 4 –1 –1 –1 ns tHSI Data Hold from SI 4 14 12 10 ns tDLIR Delay, SI HIGH to IR LOW 20 18 16 ns tDHIR Delay, SI LOW to IR HIGH 24 20 18 ns tPHSO SO HIGH Time 3 15 11 9 ns tPLSO SO LOW Time 3 20 18 17 ns tDLOR Delay, SO HIGH to OR LOW 20 18 16 ns tDHOR Delay, SO LOW to OR HIGH 24 20 18 ns tSOR Data Setup to OR HIGH –1 –1 –1 ns tHSO Data Hold from SO LOW 0 0 0 ns tFT Fallthrough Time 36 34 30 ns tBT Bubblethrough Time 28 26 25 ns tSIR Data Setup to IR 5 555 n s tHIR Data Hold from IR 5 555 n s tPIR Input Ready Pulse HIGH 8 777 n s tPOR Output Ready Pulse HIGH 8 777 n s tDLZOE OE LOW to LOW Z (LH5481) 6,9 35 30 25 ns tDHZOE OE HIGH to HIGH Z (LH5481) 6,9 35 30 25 ns tDHHF SI LOW to HF HIGH 40 40 36 ns tDLHF SO LOW to HF LOW 40 40 36 ns tDLAFE SO or SI LOW to AFE LOW 40 40 36 ns tDHAFE SO or SI LOW to AFE HIGH 40 40 36 ns tPMR MR Pulse Width 35 35 35 ns tDSI MR HIGH to SI HIGH 25 25 22 ns tDOR MR LOW to OR LOW 7 25 25 20 ns tDIR MR LOW to IR HIGH 7 25 25 20 ns tLXMR MR LOW to Output LOW 7 25 25 20 ns tAFE MR LOW to AFE HIGH 30 30 30 ns tHF MR LOW to HF LOW 30 30 30 ns tOD SO LOW to Next Data Out Valid 26 22 20 ns NOTES: 1. All time measurements performed at ‘AC Test Conditions.’ 2. fO = fSI = fSO . 3. tPHSI + tPLSI = tPHSO + tPLSO = I/fO . 4t SSI and tHSI apply when memory is not full. 5. tSIR and tHIR apply when memory is full and SI is HIGH. 6. High-Z transitions are referenced to the steady-state VOH – 500 mV and VOL + 500 mV levels on the output. 7. After reset goes LOW, all Data outputs will be at LOW level, IR goes HIGH and OR goes LOW. 8. Common dash number devices are guaranteed by design to function properly in a cascaded configuration. 64 × 8 / 64 × 9 FIFO LH5481/91
Unlike earlier versions of FIFOs, the LH5481 and LH5491 use dual-port Random-Access-Memory, write and read pointers, and special control logic. The write pointer is incremented by the falling edge of the Shift In (SI) signal, while the read pointer is incremented by the falling edge of the Shift Out (SO) signal. The Input Ready (IR) signal enables data writing to the FIFO. The Output Ready (OR) signal indicates valid read information is available on the Data Output (DO) pins. Resetting The FIFO The FIFO must be reset, upon power-up, using the Master Reset ( MR) signal. This causes the FIFO to enter an empty state, indicated by the Output Ready (OR) being LOW and Input Ready (IR) being HIGH. All Data Output (DO) pins will be LOW in this state. The AFE flag will be HIGH, and the HF flag will be LOW. If Shift In (SI) is HIGH, when the Master Reset ( MR) signal is ended, then the data on the Data Input (DI) pins will be written into the FIFO, and Input Ready (IR) will return LOW until Shift In (SI) is brought LOW. If Shift In (SI) is LOW when the Master Reset (MR) is deasserted, then Input Ready (IR) goes HIGH, but the data on the Data Input (DI) pins does not enter the FIFO until Shift In (SI) goes HIGH. Shifting Data In Data Input (DI) is shifted into the FIFO on the rising edge of Shift In (SI). This loads input data into the FIFO, and causes Input Ready (IR) to go LOW. When a falling edge of Shift In (SI) occurs,the write pointer increments to the next word position, and Input Ready (IR) goes HIGH, indicating that the FIFO is ready to accept new data. When the FIFO is full, Input Ready (IR) remains LOW after the negative edge of Shift In (SI) signal; Shift Out (SO) action is required to unload a word of data and bring Input Ready (IR) HIGH. (See ‘Bubblethrough Con- dition’ description.) Shifting Data Out Data is shifted out of the FIFO on the falling edge of Shift Out (SO). The read pointer increments to the next word location; FIFO data, if present, appears on the Data Output (DO) pins; and the Output Ready (OR) signal goes HIGH. If FIFO data is not present, Output Ready (OR) stays LOW, indicating that the FIFO is empty; in this case, the last valid data read from the FIFO remains on the Data Output (DO) pins. When the FIFO is not empty, Output Ready (OR) goes LOW after the rising edge of Shift Out (SO). The previous data remains on the Data Output (DO) pins until a falling edge of Shift Out (SO). Fallthrough Condition When the FIFO is empty, a data word entering through the Shift In (SI) action follows one of two sequences. If Shift Out (SO) is LOW, the data propagates to the Data Output (DO) pins; and Output Ready (OR) goes HIGH and stays HIGH until the next rising edge of Shift Out (SO). If Shift Out (SO) is held HIGH while data is shifted into an empty FIFO as occurs in depth cascading of FIFOs, data propagates to the Data Output (DO) pins, and Output Ready (OR) pulses HIGH for a minimum time duration specified by t POR and then goes back LOW again. The stored word remains on the Data Output (DO) pins. If more words are written into the FIFO, they line up behind the first word, and do not appear on the Data Output (DO) pins until Shift Out (SO) has returned LOW. Bubblethrough Condition When the FIFO is full, Shift Out (SO) action initiates one of the following two sequences: If Shift In (SI) is LOW, Input Ready (IR) goes HIGH and stays HIGH until the next rising edge of Shift In (SI). If Shift In (SI) is held HIGH while data is shifted out of a full FIFO, as occurs in depth cascading of FIFOs, Input Ready (IR) pulses HIGH for a minimum time duration specified by t PIR, and then goes back LOW again. Special Data Input (DI) setup and hold times (tSIR and tHIR, respectively) are defined for this condition. LH5481/91 64 × 8 / 64 × 9 FIFO
Figure 13. Master Reset Timing
Figure 16. 320 × 24/27 Configuration
erate composite Input Ready and Output Ready flags. are needed by the external system.
- When the memory is empty, the last word read remains on the out-
that the data word at the output is not valid.
- When the output data word changes as a result of a pulse on SO,
- All SHARP FIFOs can be cascaded with other SHARP FIFOs of
they may not cascade with FIFOs from other manufacturers. Figure 17. 128 × 8/9 Configuration
28SK-DIP (DIP028-P-0300) DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 11 4 1528 28DIP-1 7.05 [0.278] 6.65 [0.262] 0.51 [0.020] MIN. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.56 [0.022] 0.36 [0.014] 0.35 [0.014] 0.15 [0.006] DETAIL 35.00 [1.378] 34.40 [1.354] 0° TO 15° 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 28-pin, 300-mil PDIP 28PLCC MAXIMUM LIMIT MINIMUM LIMITDIMENSIONS IN MM [INCHES] 28PLCC (PLCC28-P-S450) 1.27 [0.050] BASIC NON-ACCUM 12.57 [0.495] 12.32 [0.485] 0.10 [0.004] 1.22 [0.048] 1.07 [0.042] x 45° 12.57 [0.495] 12.32 [0.485] 0.51 [0.020] MIN. 10.92 [0.430] 9.91 [0.390] DETAIL 11.56 [0.455] 11.43 [0.450] 11.56 [0.455] 11.43 [0.450] 0.81 [0.032] 0.66 [0.026] 2.79 [0.110] 2.52 [0.099] 0.53 [0.021] 0.33 [0.013] 4.57 [0.180] 4.19 [0.165] 28-pin, 450-mil PLCC 64 × 8 / 64 × 9 FIFO LH5481/91
ORDERING INFORMATION
LH#### Device Type X Package - ## Speed Examples: LH5481D-25 (64 x 8 FIFO, 28-pin, 300-mil PDIP, 25 MHz) LH5491U-35 (64 x 9 FIFO, 28-pin PLCC, 35 MHz) 5481MD D 28-pin, 300-mil PDIP (DIP028-P-0300) U 28-pin Plastic Leaded Chip Carrier (PLCC28-P-S450) 5481 64 x 8 FIFO 5491 64 x 9 FIFO
25 Frequency (MHz)
LH5481/91 64 × 8 / 64 × 9 FIFO