LH543601 SHARP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 43
Technical content
LH543601 256 × 36 × 2 Bidirectional FIFO
FEATURES
- Fast Cycle Times: 20/25/30/35 ns
- Pin-Compatible and Functionally-Compatible 0.7µ-Technology Replacement for Sharp LH5420
- Two 256 × 36-bit FIFO Buffers
- Full 36-bit Word Width
- Selectable 36/18/9-bit Word Width on Port B
- Independently-Synchronized (‘Fully-Asynchronous’) Operation of Port A and Port B
- ‘Synchronous’ Enable-Plus-Clock Control at Both Ports
- R/W, Enable, Request, and Address Control Inputs are Sampled on the Rising Clock Edge
- Synchronous Request/Acknowledge ‘Handshake’ Capability; Use is Optional
- Device Comes Up Into a Known Default State at Reset; Programming is Allowed, but is not Required
- Asynchronous Output Enables
- Five Status Flags per Port: Full, Almost-Full, Half-Full, Almost-Empty, and Empty
- Almost-Full Flag and Almost-Empty Flag are Programmable
- Mailbox Registers with Synchronized Flags
- Data-Bypass Function
- Data-Retransmit Function
- Automatic Byte Parity Checking
- 8 mA-IOL High-Drive Three-State Outputs with Built-In Series Resistor
- TTL/CMOS-Compatible I/O
- Space-Saving PQFP and TQFP Packages
- PQFP to PGA Package Conversion 1 FUNCTIONAL DESCRIPTION The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and FIFO #2 each are organized as 256 by 36 bits. The LH543601 is ideal either for wide unidirectional applica- tions or for bidirectional data applications; component count and board area are reduced. The LH543601 has two 36-bit ports, Port A and Port B. Each port has its own port-synchronous clock, but the two ports may operate asynchronously relative to each other. Data flow is initiated at a port by the rising edge of the appropriate clock; it is gated by the corresponding edge- sampled enable, request, and read/write control signals. At the maximum operating frequency, the clock duty cycle may vary from 40% to 60%. At lower frequencies, the clock waveform may be quite asymmetric, as long as the minimum pulse-width conditions for clock-HIGH and clock-LOW remain satisfied; the LH543601 is a fully-static part. Conceptually, the port clocks CK A and CKB are free- running, periodic ‘clock’ waveforms, used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that these ‘clock’ wave- forms must be periodic. An ‘asynchronous’ mode of operation is possible, in one or both directions, inde- pendently, if the appropriate enable and request inputs are continuously asserted, and enough aperiodic ‘clock’ pulses of suitable duration are generated by external logic to cause all necessary actions to occur. A synchronous request/acknowledge handshake facility is provided at each port for FIFO data access. This request/ acknowledge handshake resolves FIFO full and empty boundary conditions, when the two ports are op- erated asynchronously relative to each other. FIFO status flags monitor the extent to which each FIFO buffer has been filled. Full, Almost-Full, Half-Full, Almost-Empty, and Empty flags are included for each FIFO. The Almost-Full and Almost-Empty flags are pro- grammable over the entire FIFO depth, but are automat- ically initialized to eight locations from the respective FIFO boundaries at reset. A data block of 256 or fewer words may be retransmitted any desired number of times. NOTE: 1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp recommends ITT Pomona Electronics’ SMT/PGA Generic Converter model #5853.® This converter maps the LH543601 132-pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil pitch). For more information, contact Sharp or ITT Pomona Electronics at 1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.
passing control words or status words between ports. between asynchronous systems. peripheral device on Port B, during system startup. back again to odd parity, as desired. Figure 1. Pin Connections for 132-Pin PQFP Package
Figure 2. Pin Connections for 144-Pin TQFP Package
PIN NO. TQFP PIN NO. A0A 1 126 A1A 2 125 A2A 3 124 OE A 4 123 FF1 6 121 AF1 7 120 HF 1 8 119 PFA 9 118 D17A 10 117 D16A 11 116 D15A 12 115 D14A 14 113 D13A 15 112 D12A 16 111 D11A 17 110 D10A 19 106 D9A 20 105 D8A 21 104 D7A 23 102 D6A 24 101 D5A 25 100 D4A 27 98 D3A 28 97 D2A 29 96 D1A 31 94 D0A 32 93 RS 33 92 RT 1 34 91 D0B 35 89 D1B 36 88 D2B 37 87 D3B 39 85 D4B 40 84 D5B 41 83 D6B 43 81 D7B 44 80 D8B 45 79 D9B 47 77 D10B 48 76 D11B 49 75 D12B 51 71 D13B 52 70 D14B 53 69 D15B 54 68 SIGNAL NAME PQFP PIN NO. TQFP PIN NO. D 16B 56 66 D 17B 57 65 MBF 1 58 64 AE 1 59 63 EF 1 60 62 ACK B 61 61 REQ B 63 59 EN B 64 58 R/W B 65 57 CK B 66 56 A0B 67 55 WS 0 68 53 WS 1 69 52 OE B 70 51 FF2 72 49 AF 2 73 48 HF 2 74 47 PF B 75 46 D 18B 76 45 D 19B 77 44 D 20B 78 43 D 21B 80 41 D 22B 81 40 D 23B 82 39 D 24B 83 38 D 25B 85 34 D 26B 86 33 D 27B 87 32 D 28B 89 30 D 29B 90 29 D 30B 91 28 D 31B 93 26 D 32B 94 25 D 33B 95 24 D 34B 97 22 D 35B 98 21 RT 2 100 18 D 35A 101 17 D 34A 102 16 D 33A 103 15 D 32A 105 13 D 31A 106 12 D 30A 107 11 D 29A 109 9 SIGNAL NAME PQFP PIN NO. TQFP PIN NO. D 28A 110 8 D 27A 111 7 D 26A 113 5 D 25A 114 4 D 24A 115 3 D 23A 117 143 D 22A 118 142 D 21A 119 141 D 20A 120 140 D 19A 122 138 D 18A 123 137 MBF 2 124 136 AE 2 125 135 EF 2 126 134 ACK A 127 133 REQ A 129 131 EN A 130 130 R/W A 131 129 CK A 132 128 VCC 5 122 VSSO 13 114 NC 109 NC 108 V CCO 18 107 VSSO 22 103 VCCO 26 99 VSSO 30 95 NC 90 V SSO 38 86 VCCO 42 82 VSSO 46 78 VCCO 50 74 NC 73 NC 72 VSSO 55 67 VSS 62 60 NC 54 V CC 71 50 VSSO 79 42 NC 37 NC 36 V CCO 84 35 VSSO 88 31 VCCO 92 27 NOTE: PINS COMMENTS VCC Supply internal logic. Connected to each other. VCCO Supply output drivers only. Connected to each other. PINS COMMENTS VSS Supply internal logic. Connected to each other. VSSO Supply output drivers only. Connected to each other. LH543601 256 × 36 × 2 Bidirectional FIFO
PIN PIN TYPE 1 DESCRIPTION GENERAL VCC , VSS V Power, Ground RS I Reset PORT A CK A I Port A Free-Running Clock R/W A I Port A Edge-Sampled Read/Write Control EN A I Port A Edge-Sampled Enable A0A, A1A, A2A I Port A Edge-Sampled Address Pins OE A I Port A Level-Sensitive Output Enable REQ A I Port A Request/Enable RT 2 I FIFO #2 Retransmit D 0A – D35A I/O/Z Port A Bidirectional Data Bus FF1 O FIFO #1 Full Flag (Write Boundary) AF1 O FIFO #1 Programmable Almost-Full Flag (Write Boundary) HF 1 O FIFO #1 Half-Full Flag AE 2 O FIFO #2 Programmable Almost-Empty Flag (Read Boundary) EF2 O FIFO #2 Empty Flag (Read Boundary) MBF 2 O New-Mail-Alert Flag for Mailbox #2 PFA O Port A Parity Flag ACK A O Port A Acknowledge PORT B CK B I Port B Free-Running Clock R/W B I Port B Edge-Sampled Read/Write Control EN B I Port B Edge-Sampled Enable A0B I Port B Edge-Sampled Address Pin OE B I Port B Level-Sensitive Output Enable WS 0, WS1 I Port B Word-Width Select REQ B I Port B Request/Enable RT 1 I FIFO #1 Retransmit D 0B – D35B I/O/Z Port B Bidirectional Data Bus FF2 O FIFO #2 Full Flag (Write Boundary) AF2 O FIFO #2 Programmable Almost-Full Flag (Write Boundary) HF 2 O FIFO #2 Half-Full Flag AE 1 O FIFO #1 Programmable Almost-Empty Flag (Read Boundary) EF1 O FIFO #1 Empty Flag (Read Boundary) MBF 1 O New-Mail-Alert Flag for Mailbox #1 PFB O Port B Parity Flag ACK B O Port B Acknowledge NOTE: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level LH543601 256 × 36 × 2 Bidirectional FIFO
- Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause
permanent damage to the device. This is a stress rating for transient conditions only. rating conditions for extended periods may affect reliability.
- Outputs should not be shorted for more than 30 seconds. No more than one output should be
- Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
- Negative undershoot of 1.5 V in amplitude is permitted
for up to 10 ns, once per cycle.
- ICC , ICC2 , ICC 3, and ICC4 are dependent upon actual output loading, and ICC and ICC4 are also dependent on cycle rates. Specified values are
with outputs open (for ICC : CL = 0 pF); and, for ICC and ICC4 , operating at minimum cycle times.
- ICC2 (TYP .) and ICC 4 (TYP .) using VCC = 5 V and TA = 25°C.
Figure 4. Structure of Series Resistor
- Capacitances are maximum values at 25oC, measured at 1.0MHz,
Figure 5. Output Load Circuit
AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± 10%, TA = 0°C to 70°C) SYMBOL DECRIPTION –20 –25 –30 –35 UNITS MIN MAX MIN MAX MIN MAX MIN MAX fCC Clock Cycle Frequency — 50 — 40 — 33 — 28.5 MHz tCC Clock Cycle Time 20 — 25 — 30 — 35 — ns tCH Clock HIGH Time 8 — 10 — 12 — 15 — ns tCL Clock LOW Time 8 — 10 — 12 — 15 — ns tDS Data Setup Time 10 — 12 — 13 — 15 — ns tDH D a t a H o l d T i m e 0—0—0—0— n s tES Enable Setup Time 10.4 — 13 — 15 — 15 — ns tEH Enable Hold Time 0—0—0—0— n s tRWS Read/Write Setup Time 10.4 — 13 — 15 — 18 — ns tRWH Read/Write Hold Time 0—0—0—0— n s tRQS Request Setup Time 12 — 15 — 18 — 21 — ns tRQH Request Hold Time 0—0—0—0— n s tAS Address Setup Time 6 1 2—1 5—1 8—2 1—n s tAH Address Hold Time 6 0—0—0—0— n s tA Data Output Access Time — 12.8 — 16 — 20 — 25 ns tACK Acknowledge Access Time — 12 — 15 — 20 — 25 ns tOH Output Hold Time 2.0 — 2.0 — 2.0 — 2.0 — ns tZX Output Enable Time, OE LOW to D0 – D35 Low-Z 2 1.5 — 2.0 — 3.0 — 3.0 — ns tXZ Output Disable Time, OE HIGH to D 0 – D35 High-Z 2 — 9 —1 2—1 5—2 0n s tEF Clock to EF Flag Valid (Empty Flag) — 17.6 — 22 — 25 — 30 ns tFF Clock to FF Flag Valid (Full Flag) — 17.6 — 22 — 25 — 30 ns tHF Clock to HF Flag Valid (Half-Full) — 17.6 — 22 — 25 — 30 ns tAE Clock to AE Flag Valid (Almost- Empty) —1 6—2 0—2 5—3 0n s tAF Clock to AF Flag Valid (Almost-Full) — 16 — 20 — 25 — 30 ns tMBF Clock to MBF Flag Valid (Mailbox Flag) —1 2—1 5—2 0—2 5n s tPF Data to Parity Flag Valid — 13.6 — 17 — 20 — 25 ns tRS Reset/Retransmit Pulse Width 7 32/20 — 40/25 — 52/30 — 65/35 — ns tRSS Reset/Retransmit Setup Time 3 1 6—2 0—2 5—3 0—n s tRSH Reset/Retransmit Hold Time 3 8 —1 0—1 5—2 0—n s tRF Reset LOW to Flag Valid — 28 — 35 — 40 — 45 ns tFRL First Read Latency 4 2 0—2 5—3 0—3 5—n s tFWL First Write Latency 5 2 0—2 5—3 0—3 5—n s tBS Bypass Data Setup 12 — 15 — 18 — 21 — ns tBH Bypass Data Hold 3—5—5—5— n s tBA Bypass Data Access — 18 — 20 — 25 — 30 ns NOTES: 1. Timing measurements performed at ‘AC Test Condition’ levels. 2. Values are guaranteed by design; not currently production tested. 3. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while EN B is being asserted. 4. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data. 5. tFWL is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data. 256 × 36 × 2 Bidirectional FIFO LH543601
of a full condition, for FIFO #1/FIFO #2 respectively. operation means passing data from Port B to Port A. essor and a peripheral device during reset. Port A writes to FIFO #1, and Port B writes to FIFO #2. full FIFO, to ensure that correct read data are retrieved. Table 1. Resource-Register Addresses
becomes valid on the data-bus pins (D0A – D35A or D 0B – D35B) by a time tA after the rising clock (CKA or CK B) edge, provided that the data outputs are enabled. OE A and OE B are assertive-LOW, asynchronous, Out- put Enable control input signals. Their effect is only to enable or disable the output drivers of the respective port. Disabling the outputs does not disable a read operation; data transmitted to the corresponding output register will remain available later, when the outputs again are en- abled, unless it subsequently is overwritten. When an empty condition is reached, read operations are locked out until a valid write operation(s) has loaded additional data into the FIFO. Following the first write to an empty FIFO, the corresponding empty flag (EF) will be deasserted (HIGH). The first read operation should begin no earlier than a First Read Latency (tFRL ) after the first write to an empty FIFO, to ensure that correct read data words are retrieved. Dedicated FIFO Status Flags Six dedicated FIFO status flags are included for Full FF1 and FF2), Half-Full (HF 1 and HF 2), and Empty (EF1 and EF2). FF1, HF 1, and EF1 indicate the status of FIFO #1; and FF2, HF 2, and EF2 indicate the status of FIFO #2. A Full Flag is asserted following the first subsequent rising clock edge for a write operation which fills the FIFO. A Full Flag is deasserted following the first subsequent falling clock edge for a read operation to a full FIFO. A Half-Full Flag is updated following the first subsequent rising clock edge of a read or write operation to a FIFO which changes its ‘half-full’ status. An Empty Flag is asserted following the first subsequent rising clock edge for a read operation which empties the FIFO. An Empty Flag is deasserted following the falling clock edge for a write operation to an empty FIFO. Programmable Status Flags Four programmable FIFO status flags are provided, two for Almost-Full ( AF1 and AF2), and two for Almost- Empty (AE 1 and AE 2). Thus, each port has two program- mable flags to monitor the status of the two internal FIFO buffer memories. The offset values for these flags are initialized to eight locations from the respective FIFO boundaries during reset, but can be reprogrammed over the entire FIFO depth. An Almost-Full Flag is asserted following the first sub- sequent rising clock edge after a write operation which has partially filled the FIFO up to the ‘almost-full’ offset point. An Almost-Full Flag is deasserted following the first subsequent falling clock edge after a read operation which has partially emptied the FIFO down past the ‘almost-full’ offset point. An Almost-Empty Flag is as- serted following the first subsequent rising clock edge after a read operation which has partially emptied the FIFO down to the ‘almost-empty’ offset point. An Almost- Empty Flag is deasserted following the first subsequent falling clock edge after a write operation which has par- tially filled the FIFO up past the ‘almost-empty’ offset point. Flag offsets may be written or read through the Port A data bus. All four programmable FIFO status flag offsets can be set simultaneously through a single 36-bit status word; or, each programmable flag offset can be set individually, through one of four eight-bit status words. T able 3 illustrates the data format for flag-programming words . Also, Table 4 defines the meaning of each of the five flags, both the dedicated flags and the programmable flags, for the LH543601. WARNING: Control inputs which may affect the compu- tation of flag values at a port generally should not change while the clock for that port is HIGH, since some updating of flag values takes place on the falling edge of the clock. Mailbox Operation Two mailbox registers are provided for passing system hardware or software control/status words between ports. Each port can read its own mailbox and write to the other port’s mailbox. Mailbox access is performed on the rising edge of the controlling FIFO’s clock, with the mailbox address selected and the enable (EN A or ENB) HIGH. That is, writing to Mailbox Register #1, or reading from Mailbox Register #2, is synchronized to CK A; and writing to Mailbox Register #2, or reading from Mailbox Register #1, is synchronized to CK The R/W A/B and OE A/B pins control the direction and availability of mailbox-register accesses. Each mailbox register has its own New-Mail-Alert Flag ( MBF 1 and MBF 2), which is synchronized to the reading port’s clock. These New-Mail-Alert Flags are status indicators only, and cannot inhibit mailbox-register read or write operations. Request Acknowledge Handshake A synchronous request-acknowledge handshake fea- ture is provided for each port, to perform boundary syn- chronization between asynchronously-operated ports. The use of this feature is optional. When it is used, the Request input (REQ A/B) is sampled at a rising clock edge. With REQA/B HIGH, R/W A/B determines whether a FIFO read operation or a FIFO write operation is being re- quested. The Acknowledge output (ACK A/B) is updated during the following clock cycle(s). ACKA/B meets the setup and hold time requirements of the Enable input (ENA or ENB). Therefore, ACKA/B may be tied back to the enable input to directly gate FIFO accesses, at a slight decrease in maximum operating frequency. The assertion of ACKA/B signifies that REQA/B was asserted. However, ACKA/B does not depend logically on EN A/B; and thus the assertion of ACKA/B does not prove that a FIFO write access or a FIFO read access actually took place. While REQA/B and ENA/B are being held HIGH, ACKA/B may be considered as a synchronous, predictive boundary flag. That is, ACKA/B acts as a syn- OPERATIONAL DESCRIPTION (cont’d) 256 × 36 × 2 Bidirectional FIFO LH543601
Empty Flag AE for read operations. tions are satisfied before ACKA/B is received. asserted in response to REQA/B. been written into and read from a FIFO, can be retrieved. mit signal is being asserted. ister bit 00 (zero) selects the parity mode, odd or even. access which forms a complete 36-bit transfer. plete 36-bit words, and not in terms of bytes or double bytes. only after a full 36-bit-word access. operate properly in ‘loopback’ mode. Table 2. Port B Word-Width Selection
Table 3. Resource-Register Programming
- All four programmable-flag-offset values are initialized to eight (8) during a reset operation.
- Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.
Table 4. Flag Definition Table 1
- q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)
- p = Programmable-Almost-Full Offset value. (Default value: p = 8.)
- RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates
RS is being asserted (is LOW), with timing as defined by tRSS and tRSH .
- Otherwise, tRSS , tRSH need not be met unless the rising edge of CKA and/or CKB
occurs while that clock is enabled.
- The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
- The AE and AF flag offsets are initialized to eight locations from the boundary at reset.
Figure 8. Reset Timing
- tRSS , tRSH need not be met unless the rising edge of CKA or CKB occurs while that clock is enabled.
- Port A is considered the master port for bypass operation. Thus, CKA, R/WA, ENA, and REQA control
the transmission of data between ports at reset. Figure 9. Data Bypass Timing
- The Port A Parity Error Flag (PFA) reflects the parity status of data present on the data bus.
- The status of OEA does not gate read or write operations.
- If OEA is left LOW during a write operation, then the previous data held in the output latch is
Figure 10. Port A FIFO Read/Write
- The Port B Parity Error Flag (PFB) reflects the parity status of data present on the data bus.
- The status of OEB does not gate read or write operations.
- If OEB is left LOW during a write operation, then the previous data held in the output latch is
Figure 11. Port B FIFO Read/Write
- Both edges of MBF2 are synchronized to the Port A clock, CKA.
- Both edges of MBF1 are synchronized to the Port B clock, CKB.
- There is a maximum of two CKB clock cycles of synchronization latency before MBF1
is asserted to indicate valid new mailbox data.
- The status of mailbox flags does not prevent mailbox read or write operations.
Figure 12. Port A Mailbox Access
- Both edges of MBF2 are synchronized to the Port A clock, CKA.
- Both edges of MBF1 are synchronized to the Port B clock, CKB.
- There is a maximum of two CKA clock cycles of synchronization latency before MBF2
is asserted to indicate valid new mailbox data.
- The status of mailbox flags does not prevent mailbox read or write operations.
Figure 13. Port B Mailbox Access
- For valid flag address codes and data formats, see Table 3.
- If flag status is altered by flag programming, the updated flags will be valid within a time t
- The Control Register may be loaded as shown here, with A2A, A1A, A0A = HLL. However, it
is not available for reading back. Figure 14. Flag Programming
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
- Assertion of the Empty Flags is controlled by rising clock edges,
Figure 15. Empty Flag Timing
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
- Assertion of the Almost-Empty Flags is controlled by rising clock
Figure 16. Almost-Empty Flag Timing
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
- Assertion of the Full Flags is controlled by rising clock edges,
Figure 17. Full Flag Timing
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
- Assertion of the Almost-Full Flags is controlled by rising clock edges,
Figure 18. Almost-Full Flag Timing
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
- Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges. Figure 19. Half-Full Flag Timing
- tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
- tRSS is the time needed to deassert RT2 before returning to a normal FIFO cycle.
- tRSH is the time needed before asserting RT2 after a normal FIFO cycle.
- Read and write operations to FIFO #2 should be disabled while RT2 is being asserted.
Figure 20. FIFO #2 Retransmit
- tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
- tRSS is the time needed to deassert RT1 before returning to a normal FIFO cycle.
- tRSH is the time needed before asserting RT1 after a normal FIFO cycle.
- Read and write operations to FIFO #1 should be disabled while RT1 is being asserted.
Figure 21. FIFO #1 Retransmit
- A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
- tFRL (First Read Latency) - The first read following an empty condition
to ensure that valid read data is retrieved. Figure 22. FIFO #1 Write and Read Operation in
- A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
- tFRL (First Read Latency) - The first read following an empty condition
to ensure that valid read data is retrieved. Figure 23. FIFO #2 Write and Read Operation in
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- tFWL (First Write Latency) - The first write following a full condition
to ensure that valid write data is written. Figure 24. FIFO #1 Read and Write Operation in
- A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
- tFWL (First Write Latency) - The first write following a full condition
to ensure that valid write data is written. Figure 25. FIFO #2 Read and Write Operation in
- A0B is held HIGH for FIFO access.
- WS0 is held HIGH and WS1 is held LOW for double-byte access.
- Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles. Figure 26. Port B Double-Byte FIFO #1 Read Access for
- A0B is held HIGH for FIFO access.
- WS0 is held HIGH and WS1 is held LOW for double-byte access.
- Data-setup time tDS and data-hold time tDH , before and after
similarly for all subsequent write cycles. Figure 27. Port B Double-Byte FIFO #2 Write Access for
- A0B is held HIGH for FIFO access.
- WS0 and WS1 both are held LOW for single-byte access.
- Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles. Figure 28. Port B Single-Byte FIFO #1 Read Access for
- A0B is held HIGH for FIFO access.
- WS0 and WS1 both are held LOW for single-byte access.
- Data-setup time tDS and data-hold time tDH , before and after
similarly for all subsequent write cycles. Figure 29. Port B Single-Byte FIFO #2 Write Access for
- Indicates where a write would take place, if ACK were tied to EN.
- For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
- ACK can be tied directly to EN to directly gate FIFO accesses.
- REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
- When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
- Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
Figure 30. Write Request/Acknowledge Handshake
- Indicates where a read would take place, if ACK were tied to EN.
- For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
- ACK can be tied directly to EN to directly gate FIFO accesses.
- REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
- When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
- Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
Figure 31. Read Request/Acknowledge Handshake
132 PQFP
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 132PQFP (PQFP132-P-S950) 28.02 [1.103] 27.86 [1.097] 0.635 [0.025] TYP NON-ACCUM 4.57 [0.180] 4.06 [0.160] 0.51 [0.020] MIN. 24.21 [0.953] 24.05 [0.947] 28.02 [1.103] 27.86 [1.097] 27.69 [1.090] 27.18 [1.070] 27.69 [1.090] 27.18 [1.070] SECTION 0.10 [0.004] 0.25 [0.010] TYP. 0.51 [0.020] MIN. 0.15 [0.006] 0° - 8° 45° CHAMFER TOP VIEW 24.21 [0.953] 24.05 [0.947] 132-pin PQFP 256 × 36 × 2 Bidirectional FIFO LH543601
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 144TQFP (TQFP-144-P-2020) 0.50 [0.020] TYP. 0.20 [0.008] 0.09 [0.004] 20.0 [0.787] BASIC 144TQFP 1.45 [0.057] 1.35 [0.053] DETAIL 20.0 [0.787] BASIC 1.60 [0.063] REF. MAX 0.15 [0.006] 0.05 [0.002] 22.0 [0.866] BASIC 0.27 [0.010] 0.17 [0.007] 22.0 [0.866] BASIC 0.75 [0.030] 0.47 [0.019] 1.00 [0.039] REF. 144-pin TQFP LH543601 256 × 36 × 2 Bidirectional FIFO
ORDERING INFORMATION
Cycle Times (ns) M 144-Pin, Thin Quad Flat Package (TQFP144-P-2020) P 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950) LH543601 Device Type X Package - ## Speed 256 x 36 x 2 Bidirectional FIFO Example: LH543601P-20 (256 x 36 x 2 Bidirectional FIFO, 20 ns, 132-Lead, Plastic Quad Flat Package) 543601-37 256 × 36 × 2 Bidirectional FIFO LH543601