LH540225

LH540215 SHARP | Alldatasheet

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Technical content

LH540215/25 512 × 18 / 1024 × 18 Synchronous FIFO

FEATURES

• • Fast Cycle Times: 20/25/35 ns
• • Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs
• • Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal
• • Device Comes Up into One of Two Known Default States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required
• • Internal Memory Array Architecture Based on CMOS Dual-Port SRAM Technology, 512 × 18 or 1024 × 18
• • ‘Synchronous’ Enable-Plus-Clock Control at Both Input Port and Output Port
• • Independently-Synchronized Operation of Input Port and Output Port
• • Control Inputs Sampled on Rising Clock Edge
• • Most Control Signals Assertive-LOW for Noise Immunity
• • May be Cascaded for Increased Depth, or Paralleled for Increased Width
• • Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are Programmable
• • In Enhanced Operating Mode, Almost-Full, Half-Full, and Almost-Empty Flags can be Made Completely Synchronous
• • In Enhanced Operating Mode, Duplicate Enables for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected
• • In Enhanced Operating Mode, Disabling Three-State Outputs May be Made to Suppress Reading
• • Data Retransmit Function
• • TTL/CMOS-Compatible I/O
• • Space-Saving 68-Pin PLCC Package, and 64-Pin RESET LOGIC INPUT PORT RS INPUT PORT CONTROL LOGIC READ POINTER WRITE POINTER DEDICATED AND PROGRAMMABLE STATUS FLAGS FIFO MEMORY ARRAY 512 x 18/1024 x 18 OUTPUT PORT CONTROL LOGIC FF PAF WXO/HF RXO /EF2 PAE D 0 - D17 WEN WCK Q 0 - Q17 RCK OUTPUT PORT REN OE PROGRAMMABLE REGISTERS EXPANSION LOGIC WXI/WEN 2 FL/RT WXO/HF RXI/REN 2 RXO/ EF 2 LD 540215-1 WXI/WEN 2 RXI/REN 2 BOLD ITALIC = Enhanced Operating Mode. EMODE EF

Figure 1. LH540215/25 Block Diagram

NOTE: Throughout this data sheet, a BOLD ITALIC type font is used for all references to Enhanced Operating Mode features which do not function in IDT-Compatible Operating Mode; and also for all references to the re- transmit facility (which is not an IDT72215B/25B FIFO feature), even though it may be used – subject to some restrictions – in either of these two operating modes. Thus, readers interested only in using the LH540215/25 FIFOs in IDT-Compatible Operating Mode may skip over BOLD ITALIC sections, if they wish. The LH540215/25 parts are FIFO (First-In, First-Out) memory devices, based on fully-static CMOS dual-port SRAM technology, capable of containing up to 512 or 1024 18-bit words respectively. They can replace two or more byte-wide FIFOs in many applications, for microprocessor- to-microprocessor or microprocessor-to-bus communica- tion. Their architecture supports synchronous operation, tied to two independent free-running clocks at the input and output ports respectively. However, these ‘clocks’ also may be aperiodic, asynchronous ‘demand’ signals. Almost all control-input signals and status-output signals are synchro- nized to these clocks, to simplify system design. The input and output ports operate altogether inde- pendently of each other, unless the FIFO becomes either totally full or else totally empty. Data flow is initiated at a port by the rising edge of its corresponding clock, and is gated by the appropriate edge-sampled enable signals. The following FIFO status flags monitor the extent to which the internal memory has been filled: Full, Almost- Full, Half-Full, Almost-Empty, and Empty. The Almost-Full and Almost-Empty flag offsets are programmable over the entire FIFO depth; but, during a reset operation, each of these is initialized to a default offset value of 63 (LH540215) or 12710 (LH540225) FIFO-memory words, from the respective FIFO boundary. If this default offset value is satisfactory, no further programming is required. After a reset operation during which the EMODE control input was not asserted (was HIGH), these FIFOs operate in the IDT-Compatible Operating Mode. In this mode, each part is pin-compatible and functionally-compatible with the IDT72215B/25B part of similar depth and speed grade; and the Control Register is not even accessible or visible to the external-system logic which is controlling the FIFO, although it still performs the same control functions. However, assertion of the EMODE control input during a reset operation leaves Control Register bits 00-05 set, and causes the FIFO to operate in the Enhanced Operating Mode. In essence, asserting EMODE chooses a different default state for the Con- trol Register. The system optionally then may pro- gram the Control Register in any desired manner to activate or deactivate any or all of the Enhanced-Op- erating-Mode features which it can control, including selectable-clock-edge flag synchronization, and read inhibition when the data outputs are disabled. Whenever EMODE is being asserted, interlocked- operation paralleling also is available, by appropriate interconnection of the FIFO’s expansion inputs. The retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. (See T ables 1 and 2.) It is inoperative if the FL/RT input signal is grounded. It is not an IDT72215B/25B feature. The Retransmit control signal causes the internal FIFO read-address pointer to be set back to zero, without affecting the internal FIFO write-address pointer. Thus, the Retransmit control signal also provides a mechanism whereby a block of data delimited by the zero physical address and the current write-address-pointer address may be read out repeatedly, an arbitrary number of times. The only restrictions are that neither the read-ad- dress pointer nor the write-address pointer may ‘wrap around’ during this entire process, and that the retransmit facility is not available during depth-cas- caded operation, either in IDT-Compatible Operating Mode or in Enhanced Operating Mode. (See Tables 1 and 2.) Also, the flags behave differently for a short time after a retransmit operation. Otherwise, the re- transmit facility is available during standalone opera- tion, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. Note that, when FL/RT is being used as RT, RT is an assertive-HIGH signal, rather than assertive-LOW as it is in most other FIFOs having a retransmit facility. Programming the programmable-flag offsets, the tim- ing synchronization of the various status flags, the optional read-suppression functionality of OE , and the behavior of the pointers which access the offset- value registers and the Control Register may be indi- vidually controlled by asserting the signal LD, without any reset operation. When LD is being asserted, and writing is being enabled by asserting WEN, some portion of the input bus word D0 – D17 is used at the next rising edge of WCLK to program one or more of the programmable registers on successive write clocks. Likewise, the values programmed into these programmable registers may be read out for verification by asserting LD and REN, with the outputs Q0 – Q17 enabled. Reading out these pro- grammable registers should not be initiated while they are being written into. T able 3 defines the possible modes of operation for loading and reading out the contents of programmable registers. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

cascading remains available. BOLD ITALIC = Enhanced Operating Mode. biased to VCC , part will behave identical to IDT functionality. Figure 2. Pin Connections for 68-Pin PLCC Package

BOLD ITALIC = Enhanced Operating Mode. biased to VCC , part will behave identical to IDT functionality. Figure 3. Pin Connections for 64-Pin TQFP Package

SIGNAL NAME PLCC PIN NO. TQFP PIN NO. RS 1 57 OE 2 58 LD 3 59 REN 4 60 RCLK 5 61 D 17 76 3 D 16 86 4 D 15 91 D 14 10 2 D 13 11 3 D 12 12 4 D 11 13 5 D 10 14 6 D 9 15 7 D 8 17 8 D 7 19 9 D 6 20 10 D 5 21 11 D 4 22 12 D 3 23 13 D 2 24 14 D 1 25 15 D 0 26 16 PAE 27 17 FT/RT 28 18 WCLK 29 19 WEN 30 20 WXI/WEN 2 31 21 PAF 33 23 RXI/REN 2 34 24 FF 35 25 WXO/ HF 36 26 RXO/ EF2 37 27 Q 0 38 28 SIGNAL NAME PLCC PIN NO. TQFP PIN NO. Q 1 39 29 Q 2 41 31 Q 3 42 32 Q 4 44 34 Q 5 46 36 Q 6 47 37 EMODE 48 33 Q 7 49 38 Q 8 50 39 Q 9 52 41 Q 10 53 42 Q 11 55 44 Q 12 56 45 Q 13 58 47 Q 14 59 48 Q 15 61 50 Q 16 63 52 Q 17 64 53 EF 66 54 VSS 66 2 V CC 16 NC VSS 18 NC V CC 32 22 VSS 40 30 V CC 43 NC VSS 45 35 VSS 51 40 V CC 54 43 VSS 57 46 V CC 60 49 VSS 62 51 V CC 65 NC VSS 67 55 V CC 68 56 BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

D0 – D17 Data Inputs I Data inputs from an 18-bit bus. RS Reset I When RS is taken LOW, the FIFO’s internal read and write pointers are set to address the first physical location of the RAM array; FF, PAF, and HF go HIGH; and PAE and EF go LOW. The programmable-flag-offset registers and the Control Register are set to their default values. (But see the description of EMODE , below.) A reset operation is required before an initial read or write operation after power-up. EMODE Enhanced Operating Mode I When EMODE is tied LOW, the default setting for Control Register bits 00-05 after a reset operation changes to HIGH rather than LOW, thus enabling all Control-Register-controllable Enhanced Operating Mode features, and allowing access to the Control Register for reprogramming or readback. (See Tables 1, 2, and 5.) If this behavior is desired, EMODE may be grounded; however, Control Register bits 00-05 still may be individually programmed to selectively enable or disable certain of the Enhanced Mode features, even though those features associated with interlocked-paralleled operation always are enabled whenever EMODE is being asserted. (See Table 2.) Alternatively, EMODE may be tied to VCC, so that the FIFO is functionally IDT-compatible, and the Control Register is not accessible or visible, and all of its bits remain LOW. Controlling EMODE dynamically during system operation is not recommended. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK, whenever WEN (Write Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is written into. In the Enhanced Operating Mode, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 WEN Write Enable I When WEN is LOW and LD is HIGH, an 18-bit data word is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO internal memory continues to hold the previous data. (See Table 3.) Data will not be written into the FIFO if FF is LOW. In the Enhanced Operating Mode, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK whenever REN (Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is read from. In the Enhanced Operating Mode, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 REN Read Enable I When REN is LOW and LD is HIGH, an 18-bit data word is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, and/or also when EF is LOW, the FIFO’s output register continues to hold the previous data word, whether or not Q 0 – Q17 (the data outputs) are enabled. (See T able 3.) In the Enhanced Operating Mode, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in high-Z (high-impedance) state. In the Enhanced Operating Mode, OE not only continues to control the outputs in this same manner, but also can function as an additional ANDing input to the combined effective read-enable signal, along with REN and REN 2, whenever Control Register bit 05 is HIGH. (See Table 5.) 2

1 I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

2 The ostensible differences in signal assertiveness are reconciled before ANDing. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

PIN DESCRIPTIONS (cont’d) PIN NAME PIN TYPE 1 DESCRIPTION LD Load I When LD is LOW, the data word on D0 – D17 (the data inputs) is written into a programmable-flag-offset register, or into the Control Register (when in the Enhanced Operating Mode), on the LOW-to-HIGH transition of WCLK, whenever WEN is LOW. (See T able 3.) Also, when LD is LOW, a word is read to Q0 – Q17 (the data outputs) from the offset registers and/or the Control Register (when in the Enhanced Operating Mode) on the LOW-to-HIGH transition of RCLK, whenever REN is LOW. (See again T able 3, and particularly the Notes following this table.) When LD is HIGH, normal FIFO write and read operations are enabled. FL/RT First Load/ Retransmit I In the standalone or paralleled configuration, FL/RT should be LOW during a reset operation. (See T ables 1 and 2.) However, thereafter, in the standalone or paralleled configuration, if FL is taken HIGH, it functions instead as RT (Retransmit), and resets the FIFO’s internal read pointer to the first physical location of the RAM array. Note that although Retransmit is an ‘enhanced’ feature, it is always available for a FIFO during standalone operation, whether the FIFO is in IDT-Compatible Operating Mode or in Enhanced Operating Mode; it is not regulated either by the Control Register or by the EMODE control input. In IDT-compatible cascaded configuration, FL has an entirely different function; it is grounded for the first FIFO device (the ‘master’ device or ‘first- load’ device), and is set to HIGH for all other FIFO devices in the daisy chain. Thus, the Retransmit feature is not available for FIFOs operating in an IDT-compatible cascaded configuration. WXI /WEN 2 Write Expansion Input/Write Enable 2 I This signal is dual-purpose; its functionality is determined during a reset operation, according to its own state, and also according to the states of the three other control inputs RXI/REN2, FL/RT, and EMODE . (See Tables 1 and 2.) In the standalone or paralleled configuration, WXI/WEN 2 is grounded. In the cascaded configuration, WXI/WEN 2 is connected to WXO (Write Expansion Output) of the previous device, and functions as WXI. In the Enhanced Operating Mode, WXI/WEN 2 functions as a second write-enable signal, WEN2, which is ANDed with WEN to produce an effective internal write-enable signal. 2 RXI/REN2 Read Expansion Input/ Read Enable 2 I This signal is dual-purpose; its functionality is determined during a reset operation, according to its own state, and also according to the states of the three other control inputs WXI /WEN 2, FL/RT, and EMODE . (See Tables 1 and 2.) In the standalone or paralleled configuration, RXI/REN 2 is grounded. In the cascaded configuration, RXI/REN 2 is connected to RXO (Read Expansion Output) of the previous device, and functions as RXI. In the Enhanced Operating Mode, RXI/REN2 functions as a second read-enable signal, REN 2, which is ANDed with REN – and perhaps also with OE, if Control-Register bit 05 is HIGH – to produce an effective internal read-enable signal. 2 FF Full Flag O When FF is LOW, the FIFO is full; further advancement of its internal write-address pointer, and further data writes through its Data Inputs into its internal memory array, are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. PAF Programmable Almost-Full FlagO When PAF is LOW, the FIFO is ‘almost full,’ based on the almost-full-offset value programmed into the FIFO’s Almost-Full Offset Register. The default value of this offset at reset is one-eighth of the total number of words in the FIFO-memory array, minus one, measured from ‘full.’ (See T able 4.) In the IDT-Compatible Operating Mode, PAF is asynchronous. In the Enhanced Operating Mode, PAF is synchronized to WCLK after a reset operation, according to the state of Control Register bit 04. (See Table 5.) NOTES: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level 2. The ostensible differences in signal assertiveness are reconciled before ANDing. BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

O This signal is dual-purpose; its functionality is determined during a reset operation according to the states of the two control inputs WXI/WEN 2 and RXI/REN 2. (See Tables 1 and 2.) In the standalone or paralleled configuration, whenever HF is LOW the device is more than half full. In IDT-Compatible Operating Mode, HF is asynchronous; in the Enhanced Operating Mode, HF may be synchronized either to WCLK or to RCLK after a reset operation, according to the state of Control Register bits 02 and 03. (See Table 5.) In the IDT-compatible cascaded configuration, a pulse is sent from WXO to the WXI input of the next FIFO in the daisy-chain cascade, whenever the last location in the FIFO is written. PAE Programmable Almost-Empty Flag O When PAE is LOW, the FIFO is ‘almost empty,’ based on the almost-empty-offset value programmed into the FIFO’s Almost-Empty Offset Register. The default value of this offset at reset is one-eighth of the total number of words in the FIFO-memory array, minus one, measured from ‘empty.’ (See Table 4.) In IDT-Compatible Operating Mode, PAE is asynchronous. In the Enhanced Operating Mode, PAE is synchronized to RCLK after a reset operation, according to the state of Control Register bit 01. (See Table 5.) EF Empty Flag O When EF is LOW, the FIFO is empty; further advancement of its internal read- address pointer, and further readout of data words from its internal memory array to its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. RXO /EF 2 Read Expansion Output O This signal is dual-purpose; its functionality is determined by the state of the EMODE control input during a reset operation. (See Tables 1 and 2.) In the IDT- Compatible Operating Mode, in a cascaded configuration, a pulse is sent from RXO to the RXI input of the next FIFO in the daisy-chain cascade, whenever the last location of the FIFO is read. In the Enhanced Operating Mode, whenever EMODE is being asserted (LOW), EF 2 behaves as an exact duplicate of EF, but delayed by one full cycle of RCLK with respect to EF. Q 0 – Q17 Data Outputs O/Z Data outputs to drive an 18-bit bus. VCC Power V +5 V power-supply pins. VSS Ground V 0 V ground pins. NOTE: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level PIN DESCRIPTIONS (cont’d) BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

1. Only one output may be shorted at a time, for a period not exceeding 30 seconds.
2. Measured with clocks idle.
3. Output load is disconnected.
4. Capacitances are maximum values at 25°C, measured at

Figure 4. Output Load Circuit

AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER –20 –25 -35 fCC Clock Cycle Frequency 50 40 28.6 tA Data Access Time 2 12 3 15 3 20 tCLK Clock Cycle Time 20 25 35 tCLKH Clock HIGH Time 8 10 14 tCLKL Clock LOW Time 8 10 14 tDS Data Setup Time 5 6 7 tDH Data Hold Time 2 2 2 tENS Enable Setup Time 5 6 7 tENH Enable Hold Time 2 2 2 tRS Reset Pulse Width 1 20 25 35 tRSS Reset Setup Time 2 12 15 20 tRSR Reset Recovery Time 2 12 15 20 tRSF Reset to Flag and Output Time 30 35 40 tOLZ Output Enable to Output in Low-Z 2 000 tOE Output Enable to Output Valid 9 12 15 tOHZ Output Enable to Output in High-Z 2 191 1 2 1 1 5 tWFF Write Clock to Full Flag 12 15 20 tREF Read Clock to Empty Flag 12 15 20 tPAF Clock to Programmable Almost-Full Flag (IDT-Compatible Operating Mode) 14 17 23 tPAE Clock to Programmable Almost-Empty Flag (IDT-Compatible Operating Mode) 14 17 23 tHF Clock to Half-Full Flag (IDT-Compatible Operating Mode) 14 17 23 tPAFS Clock to Programmable Almost-Full Flag (Enhanced Operating Mode) 14 17 23 tPAES Clock to Programmable Almost-Empty Flag (Enhanced Operating Mode) 14 17 23 tHFS Clock to Half-Full Flag (Enhanced Operating Mode) 14 17 23 tXO Clock to Expansion-Out 12 15 20 tXI Expansion-In Pulse Width 7 9 13 tXIS Expansion-In Setup Time 7 9 14 tSKEW1 Skew Time Between Read Clock and Write Clock for Full Flag 3 91 1 1 6 tSKEW2 Skew Time Between Write Clock and Read Clock for Empty Flag 4 91 1 1 6 NOTES: 1. Pulse widths less than the stated minimum values may cause incorrect operation. 2. Values are guaranteed by design; not currently tested. 3. These times also apply to the Programmable-Almost-Full and Half-Full flags when they are synchronized to WCLK. 4. These times also apply to the Half-Full and Programmable-Almost-Empty flags when they are synchronized to RCLK. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

Table 1. Grouping-Mode Determination

1. In IDT-compatible cascading, a reset operation forces WXO/ HF and RXO/ EF2 HIGH for the nth FIFO, thus forcing WXI/WEN 2 and RXI/REN 2

HIGH for the (n + 1)st FIFO.

1. The terms ‘master’ and ‘slave’ refer to IDT-compatible cascading. In pipelined cascading4, there is no such distinction.
2. Once grouping mode has been determined during a reset operation, FL/RT then may go HIGH to activate a retransmit operation.
3. EMODE must be asserted for access to the Control Register to be enabled. Also, FIFOs being used in a pipelined-cascading

configuration should be in Interlocked Paralleled mode.

1. Setup-time and recovery-time specifications apply during a reset operation.
2. H = HIGH; L = LOW; X = Don’t Care.

Table 2. Expansion-Pin Usage According to

1. FL/RT may be grounded if the Retransmit facility is not being used.

Table 3. Selection of Read and Write Operations LL L ∧∧ Illegal combination, which will cause errors. HL X ∧ X Normal FIFO write operation. H XLX ∧ Normal FIFO read operation. H L X – X No write operation. H X L X – No read operation. H X H X X No read operation. ∧ = A ‘LOW’-to-‘HIGH’ transition; – = Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.

1. The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the se-

lection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other. for the reading-control state machine.

1. The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is

Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate.

1. After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty.
2. WEN 2, REN2, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control

input and of Control Register Bit 05.

Table 4. Status Flags

1. q = Programmable-Almost-Empty Offset value. (Default values: 512 × 18, q = 63; 1024 × 18, q = 127.)
2. p = Programmable-Almost-Full Offset value. (Default values: 512 × 18, p = 63; 1024 × 18, p = 127.)
3. Only 9 (512 × 18) or 10 (1024 × 18) of the 12 offset-value-register bits should be programmed. The unneeded most-significant-end bits should
4. The flag output is delayed by one full clock cycle in Enhanced Operating Mode, when synchronous operation is specified for intermediate flags.

Table 5. Control-Register Format

01 L LH PAE

H Set and reset by ↑↑RCLK. Synchronous flag clocking.

04 L L H PAF

H Set and reset by ↑↑WCLK. Synchronous flag clocking. 09, 08, 07LLLLL LLLLL LLLLL – Reserved. Reserved.

1. When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the

ternal system which includes the FIFO.

1. If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is

06-11 are unaffected by EMODE.

trol-Register words should be zero-filled. Table 5. For permanent Enhanced-Operating-Mode timing for ‘pipelined’ cascaded operation. specified time intervals, following a rising edge of WCLK. are not synchronized to each other in any way. operation, WEN has no effect when the FIFO is full.

READ CLOCK (RCLK) A rising edge (LOW-to-HIGH transition) of RCLK initi- ates a FIFO read cycle if LD is HIGH, or a programma- ble-register read cycle if LD is LOW. All output-side synchronous control inputs must meet setup and hold times with respect to the rising edge of RCLK. The 18 data outputs, and the output-side status flags, are meaningful after specified time intervals, following a rising edge of RCLK. Conceptually, the RCLK input receives a free-running, periodic ‘clock’ waveform, which is used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that the RCLK waveform must be periodic. An ‘asynchronous’ mode of operation is in fact possible, if REN is continuously asserted (that is, is continuously held LOW), and RCLK receives aperiodic ‘clock’ pulses of suitable duration. There likewise is no requirement that RCLK must have any particular synchro- nization relation to the write clock WCLK. These two clock inputs may in fact receive the same ‘clock’ signal; or they may receive totally-different signals, which are not syn- chronized to each other in any way. READ ENABLE ( REN) Whenever REN is being asserted (is LOW), and the FIFO is not empty, an 18-bit data word is loaded into the output register from the memory array at every RCLK rising edge (LOW-to-HIGH transition). Data words are read from the two-port memory array sequentially, regard- less of any ongoing write operation. Whenever REN is not being asserted (is HIGH), the output register retains whatever data word it contained previously, and no new data word gets loaded into it from the memory array. To prevent underrunning the internal FIFO boundaries, further read operations are inhibited whenever the Empty Flag ( EF) is being asserted (is LOW). If a valid write operation then occurs, upon the completion of that write cycle EF again goes HIGH after a time tREF , and another read operation is allowed to begin whenever RCLK makes another LOW-to-HIGH transition. Effectively, REN is overridden by EF; thus, during normal FIFO operation, REN has no effect when the FIFO is empty. In the Enhanced Operating Mode, one (or, some- times two) additional read-enable inputs may be ANDed with REN to control reading, depending on the state of Control-Register Bit 05. The additional read-enable input(s) are REN2 (and OE). Whene ver EMODE is being asserted (is LOW), RXI/REN2 functions as REN2, an additional duplicate (albeit assertive-HIGH) Read-Enable input, in order to provide an ‘interlocking’ mechanism for reliable synchronization of two paralleled FIFOs. Also, if Control Register bit 05 has been set, OE takes on the extra role of serving as yet another duplicate read-enable input, in addition to its usual function of controlling the FIFO’s data outputs, in order to inhibit further read operations whenever the FIFO’s data outputs are disabled, and thereby to prevent data loss under some circumstances. OUTPUT ENABLE ( OE) OE is an assertive-LOW, asynchronous, output enable. In the IDT-Compatible Operating Mode, OE has only the effect of enabling or disabling the data outputs Q 0 – Q17. That is, disabling Q0 – Q17 does not inhibit a read operation, for data being transmitted to the output register; the same data will remain available later, when the outputs are again enabled, unless subsequently over- written. When Q 0 – Q17 are enabled, each of these 18 data outputs is in a normal HIGH or LOW state, according to the bit pattern of the data word in the output register. When Q 0 – Q17 are disabled, each of these outputs is in the high-Z (high-impedance) state. In the Enhanced Operating Mode, if Control Regis- ter bit 05 has been set, OE behaves as an additional read-enable control input, as well as enabling and disabling the data outputs Q0 – Q17. Under these circumstances, incrementing the read-address pointer is inhibited whenever Q0 – Q17 are in the high-Z state. Thus, ‘reading’ successive words which fail ever to reach the outputs is prevented, as a safeguard against data loss. LOAD (LD ) The Sharp LH540215/25 FIFOs contain three 18-bit programmable registers. The contents of these three registers may be loaded with data from the data inputs D 0 – D17, or read out onto the data outputs Q0 – Q17. The first two registers are the Programmable-Flag-Offset- Value Registers, for the Programmable Almost-Empty Flag (PAE) and the Programmable Almost-Full Flag (PAF) respectively. The third register is the Control Register, which includes several configuration-control bits for selectively enabling and disabling Sharp’s Enhanced-Operating-Mode features. None of these three registers makes use of all of its available 18 bits. Figure 5 shows which bit positions of each register are operational. The two Programmable- Flag-Offset-Value Registers each contain an offset value in bits 0-8 (LH540215) or bits 0 – 9 (LH540225); bits 9 – 17 (LH540215) or bits 10 – 17 (LH540225) are unused. The default values for both offsets are one-eighth of the total number of words in the FIFO memory array, minus one: 63 for a 512 × 18 FIFO, and 127 for a 1024 × 18 FIFO. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

Future use to control depth cascading and interlocked paralleling. Enables suppressing reading whenever data outputs are disabled. Selects reinitialized addressing of the programmable registers. BOLD ITALIC = Enhanced Operating Mode. = Reserved. Do not load with non-zero information.

1. Bits 9-17 (LH540215) or bits 10-17 (LH540225) of both offset-value registers should

in all cases be programmed LOW (zero).

1. This bit position is used for offset values in the LH540225 only. In the LH540215, it

always should be programmed LOW.

1. See the Control-Register Format table for the default states of the Control Register,

for EMODE = HIGH (IDT-Compatible Operating Mode) and for EMODE = LOW (Enhanced Operating Mode). The Control Register is not accessible or visible in IDT-Compatible Operating Mode.

1. The assertion of EMODE (LOW) forces Control Register bits 00-05 HIGH during a reset operation.

After that, these bits may be programmed at will. Figure 5. Programmable Registers

But, if EMODE is asserted (LOW), then still another 18-bit data word from the data inputs D0 – D17 is written into the Control Register at the third rising edge of WCLK. At the fourth rising edge of WCLK, writing again occurs to the Programmable-Almost- Empty-Flag-Offset-Value Register; and the same three-step writing sequence gets repeated on sub- sequent WCLK rising edges. The lower nine bits of these offset-value words are made use of by the 512-word LH540215, and the lower ten bits by the 1024-word LH540225. Six active bits are used for the Control Register, by both the LH540215 and the LH540225. There is no restriction on the values which may occur in these offset-value and Control-Reg- ister fields. However, reserved bit positions must be encoded LOW, in order to maintain forward compatibility. Writing contents to these two or three programmable registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but WEN is not being asserted (is HIGH), the FIFO’s internal programmable-register- write-address pointer maintains its present value, without any writing actually taking place at each rising edge of WCLK. (See T able 3.) Thus, for instance, one or two programmable registers may be written, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). Likewise, whenever LD and REN are simultaneously being asserted (are both LOW) the 18-bit data word (zero-filled as necessary) from the Programmable-Al- most-Empty-Flag-Offset-Value Register is read to the data outputs Q 0 – Q17 at the first rising edge (LOW-to- HIGH transition) of the read clock (RCLK). (See Table 3.) If LD and REN continue to be simultaneously asserted, another 18-bit data word from the Programmable-Almost- Full-Flag-Offset-Value Register is read to the data outputs Q 0 – Q17 at the second rising edge of RCLK. What happens next is determined by the state of the EMODE control input. If it is deasserted (HIGH), the next 18-bit word again comes from the Programmable-Almost- Empty-Flag-Offset-Value Register; it is read to the data outputs Q0 – Q17. But, if EMODE is asserted (LOW), then the next 18-bit data word instead comes from the Control Register; it is read to the data outputs Q0 – Q17 at the third rising edge of RCLK. At the fourth rising edge of RCLK, reading again occurs from the Programma- ble-Almost-Empty-Flag-Offset-Value Register; and the same three-step reading sequence gets repeated on subsequent RCLK rising edges. Reading contents from these two or three programma- ble registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but REN is not being asserted (is HIGH), the FIFO’s internal programmable- register-read-address pointer maintains its present value, without any reading actually taking place at each rising edge of RCLK. (See Table 3.) Thus, for instance, one or two programmable registers may be read, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). T o ensure correct operation, the simultaneous reading and writing of a register should be avoided. FIRST LOAD/RETRANSMIT ( FL/RT) FL/RT is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are WXI /WEN 2, RXI/REN 2, and EMODE. There are four possible grouping modes: standalone, inter- locked paralleled, cascaded ‘master’ or ‘first-load,’ and cascaded ‘slave.’ The designations ‘master’ and ‘slave’ pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone or paralleled operation, the FL/RT pin should be grounded for strict IDT72215B/25B-compatible operation. However, if it is taken HIGH, regardless of the state of the EMODE control input, the FIFO’s internal read-address pointer is reset to address the FIFO’s first physical memory location, without the other usual reset actions being taken; in particular, the FIFO’s internal write-address pointer is unaf- fected. Subsequent read operations may then again read out the same block of data, delimited by the FIFO’s first physical memory location and the current value of the write pointer, as was read out previously. There is no limit on the number of times that a block of data may be retransmitted. The only restrictions are that neither the read-address pointer nor the write-address pointer may ‘wrap around’ and address the FIFO’s first physical memory location a second time during the retransmission process, and that the retransmit facility is unavailable during cascaded opera- tion. In IDT-compatible cascaded operation, FL/RT is grounded for the ‘master’ or ‘first-load’ FIFO, to distinguish it from the other ‘slave’ FIFOs in the cascade, which must all have their FL/RT inputs HIGH during a reset operation. (See again Tables 1 and 2.) The cascade will not operate correctly either without any ‘master’ FIFO, or with more than one ‘master’ FIFO. WRITE EXPANSION INPUT/ WRITE ENABLE 2 (WXI/WEN 2) WXI /WEN 2 is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are FL/RT , RXI/REN 2, and EMODE . There are four possible grouping modes: standalone, inter- BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

locked paralleled, cascaded ‘master’ or ‘first-load,’ and cascaded ‘slave.’ The designations ‘master’ and ‘slave’ pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone operation, WXI/WEN 2 and RXI/REN 2 both must be grounded so that the FIFO comes up in the standalone grouping mode after a reset operation. In interlocked-paralleled operation, WXI/WEN 2 is tied to FF of the other paralleled FIFO, and RXI/REN2 is tied to EF of that same other FIFO. This interconnection scheme ensures that both FIFOs will operate together, and remain coordinated, regardless of tim- ing skews. In cascaded operation, WXI/WEN 2 is connected to the WXO (Write Expansion Output; actually WXO/ HF) output of the previous FIFO in the cascade. RXI/REN 2 is likewise connected to the RXO (Read Expansion Output; actually RXO/ EF2) output of that previous FIFO. A reset operation forces WXO/ HF and RXO/ EF2 HIGH for each FIFO; consequently, all FIFOs with their WXI/WEN 2 and RXI/REN 2 inputs thus connected come up in one of the two cascaded grouping modes, according to whether their FL/RT inputs are grounded or tied HIGH. (See again Tables 1 and 2.) READ EXPANSION INPUT/ READ ENABLE 2 (RXI/REN 2) RXI/REN2 is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are FL/RT , WXI/WEN 2, and EMODE . There are four possible grouping modes: standalone, inter- locked-paralleled, cascaded ‘master’ or ‘first-load,’ and cascaded ‘slave.’ The designations ‘master’ and ‘slave’ pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone operation, WXI/WEN 2 and RXI/REN 2 both must be grounded, so that the FIFO comes up in the standalone grouping mode after a reset operation. In interlocked-paralleled operation, WXI/WEN 2 is tied to FF of the other paralleled FIFO, and RXI/REN2 is tied to EF of that same other FIFO. This interconnection scheme ensures that both FIFOs will operate to- gether, and remain coordinated, regardless of timing skews. In cascaded operation, RXI/REN 2 is connected to RXO (Read Expansion Output; actually RXO/EF2)) of the previous FIFO in the cascade. WXI/WEN 2 is likewise connected to WXO (Write Expansion Output; actually WXO/HF) output of that previous FIFO. A reset operation forces RXO/ EF2 and WXO/ HF HIGH for each FIFO; consequently, all FIFOs with their RXI/REN 2 and WXI/WEN 2 inputs thus connected come up in one of the two IDT-compatible cascaded grouping modes, accord- ing to whether their FL/RT inputs are grounded or tied HIGH. (See again T ables 1 and 2.) Data Outputs DATA OUT (Q 0 – Q17) Data, programmable-flag-offset values, and Control- Register codes are output from the FIFO as 18-bit words on Q0 – Q17. Unused bit positions in offset-value words and Control-Register words are zero-filled. Control/Status Outputs FULL FLAG (FF) FF goes LOW whenever the FIFO is completely full. That is, whenever the FIFO’s internal write pointer has completely caught up with its internal read pointer; so that, if another word were to be written, it would have to overwrite the unread word which is now in position for reading out by the next requested read operation. Under these conditions, the FIFO is filled to its nominal capacity, which is 512 18-bit words for the LH540215 or 1024 18-bit words for the LH540225 respectively. Write operations are inhibited whenever FF is LOW, regardless of the assertion or deassertion of Write Enable (WEN). If the FIFO has been reset by asserting RS (LOW), FF initially is HIGH. But, whenever no read operations have been performed since the completion of the reset opera- tion, FF goes LOW after 512 write operations for the LH540215, or after 1024 write operations for the LH540225. (See T able 4.) FF gets updated after a LOW-to-HIGH transition of the Write Clock (WCLK). PROGRAMMABLE ALMOST-FULL FLAG ( PAF) PAF goes LOW whenever the FIFO is ‘almost’ full; that is, whenever subtracting the value of the FIFO’s internal read pointer from the value of its internal write pointer yields a difference which is less than the value of the Programmable-Almost-Full-Flag Offset ‘p.’ The sub- traction is performed using modular arithmetic, modulo the total nominal number of 18-bit words in the FIFO’s physical memory, which is 512 for the LH540215 or 1024 for the LH540225 respectively. The default value of ‘p’ after the completion of a reset operation is one-eighth of the total number of words in the FIFO-memory array, minus one: 63 10 for the LH540215 or 12710 for the LH540225 respectively. However, ‘p’ may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of Load ( LD). DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

If the FIFO has been reset by asserting RS (LOW), and no read operations have been performed since the completion of the reset operation, PAF goes LOW after (512-p) write operations for the LH540215, or after (1024-p) write operations for the LH540225. (See Table 4.) If p is still at its default value, PAF is LOW whenever the FIFO is from seven-eighths full to completely full. In the IDT-Compatible Operating Mode, PAF changes from HIGH to LOW only after a LOW-to-HIGH transition of the Write Clock WCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Read Clock RCLK. Thus, in this operating mode, PAF behaves as an ‘asyn- chronous flag.’ In the Enhanced Operating Mode, on the other hand, PAF gets updated only after a LOW-to-HIGH transition of the Write Clock WCLK, and thus behaves as a ‘synchronous flag,’ whenever Control Register bit 04 is HIGH. (See Table 5.) WRITE EXPANSION OUT/HA LF-FULL FLAG (WXO/ HF) WXO/ HF is a dual-purpose signal. In ‘standalone’ op- eration, it behaves as a Half-Full Flag (HF), in accordance with T able 4. In IDT-compatible ‘cascaded’ operation, it behaves as a Write Expansion Output ( WXO) signal to coordinate writing operations with the next FIFO in the cascade. Under these same conditions, also, the dual- purpose WXI/WEN 2 and RXI/REN 2 inputs behave as Write Expansion Input (WXI) and Read Expansion Input (RXI) signals respectively. When two or more LH540215 or LH540225 FIFOs are ‘cascaded’ to operate as a deeper ‘effective FIFO,’ in an IDT-style ‘daisy-chain’ ring configuration, the Write Ex- pansion Input (WXI) of each FIFO is connected to WXO of the previous FIFO in the ring, with WXI of the ‘first-load’ or ‘master’ FIFO being connected to WXO of the last FIFO so as to complete the ring. Similar connections are made for each FIFO in the ring, parallel to these WXO-to-WXI connections, for Read Expansion Input (RXI) and Read Expansion Output (RXO/ EF2, when it is behaving as RXO). When the last physical location has been written in a FIFO operating in cascaded mode, a LOW-going pulse is emitted by that FIFO on its WXO output, and the FIFO is deactivated for writing at the next valid WCLK; and the next FIFO in the ring is simultaneously activated for writing. Otherwise, WXO remains constantly HIGH when- ever the FIFO is operating in cascaded mode. This LOW- going WXO pulse serves as a ‘write token’ in the ‘token-passing’ FIFO-cascading scheme; it is passed on to the next FIFO in the ring via its WXI input. When this next FIFO receives the write token, it is activated for writing at the next valid WCLK. The foregoing description applies both to the ‘first-load’ or ‘master’ FIFO in the ring, and to any and all ‘slave’ FIFOs in the ring. However, WXO has no necessary function for FIFOs operating in the ‘standalone’ mode. Consequently, in that mode, the same output pin is used for HF; it follows that HF is not available as an output from any FIFO which is operating in the IDT-compatible cas- caded mode. A FIFO is initialized into ‘cascaded master’ mode, into ‘cascaded slave’ mode, into interlocked-par- alleled mode, or into standalone mode according to the state of its WXI/WEN 2, RXI/REN 2, and FL/RT control inputs during a reset operation, and of EMODE . (See T able 1, T able, 2, and T able 5.) In standalone or interlocked-paralleled operation, HF goes LOW whenever the FIFO is more than half full; that is, whenever subtracting the value of the FIFO’s internal read pointer from the value of its internal write pointer yields a difference which is less than half of the total nominal number of 18-bit words in the FIFO’s physi- cal memory, which is 256 for the LH540215 or 512 for the LH540225 respectively. (See T able 4.) The subtraction is performed using modular arithmetic, modulo this total nominal number of words, which is 512 for the LH540215 or 1024 for the LH540225 respectively. If the FIFO has been reset by asserting RS (LOW), and it is operating in standalone mode or in interlocked-par- alleled mode, and no read operations have been per- formed since the completion of the reset operation, HF goes LOW after 257 write operations for the LH540215, or after 513 write operations for the LH540225. (See again Table 4.) In the IDT-Compatible Operating Mode, HF changes from HIGH to LOW only after a LOW-to-HIGH transition of the Write Clock WCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Read Clock RCLK. Thus, in this operating mode, HF behaves as an ‘asyn- chronous flag.’ In the Enhanced Operating Mode, on the other hand, HF gets updated only after a LOW-to-HIGH transition of the Read Clock RCLK, or else after a LOW-to-HIGH transition of the Write Clock WCLK, according to the setting of bits 03 and 02 of the Control Register (see Table 5). Thus, in this mode HF behaves as a ‘synchronous flag,’ and may be syn- chronized either to the input side of the FIFO (i.e., to WCLK), or to the output side of the FIFO (i.e., to RCLK). PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE) PAE goes LOW whenever the FIFO is ‘almost empty’; that is, whenever subtracting the value of the FIFO’s internal write pointer from the value of its internal read pointer yields a difference which is less than q + 1, where ‘q’ is the value of the Programmable-Almost-Empty-Flag Offset. The subtraction is performed using modular arith- metic, modulo the total nominal number of 18-bit words BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

in the FIFO’s physical memory, which is 512 for the LH540215 or 1024 for the LH540225 respectively. The default value of q after the completion of a reset operation is one-eighth of the total number of words in the FIFO-memory array, minus one; 63 for the LH540215 or 127 for the LH540225 respectively. However, q may be set to any value which does not exceed this total nominal number of words for the device, as explained in the description of Load ( LD). If the FIFO has been reset by asserting RS (LOW), and no write operations have been performed since the com- pletion of the reset operation, then PAE is LOW. (See Table 4.) If q is still at its default value, PAE is LOW whenever the FIFO is from one-eighth full to completely empty. In the IDT-Compatible Operating Mode, PAE changes from HIGH to LOW only after a LOW-to-HIGH transition of the Read Clock RCLK, and from LOW to HIGH only after a LOW-to-HIGH transition of the Write Clock WCLK. Thus, in this operating mode, PAE behaves as an ‘asyn- chronous flag.’ In the Enhanced Operating Mode, on the other hand, PAE gets updated only after a LOW-to-HIGH transition of the Read Clock RCLK, and thus behaves as a ‘synchronous flag,’ whenever Control Register bit 01 is HIGH. (See Table 5.) EMPTY FLAG ( EF) EF goes LOW whenever the FIFO is completely empty. That is, whenever the FIFO’s internal read pointer has completely caught up with its internal write pointer; so that, if another word were to be read out, it would have to come from the physical memory location which is now in position to be written into by the next requested write operation. Read operations are inhibited whenever EF is LOW, regardless of the assertion or deassertion of Read Enable (REN). If the FIFO has been reset by asserting RS (LOW), and no write operations have been performed since the completion of the reset operation, then EF is LOW. (See Table 4.) EF gets updated after a LOW-to-HIGH transition of the Read Clock RCLK. READ EXPANSION OUT/ EMPTY FLAG 2 (RXO /EF2) RXO/ EF2 is a dual-purpose signal. In ‘standalone’ operation, it has no function. In IDT-compatible ‘cas- caded’ operation, it behaves as a Read Expansion Output RXO) signal to coordinate writing operations with the next FIFO in the cascade. Under these same conditions, also, the dual-purpose RXI/REN 2 and WXI/WEN 2 inputs behave as Read Expansion Input (RXI) and Write Expan- sion Input (WXI) signals respectively. When two or more LH540215 or LH540225 FIFOs are operating in IDT-compatible ‘cascaded’ mode as a deeper ‘effective FIFO,’ the dual-purpose RXI/REN 2 and WXI/WEN 2 inputs behave as Read Expansion Input (RXI) and Write Expansion Input (WXI) signals respec- tively. An IDT-style cascade of these FIFO devices has a ‘daisy-chain’ ring configuration; the Read Expansion Input (RXI) of each FIFO is connected to RXO ( RXO/ EF2, behaving as RXO) of the previous FIFO in the ring, with RXI of the ‘first-load’ or ‘master’ FIFO being connected to RXO of the last FIFO so as to complete the ring. Similar connections are made for each FIFO in the ring, parallel to these RXO-to-RXI connections, for Write Expansion Input (WXI) and Write Expansion Output (WXO). When the last physical location has been read in a FIFO operating in IDT-style cascaded mode, a LOW-go- ing pulse is emitted by that FIFO on its RXO output; otherwise, RXO remains constantly HIGH. This LOW-go- ing RXO pulse serves as a ‘read token’ in the token-pass- ing FIFO-cascading scheme; it is passed on to the next FIFO in the ring via its RXI input. When this next FIFO receives the read token, it is activated for reading at the next valid RCLK. After a FIFO emits an RXO pulse, the FIFO is deacti- vated for reading at the next valid RCLK. Also, its data outputs go into high-Z state, regardless of the assertion or deassertion of its Output Enable ( OE) control input, until it again receives the token. Simultaneously, the next FIFO in the ring is activated for reading. The foregoing description applies both to the ‘first-load’ or ‘master’ FIFO in the ring, and to any and all ‘slave’ FIFOs in the ring. However, RXO has no necessary function for a FIFO which is operating in ‘standalone’ mode. Consequently, in that mode, RXO is never as- serted, and remains constantly HIGH. A FIFO is initialized into ‘standalone’ mode, into ‘cascaded master’ mode, or into ‘cascaded slave’ mode according to the state of its WXI/WEN 2, RXI/REN 2, and FL/RT control inputs during a reset operation. It also may be forced into inter- locked-paralleled mode by EMODE. (See Table 1, Table 2, and Table 5.) In the Enhanced Operating Mode, RXO/ EF2 be- haves as a second Empty Flag EF2. EF2 is an exact duplicate of the main Empty Flag EF, except that it is delayed with respect to EF by one full cycle of the Read Clock RCLK. DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

1. After reset, the outputs will be LOW if OE = LOW, and in a high-impedance state if OE = HIGH.
2. The clocks (RCLK, WCLK) may be free-running during a reset operation.

Figure 6. Reset Timing

1. tSKEW1 is the minimum time between a rising RCLK edge and a

that FF will change state until the next following WCLK edge. Figure 7. Synchronous Write Operation

1. tSKEW2 is the minimum time between a rising WCLK edge and a

that EF will change state until the next following RCLK edge. Figure 8. Synchronous Read Operation

1. tSKEW2 is the minimum time between a rising RCLK edge and a rising

WCLK edge for FF to change predictably during the current clock cycle. state until the next following WCLK edge.

1. tFRL (First-Read Latency) is the minimum time between a rising WCLK

0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2 . timing restrictions apply only when the FIFO has been empty (EF = LOW).

1. EF may be used to determine when the first data word D0 may be read.

D0 always is available on the next cycle after EF has gone HIGH. Figure 9. Latency for the First Data Word After a

1. tSKEW1 is the minimum time between a rising RCLK edge and a

that FF will change state until the next following WCLK edge. Figure 10. Full-Flag Timing

1. tSKEW2 is the minimum time between a rising WCLK edge and a

that EF will change state until the next following RCLK edge.

1. tFRL (First-Read Latency) is the minimum time between a rising WCLK

0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2 . timing restrictions apply only when the FIFO has been empty (EF = LOW).

1. EF may be used to determine when the first data word D0 may be read.

D0 always is available on the next cycle after EF has gone HIGH. BOLD ITALIC = Enhanced Operating Mode. Figure 11. Empty-Flag Timing

1. PAE offset = q. Also, number of data words written into FIFO already = q.

Figure 14. Programmable-Almost-Empty Flag Timing,

1. tSKEW2 is the minimum time between a rising WCLK edge and a

that PAE will change state until the next following RCLK edge.

1. PAE offset = q. Also, number of data words written into FIFO already = q.
2. The internal state of the FIFO:

Figure 15. Programmable-Almost-Empty Flag Timing,

1. PAF offset = p. Number of data words written into FIFO already = 511 - p for the LH540215 and 1023 - p for the LH540225.
2. 512 - p words in FIFO for LH540215. 1024 - p words in FIFO for LH540225.
3. 511 - p words in FIFO for LH540215. 1023 - p words in FIFO for LH540225.

Figure 16. Programmable Almost-Full-Flag Timing,

1. tSKEW1 is the minimum time between a rising RCLK edge and a

that PAF will change state until the next following WCLK edge.

1. PAF offset = p. Number of data words written into FIFO already = 511 - p
2. The internal state of the FIFO:

At , 511 - p words in FIFO for LH540215 and 1023 - p words in FIFO for LH540225. At , 512 - p words in FIFO for LH540215 and 1024 - p words in FIFO for LH540225. At , again, 511 - p words in FIFO for LH540215 and 1023 - p words in FIFO for LH540225. Figure 17. Programmable-Almost-Full-Flag Timing,

Figure 18. Half-Full-Flag Timing,

1. tSKEW1 is the minimum time between a rising RCLK edge and a

that HF will change state until the next following WCLK edge.

1. The internal state of the FIFO:

At , exactly half full again. Figure 19. Half-Full-Flag Timing, When Synchronized

1. tSKEW2 is the minimum time between a rising WCLK edge and a

that HF will change state until the next following RCLK edge.

1. The internal state of the FIFO:

Figure 20. Half-Full-Flag Timing, When Synchronized

2 D RT2

1. It is not necessary for REN to be LOW for the device to recognize a retransmit request.
2. In order to actually read data words from the memory arrary, in IDT-Compatible

(and OE = LOW, if Control Register bit 05 = HIGH). In any case, LD = HIGH.

1. DRT1 is the data item in physical location zero of the FIFO memory array.
2. The asynchronous intermediate flags (corresponding to LOW Control-Register bits) will

show correct status three RCLK cycles after a retransmit operation, as is shown above.

1. The intermediate flags which have been synchronized to RCLK, by setting the appropriate
2. The intermediate flags which have been synchronized to WCLK, by setting the appropriate
3. Immediately after a reset operation, before any write operations have taken place, a retransmit

operation is a 'no-op', and does not change the state of any FIFO registers or flags.

1. In the special case that the FIFO memory array contains only one valid data item, the status

of HF and PAF should be ignored on a retransmit. Figure 21. Retransmit Timing

When standalone-mode LH540215/25 devices are paralleled, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. After writing or reading have been in a disabled state, the process of re-enabling should be gated by the slowest FIFO. For m paralleled FIFOs, the form of this external composite-flag logic may be an OR gate with m asser- tive-LOW inputs and an assertive-LOW output. In keep- ing with deMorgan’s Theorem, such a gate may be implemented as an AND gate with m assertive-HIGH inputs and an assertive-HIGH output. Figure 27 illustrates the case m = 2. The LH540215/25 architecture supports two very dif- ferent methods of depth cascading: Token passing, which follows the scheme used in the pin-compatible and functionally-compatible Integrated Device Technology IDT72205B/15B/25B/35B/45B FIFOs, which the LH540215/25 can directly replace. Pipelining, which follows the scheme used in the Texas Instruments SN74ACT7801/11/81 FIFOs, and also in the Sharp LH543620 1024×36 FIFO. The SN74ACT7801/11/81 pinout closely resembles the LH540215/25 pinout, but is not identical. Depth Cascading Using Token Passing Using the token-passing approach, depth cascading is implemented by configuring the required number of LH540215/25s in a circular ‘ring’ fashion, with the Expan- sion Out outputs ( WXO/ HF and RXO/ EF2) of each device tied to the Expansion In inputs (WXI/WEN 2 and RXI/REN 2) of the next device. (See Figure 28.) Because a reset operation forces the WXO/ HF and RXO/ EF2 outputs HIGH for each device, the WXI/WEN 2 and RXI/REN 2 inputs for the next device are HIGH during the reset operation; thus, these two inputs are HIGH for all devices in the ring. (See Tables 1 and 2, and also Figure 28.) All devices in the cascade must be in the IDT-Com- patible Operating Mode; thus, their EMODE inputs must be tied to Vcc. One FIFO in the cascade must be designated as the ‘first-load’ device, by tying its First Load input (FL/RT ) to ground. All other devices must have their FL/RT inputs tied HIGH. Under these circumstances, the Retransmit function is not available for use. In this mode, the control inputs which govern writing (WCLK and WEN) and the control inputs which govern reading (RCLK and REN) are shared by all devices, while logic within each LH540215/25 governs the steering of data. The common Data Inputs of all devices are tied together; but only one LH540215/25 is enabled during any given write cycle. Likewise, the common three-state Data Outputs of all devices are wire-ORed together; but only one LH540215/25 is enabled, including its three- state outputs, during any given read cycle. A data word is handled only by one device as it passes through the cascade of FIFOs, regardless of how many FIFOs are being cascaded together. In the token-passing depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540215/25 devices together and by ANDing the EF outputs of all devices together, using AND gates with assertive-LOW inputs and an assertive-LOW output. Here, the meaning of these composite flags is direct: the cascade of FIFOs is full, if and only if all k FIFOs belonging to the cascade are individually full; and similarly for empty. In keeping with deMorgan’s Theorem, these k-input as- sertive-LOW AND gates are implemented physically as k-input assertive-HIGH OR gates. Figure 28 illustrates the case k = 3. Similar external logic also may be used to generate a composite Programmable Almost-Full Flag and a com- posite Programmable Almost-Empty Flag, by ANDing the PAF outputs of all LH540215/25 devices together and by ANDing the PAE outputs of all devices together. Here, however, some careful analysis is required, to determine exactly what the resulting composite flags mean. Their significance may vary widely, depending on the number of FIFOs in the cascade, and on the ‘offset’ values which are present in the offset registers for these FIFOs. More complex logical combinations of PAF outputs with FF outputs, and of PAE outputs with EF outputs, may be found useful in particular applications. In any case, the Half-Full Flag and the Retransmit function are not available for devices being used in token- passing depth-cascaded mode. BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

BOLD ITALIC = Enhanced Operating Mode. Figure 27. Interlocked-Paralleled Word-Width Expansion

Grounding FL designates the 'first-load' FIFO ('master' FIFO). The remaining FIFOs are 'slave' FIFOs. BOLD ITALIC = Enhanced Operating Mode. Figure 28. Synchronous-FIFO Depth-Cascading Using

thus, their EMODE inputs must be grounded. clock pins are connected to the external system. even be some other, totally-different clock. by one full RCLK cycle with respect to EF. downstream device is not full. Table 6. Required External-Logic Speeds for

1. T a is the setup time for the signal ‘FF (DEVICE n),’ including the

delay of the assertive-LOW AND gate, with respect to the clock.

1. Tb is the clock-to-output time for the signal ‘WEN2 (DEVICE n),’

including the delay of the assertive-HIGH AND gate. allows for the cascading of LH540215/25s eleven deep. using PLDs may recognize other implementations.

NOTES: 1. The transfer clock may be any free-running clock. However, it is recommended that the faster of the Write Clock and the Read Clock be used, if both of these are free-running clocks. 2. Block 'A' contains the circuit shown in Figure 29b. 540215-30 18 18 18 18 BOLD ITALIC = Enhanced Operating Mode. Figure 29a. TI-Style Pipelined Depth-Cascading 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

1. The transfer clock may be any free-running clock. However, it is recommended that the

faster of the Write Clock and the Read Clock 2 be used, if both of these are free-running clocks.

1. Block 'A' contains the circuit shown in Figure 29b.

36 DATA OUT

BOLD ITALIC = Enhanced Operating Mode. Figure 30. Interlocked Paralleling Used Together

25.27 [0.995] 25.02 [0.985] 24.23 [0.954] 24.13 [0.950] 24.23 [0.954] 24.13 [0.950] 25.27 [0.995] 25.02 [0.985] 23.62 [0.930] 22.61 [0.890] MAXIMUM LIMIT MINIMUM LIMITDIMENSIONS IN MM [INCHES] 1.27 [0.050] BSC 0.53 [0.021] 0.33 [0.013] 0.051 [0.020] MIN 3.91 [0.154] 3.71 [0.146] 0.10 [0.004] 4.57 [0.180] 4.19 [0.165] 68PLCC-1 68PLCC (PLCC68-P-950) 68-pin, 950-mil PLCC LH540215/25 512 x 18/1024 x 18 Synchronous FIFO

DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 0.20 [0.008] 0.09 [0.004] 0.15 [0.006] 0.05 [0.002] 16.0 [0.630] BASIC 14.0 [0.551] BASIC 0.45 [0.018] 0.30 [0.012] 1.45 [0.057] 1.35 [0.53] 1.60 [0.063] MAX. 0.80 [0.031] BASIC 14.0 [0.551] BASIC 16.0 [0.630] BASIC 0.75 [0.030] 0.45 [0.018] 0.10 [0.004] 64TQFP (TQFP-64-P-1414) DETAIL 64-pin TQFP BOLD ITALIC = Enhanced Operating Mode 512 x 18/1024 x 18 Synchronous FIFO LH540215/25

ORDERING INFORMATION

Cycle Time (ns) U 68-pin Plastic Leaded Chip Carrier (PLCC68-P-S950) M 64-pin Thin Quad Flat Package (TQFP-64-P-1414) LH540215/25 Device Type X Package - ## Speed 540215MD 512 x 18/1024 x 18 Synchronous FIFO Example: LH540215U-25 (512 x 18 Sychronous FIFO, 25 ns, 68-pin PLCC) BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO