LH540202 SHARP | Alldatasheet
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Technical content
LH540202 CMOS 1024 × 9 Asynchronous FIFO
FEATURES
- • Fast Access Times: 15/20/25/35/50 ns
- • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology
- • Input Port and Output Port Have Entirely Independent Timing
- • Expandable in Width and Depth
- • Full, Half-Full, and Empty Status Flags
- • Data Retransmission Capability
- • TTL-Compatible I/O
- • Pin and Functionally Compatible with Sharp LH5497 and with Am/IDT/MS7202
- • Industrial T emperature Grade Option Currently Available With Sharp LH5497H only (Contact a Sharp Representative for More Information)
- • Control Signals Assertive-LOW for Noise Immunity
- • Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC PIN CONNECTIONS FUNCTIONAL DESCRIPTION The LH540202 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM tech- nology, capable of storing up to 1024 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540202 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely inde- pendently of each other, unless the LH540202 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, as- sertive-LOW control inputs: Write ( W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540202, or by attempting to read additional words from an already-empty LH540202. When an LH540202 is operating in a depth-cascaded configuration, the Half-Full Flag is not available. 540202-2D W D D 3 D 2 D 1 D 0 XI FF Q 0 Q 1 Q 2 Q 3 Q 8 VSS D 7 FL/RT RS EF XO/HF Q 5 Q 4 R Q 6 Q 7 D 6 D 5 D 4 VCC 28-PIN PDIP 28-PIN SOJ * TOP VIEW
Figure 1. Pin Connections for PDIP and
23 XO/HF
NOTE: * = No external electrical connections are allowed. Figure 2. Pin Connections for PLCC Package
- This is a final data sheet; except that all references to the SOJ package have Advance Information status.
tion of the LH540202 device. states of the Full Flag and the Half-Full Flag. should be reset during every system power-up sequence. recoverable after a reset operation. devices operating in cascaded mode. Figure 3. LH540202 Block Diagram
The LH540202 is reset whenever the Reset input (RS) is taken LOW. A reset operation initializes both the read- address pointer and the write-address pointer to point to location zero, the first physical memory location. During a reset operation, the state of the XI and FL/RT inputs determines whether the device is in standalone mode or in depth-cascaded mode. (See Tables 1 and 2.) The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full Flag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 – D8) are forced into a high-impedance state. A reset operation is required whenever the LH540202 first is powered up. The Read (R) and Write (W) inputs may be in any state when the reset operation is initiated; but they must be HIGH, before the reset operation is terminated by a rising edge of RS, by a time tRRSS (for Read) or tWRSS (for Write) respectively. (See Figure 10.) Write A write cycle is initiated by a falling edge of the Write (W) control input. Data setup times and hold times must be observed for the data inputs (D0 – D8). Write opera- tions may occur independently of any ongoing read op- erations. However, a write operation is possible only if the FIFO is not full, (i.e., if the Full Flag FF is HIGH). At the falling edge of W for the first write operation after the memory is half filled, the Half-Full Flag is asserted HF = LOW). It remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the LH540202 are filling the FIFO memory to less than or equal to one-half of its total capacity. The Half-Full Flag is deasserted HF = HIGH) by the appropriate rising edge of R. (See Table 3.) The Full Flag is asserted (FF = LOW) at the falling edge of W for the write operation which fills the last available location in the FIFO memory array. FF = LOW inhibits further write operations until FF is cleared by a valid read operation. The Full Flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory loca- tion. (See T able 3.) Read A read cycle is initiated by a falling edge of the Read (R) control input. Read data becomes valid at the data outputs (Q0 – Q8) after a time tA from the falling edge of R. After R goes HIGH, the data outputs return to a high-impedance state. Read operations may occur inde- pendently of any ongoing write operations. However, a read operation is possible only if the FIFO is not empty (i.e., if the Empty Flag EF is HIGH). The LH540202’s internal read-address and write- address pointers operate in such a way that consecutive read operations always access data words in the same order that they were written. The Empty Flag is asserted EF = LOW) after that falling edge of R which accesses the last available data word in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another valid data word. (See T able 3.) Data Flow-Through Read-data flow-through mode occurs when the Read (R) control input is brought LOW while the FIFO is empty, and is held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty Flag EF momentarily is deasserted, and the data word just written becomes available at the data outputs (Q 0 – Q8) after a maxi- mum time of tWEF + tA. Additional write operations may occur while the R input remains LOW; but only data from the first write operation flows through to the data outputs. Additional data words, if any, may be accessed only by toggling Write-data flow-through mode occurs when the Write (W) input is brought LOW while the FIFO is full, and is held LOW in anticipation of a read cycle. At the end of the read cycle, the Full Flag momentarily is deasserted, but then immediately is reasserted in response to W being held LOW. A data word is written into the FIFO on the rising edge of W, which may occur no sooner than tRFF + tWPW after the read operation. PIN DESCRIPTIONS PIN PIN TYPE 1 DESCRIPTION D 0 – D8 I Input Data Bus Q 0 – Q8 O/Z Output Data Bus W I Write Request R I Read Request EF O Empty Flag FF O Full Flag PIN PIN TYPE 1 DESCRIPTION XO/HF O Expansion Out/Half-Full Flag XI I Expansion In FL/RT I First Load/Retransmit RS I Reset VCC V Positive Power Supply VSS V Ground NOTES: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level CMOS 1024 × 9 Asynchronous FIFO LH540202
retransmit operation and the subsequent read operations. tions, some data words will be lost. selection rather than for retransmission control. Table 1. Grouping-Mode Determination
- A reset operation forces XO HIGH for the nth FIFO, thus forcing XI
- The terms ‘master’ and ‘slave’ refer to operation in depth-cas-
- H = HIGH; L = LOW; X = Don’t Care.
Table 2. Expansion-Pin Usage According to Table 3. Status Flags
1024 L L H
each of these flags could be derived from any one device. Figure 4. Standalone FIFO
18 DATA OUT
Figure 5. FIFO Word-Width Expansion
required number of LH540202s in depth-cascaded mode.
9 DATA OUT
Figure 6. FIFO Depth Cascading
ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING Supply Voltage to VSS Potential –0.5 V to 7 V Signal Pin Voltage to VSS Potential 2 –0.5 V to VCC + 0.5 V (not to exceed 7 V) DC Output Current 3 ±50 mA Storage T emperature Range –65 oC to 150oC Power Dissipation (Package Limit) 1.0 W DC Voltage Applied to Outputs In High-Z State –0.5 V to V CC + 0.5 V (not to exceed 7 V) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside of those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGE SYMBOL PARAMETER MIN MAX UNIT TA T emperature, Ambient 07 0 °C VCC Supply Voltage 4.5 5.5 V VSS Supply Voltage 00V VIL Logic LOW Input Voltage 1 –0.5 0.8 V VIH Logic HIGH Input Voltage2.0 V CC + 0.5 V NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ILI Input Leakage Current V CC = 5.5 V , VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current R ≥ VIH, 0 V ≤ VOUT ≤ VCC –10 10 µA VOH Output HIGH Voltage I OH = –2.0 mA 2.4 V VOL Output LOW Voltage I OL = 8.0 mA 0.4 V ICC Average Supply Current 1 Measured at f = 40 MHz 100 mA ICC2 Average Standby Current 1 All Inputs = VIH 15 mA ICC3 Power Down Current 1 All Inputs = VCC – 0.2 V 5m A NOTE: 1. ICC , ICC2 , and ICC 3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open. LH540202 CMOS 1024 × 9 Asynchronous FIFO
- Capacitances are maximum values at 25oC, measured at 1.0 MHz,
Figure 9. Output Load Circuit
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL PARAMETER tA = 15 ns t A = 20 ns t A = 25 ns t A = 35 ns t A = 50 ns UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX READ CYCLE TIMING tRC Read Cycle Time 25 – 30 – 35 – 45 – 65 – ns tA Access Time – 15 – 20 – 25 – 35 – 50 ns tRR Read Recovery Time 10 – 10 – 10 – 10 – 15 – ns tRPW Read Pulse Width 2 1 5–2 0–2 5–3 5–5 0–n s tRLZ Data Bus Active from Read LOW 3 5–5–5–5–5– n s tWLZ Data Bus Active from Write HIGH 3,4 1 0–1 0–1 0–1 0–1 0–n s tDV Data Valid from Read Pulse HIGH 5 – 5–5–5–5– n s tRHZ Data Bus High-Z from Read HIGH 3 –1 5–1 5–1 5–1 5–2 0 n s WRITE CYCLE TIMING tWC Write Cycle Time 25 – 30 – 35 – 45 – 65 – ns tWPW Write Pulse Width 2 1 5–2 0–2 5–3 5–5 0–n s tWR Write Recovery Time 10 – 10 – 10 – 10 – 15 – ns tDS Data Setup Time 10 – 10 – 10 – 15 – 20 – ns tDH Data Hold Time 0 – 0–0–0–0– n s RESET TIMING tRSC Reset Cycle Time 25 – 30 – 35 – 45 – 65 – ns tRS Reset Pulse Width 2 1 5–2 0–2 5–3 5–5 0–n s tRSR Reset Recovery Time 10 – 10 – 10 – 10 – 15 – ns tRRSS Read HIGH to R S H I G H 1 5–2 0–2 5–3 5–5 0–n s tWRSS Write HIGH to RS HIGH 15 – 20 – 25 – 35 – 50 – ns RETRANSMIT TIMING 5 tRTC Retransmit Cycle Time 25 – 30 – 35 – 45 – 65 – ns tRT Retransmit Pulse Width 2 1 5–2 0–2 5–3 5–5 0–n s tRTR Retransmit Recovery Time 10 – 10 – 10 – 10 – 15 – ns FLAG TIMING tEFL Reset LOW to Empty Flag LOW – 25 – 30 – 35 – 45 – 65 ns tHFH,FFH Reset LOW to Half-Full and Full Flags HIGH –2 5–3 0–3 5–4 5–6 5 n s tREF Read LOW to Empty Flag LOW – 15 – 20 – 25 – 35 – 45 ns tRFF Read HIGH to Full Flag HIGH – 15 – 20 – 25 – 35 – 45 ns tWEF Write HIGH to Empty Flag HIGH – 15 – 20 – 25 – 35 – 45 ns tWFF Write LOW to Full Flag LOW – 15 – 20 – 25 – 35 – 45 ns tWHF Write LOW to Half-Full Flag LOW – 15 – 20 – 25 – 35 – 45 ns tRHF Read HIGH to Half-Full Flag HIGH–1 5–2 0–2 5–3 5–4 5 n s EXPANSION TIMING tXOL Expansion Out LOW –1 8–2 0–2 5–3 5–5 0 n s tXOH Expansion Out HIGH – 18 – 20 – 25 – 35 – 50 ns tXI Expansion In Pulse Width 15 – 20 – 25 – 35 – 50 – ns tXIR Expansion In Recovery Time 10 – 10 – 10 – 10 – 10 – ns tXIS Expansion in Setup Time 7 –1 0–1 0–1 5–1 5–n s NOTES: 1. All timing measurements are performed at ‘AC Test Condition’ levels. 2. Pulse widths less than minimum value are not allowed. LH540202 CMOS 1024 × 9 Asynchronous FIFO
7.49 [0.295] 7.11 [0.280] 0.51 [0.020] MIN 4.57 [0.180] MAX 3.43 [0.135] 3.18 [0.125] 2.54 [0.100] TYP. 0.53 [0.021] 0.38 [0.015] 0.30 [0.012] 0.20 [0.008] DETAIL DIMENSIONS IN MM [INCHES] 34.80 [1.370] 34.54 [1.360] 0° TO 15° MAXIMUM LIMIT MINIMUM LIMIT 3.30 [0.130] 7.62 [0.300] TYP. 28DIP (DIP28-W-300) 28-pin, 300-mil PDIP 28SOJ300 DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOJ (SOJ28-P-300) 1.27 [0.050] TYP. 0.53 [0.021] 0.33 [0.013] DETAIL 7.9 [0.311] 7.5 [0.295] 8.63 [0.340] 8.23 [0.324] 18.7 [0.736] 18.3 [0.720] 1.15 [0.045] 0.85 [0.033] 0.64 [0.025] MIN 7.0 [0.276] 6.6 [0.260] 2.6 [0.102] 2.2 [0.087] 3.7 [0.146] 3.3 [0.130] 0.20 [0.008] 0.8 [0.031] 0.6 [0.024] 0.102 [0.004] 11 4 28 15 28-pin, 300-mil SOJ CMOS 1024 × 9 Asynchronous FIFO LH540202
ORDERING INFORMATION
1.27 [0.050]
4 SIDES BSC
14.05 [0.553] 13.89 [0.547] 15.11 [0.595] 14.86 [0.585] 11.51 [0.453] 11.35 [0.447] 12.57 [0.495] 12.32 [0.485] 3.56 [0.140] 1.52 [0.060] 0.81 [0.032] 0.66 [0.026] 0.53 [0.021] 0.33 [0.013] 32PLCC MAXIMUM LIMIT MINIMUM LIMITDIMENSIONS IN MM (INCHES) 0.38 [0.015] MIN DETAIL 10.92 [0.430] 9.91 [0.390] 13.46 [0.530] 12.45 [0.490] 0.10 [0.004] 32PLCC (PLCC32-P-R450) 32-pin, 450-mil PLCC D 28-pin, 300-mil Plastic DIP (DIP28-W-300) K 28-pin, 300-mil SOJ * (SOJ28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) LH540202 Device Type X Package - ## Speed 540202MD CMOS 1024 x 9 FIFO Example: LH540202U-25 (CMOS 1024 x 9 FIFO, 32-pin PLCC, 25 ns) Access Time (ns) * Contact a Sharp representative for availability of SOJ package. LH540202 CMOS 1024 × 9 Asynchronous FIFO