LH5332600 SHARP | Alldatasheet

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Technical content

LH5332600 CMOS 32M (4M × 8/2M × 16) MROM

FEATURES

  • • 4,194,304 × 8 bit organization (Byte mode: BYTE = VIL) 2,097,152 × 16 bit organization (Word mode: BYTE = VIH)
  • • Access time: 100 ns (MAX.)
  • • Supply current: – Operating: 100 mA (MAX.) – Standby: 100 µA (MAX.)
  • • TTL compatible I/O
  • • Three-state output
  • • Single +5 V power supply
  • • Static operation
  • • Packages: 44-pin, 600-mil SOP 48-pin, 12 mm × 18 mm2 TSOP (Type I)
  • • Others: – Non programmable – Not designed or rated as radiation hardened – CMOS process (P type silicon substrate)

DESCRIPTION

The LH5332600 is a 32M-bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 5332600N-1 TOP VIEW A15 A16 BYTE A13 D 15/A-1 (NOTE) D 13 D 5 D 6 A14 44-PIN SOP A10 D 14 D 7

23 VCC

NOTE: The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D 15) when set to be HIGH in word mode. Figure 1. SOP Pin Connections

46 D 15/A-1 (NOTE)

15) when set to be HIGH in word mode. Figure 2. TSOP Pin Connections

12 TIMING

Figure 3. LH5332600 Block Diagram

(D15) DA TA OUTPUT ADDRESS INPUT SUPPL Y CURRENTD0 - D7 D 8 - D15 LSB MSB H X X X High-Z High-Z  Standby (ISB ) L H X X High-Z High-Z  Operating LL H  D 0 - D7 D 8 - D15 A0 A20 Operating LL L L D 0 - D7 High-Z A -1 A20 Operating LL L H D 8 - D15 High-Z A -1 A20 Operating NOTES: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage V CC -0.3 to +7.0 V Input voltage V IN -0.3 to VCC + 0.3 V Output voltage V OUT -0.3 to VCC + 0.3 V Operating temperature TOPR 0 to +70 °C Storage temperature T STG -65 to +150 °C RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70°C) PARAMETER SYMBOL MIN. TYP . MAX. UNIT Supply voltage V CC 4.5 5.0 5.5 V DC ELECTRICAL CHARACTERISTICS (V CC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CON DITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage V IH  2.2 V CC + 0.3 V  Input ‘Low’ voltage V IL  -0.3 0.8 V  Output ‘High’ voltage V OH IOH = -400 µA 2.4  V  Output ‘Low’ voltage V OL IOL = 2.0 mA  0.4 V  Input leakage current | ILI | V IN = 0 V to VCC  10 µA  Output leakage current | ILO |V OUT = 0 V to VCC  10 µA 1 Operating current ICC1 tRC = 100 ns  100 mA 2 ICC2 tRC = 1 µs  90 Standby current ISB1 CE = VIH  2m A  ISB2 CE = VCC - 0.2 V  100 µA  Input capacitance C IN f = 1 MHz, tA = 25°C  10 pF  Output capacitance C OUT  10 pF  NOTES: 1. CE = VIH, OE = VIH 2. V IN = VIH or VIL, CE = VIL, output is open LH5332600 CMOS 32M (4M x 8/2M x 16) MROM

AC ELECTICAL CHARACT ERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time t RC 100  ns  Address access time t AA  100 ns  Chip enable access time t ACE  100 ns  Output enable delay time tOE  50 ns  Output hold time tOH 5  ns  Output floating time tCHZ  40 ns tOHZ  40 ns NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude 0.4 V to 2.6 V Input rise/fall time 10 ns Input signal fall time 10 ns Input reference level 1.5 V Output reference level 1.5 V Output load condition 1TTL + 100 pF CAUTION It is recommended that a decoupling capacitor be connected between VCC and GND-Pin. CMOS 32M (4M x 8/2M x 16) MROM LH5332600

DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 44SOP (SOP044-P-0600) 16.40 [0.646] 15.60 [0.614] 13.40 [0.528] 13.00 [0.512] 14.40 [0.567] 28.40 [1.118] 28.00 [1.102] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 44 23 221 3.25 [0.128] 2.45 [0.096] 44SOP 2.9 [0.114] 2.5 [0.098] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 0.80 [0.031] 0 - 10° SEE DETAIL DETAIL PACKAGE DIAGRAM DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 48TSOP (TSOP048-P-1218) 18.40 [0.724] 17.60 [0.693] 16.60 [0.654] 16.20 [0.638] 17.00 [0.669] 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 1.20 [0.047] MAX. 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.10 [0.004] 0.30 [0.012] 0.10 [0.004] 48 25 241 0.425 [0.017] 48TSOP 0.50 [0.020] TYP. CMOS 32M (4M x 8/2M x 16) MROM LH5332600

X Package 5332600N-5 Example: LH5332600N (CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP) CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM N 44-pin, 600-mil SOP (SOP044-P-0600) T 48-pin, 12 mm x 18 mm2 TSOP (Type I) (TSOP048-P-1218)

ORDERING INFORMATION

LH5332600 CMOS 32M (4M x 8/2M x 16) MROM