LH531000B SHARP | Alldatasheet
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Technical content
LH531000B CMOS 1M (128K × 8) MROM
FEATURES
- • 131,072 words × 8 bit organization
- • Access time: 150 ns (MAX.)
- • Low power consumption: Operating: 192.5 mW (MAX.) Standby: 550 µW (MAX.)
- • Programmable CE/OE/OE
- • Static operation
- • TTL compatible I/O
- • Three-state outputs
- • Single +5 V power supply
- • Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP
- • Mask ROM specific pinout DESC RIPTION The LH531000B is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 531000B-1 TOP VIEW28-PIN DIP 28-PIN SOP A15 A12 GND A13 A11 A10 CE D 7 D 6 D 3
27 A14
16 D 4
/OE/OE A16 Figure 1. Pin Connections for DIP and
- Active level of CE/OE/OE is mask-programmable.
20 TIMING
Figure 2. LH531000B Block Diagram
PARAMETER SYMBOL RATING UNIT Supply voltage V CC –0.3 to +7.0 V Input voltage V IN –0.3 to VCC +0.3 V Output voltage V OUT –0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage V CC 4.5 5.0 5.5 V DC CHARACTERIST ICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CON DITIONS MIN. TYP. MAX. UNIT NOTE Input ‘Low’ voltage V IL –0.3 0.8 V Input ‘High’ voltage V IH 2.2 V CC + 0.3 V Output ‘Low’ voltage V OL IOL = 2.0 mA 0.4 V Output ‘High’ voltage V OH IOH = –400 µA 2.4 V Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO |V OUT = 0 V to VCC 10 µA 1 Operating current ICC1 tRC = 150 ns 35 mA 2 ICC2 tRC = 1 µs 25 ICC3 tRC = 150 ns 30 mA 3 ICC4 tRC = 1 µs2 0 Standby current ISB1 CE = VIH 2m A ISB2 CE = VCC – 0.2 V 100 µA Input capacitance C IN f = 1 MHz TA = 25°C 10 pF Output capacitance C OUT 10 pF NOTES: 1. CE/OE = VIH, OE = VIL 2. V IN = VIH or VIL, CE = VIL, outputs open AC CHARACTERIST ICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Read cycle time t RC 150 ns Address access time t AA 150 ns Chip enable access time t ACE 150 ns Output enable time t OE 70 ns Output hold time t OH 5n s CE to output in High-Z t CHZ 70 ns 1 OE to output in High-Z t OHZ 70 ns NOTE: 1. This is the time required for the output to become high-impedance. CMOS 1M MROM LH531000B
input, chip enable, and output enable, respectively have been met. Figure 3. Timing Diagram
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28DIP (DIP028-P-0600) 11 4 1528 28DIP-2 13.45 [0.530] 12.95 [0.510] 0.51 [0.020] MIN. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] 0.30 [0.012] 0.20 [0.008] DETAIL 36.30 [1.429] 35.70 [1.406] 0° TO 15° 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 28-pin, 600-mil DIP DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP (SOP028-P-0450) 12.40 [0.488] 11.60 [0.457] 8.80 [0.346] 8.40 [0.331] 10.60 [0.417] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 28 15 141 1.70 [0.067] 1.70 [0.067] 28SOP 28-pin, 450-mil SOP CMOS 1M MROM LH531000B
D 28-pin, 600-mil DIP (DIP028-P-0600) N 28-pin, 450-mil SOP (SOP028-P-0450) LH531000B Device Type X Package 531000B-7 Example: LH531000BD (CMOS 1M (128K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP) CMOS 1M (128K x 8) Mask Programmable ROM