LH530800A-Y SHARP | Alldatasheet
Document overview
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Technical content
FEATURES
- • 131,072 words × 8 bit organization
- • Access times: 500 ns (MAX.) at 2.6 V ≤ VCC < 4.5 V 150 ns (MAX.) at 4.5 V ≤ VCC ≤ 5.5 V
- • Low-power consumption: Operating: 193 mW (MAX.) Standby: 550 µW (MAX.)
- • Static operation
- • Three-state outputs
- • Mask-programmable control pin: Pin 24 = OE/OE
- • Wide range power supply: 2.6 V to 5.5 V
- • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP
DESCRIPTION
The LH530800A-Y is a 1M-bit mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS CMOS 1M (128K × 8) 3 V-Drive MROM 530800A-Y-1 TOP VIEW 10A Vcc A15 A12 GND A13 A11 A10 CE D 7 D 6 D 3 NC A14 NC
19 D 5
18 D 4
Figure 1. Pin Connections for DIP and
- Active levels of OE/OE are mask-programmable.
- X = H or L ABSOLUTE MAXIMUM RATINGS
21 TIMING
Figure 2. LH530800A-Y Block Diagram
Input voltage V IN -0.3 to VCC +0.3 V Output voltage V OUT -0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C RECOMMENDED OPERATING CONDI- TIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage V CC 2.6 5.5 V DC CHARACTERIST ICS (VCC = 2.6 V to 5.5 V, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP . MAX. UNIT NOTE Input ‘Low’ voltage V IL -0.3 0.4 V Input ‘High’ voltage V IH 0.8 × VCC VCC + 0.3 V Output ‘Low’ voltage V OL IOL = 400 µA0 . 4 V Output ‘High’ voltage V OH IOH = -100 µA 0.8 × VCC V Input leakage current | ILI | VIN = 0 V to VCC 10 µA Output leakage current | ILO |V OUT = 0 V to VCC 10 µA1 Operating current ICC1 tRC = 150 ns 35 mA 2 ICC2 tRC = 500 ns 18 mA 3 ICC3 tRC = 500 ns 12 mA 4 Standby current ISB1 CE = VIH 2m A ISB2 CE = VCC - 0.2 V 100 µA Input capacitance C IN f = 1 MHz TA = 25°C 10 pF Output capacitance C OUT 10 pF NOTES: 1. CE/OE = VIH, OE = VIL 2. 4.5 V ≤ VCC ≤ 5.5 V, outputs open 3. 3.4 V < VCC < 4.5 V, outputs open 4. 2.6 V ≤ VCC ≤ 3.4 V, outputs open AC CHARACTERIST ICS (TA = 0 to +70°C) PARAMETER SYMBOL 2.6 V ≤ VCC < 4.5 V 4.5 V ≤ VCC ≤ 5.5 V UNIT NOTE MIN. MAX. MIN. MAX. Read cycle time t RC 500 150 ns Address access time t AA 500 150 ns Chip enable access time t ACE 500 150 ns Output enable delay time t OE 200 80 ns Output hold time t OH 10 10 ns CE to output in High-Z t CHZ 150 80 ns 1 OE to output in High-Z t OHZ 150 80 ns NOTE: 1. This is the time required for the output to become high-imped- ance. CMOS 1M Mask-Programmable ROM L H530800A-Y
NOTE: Data becomes valid when the last intervals, tAA , tACE , or tOE , have concluded. Figure 3. Timing Diagram
13.45 [0.530] 12.95 [0.510] 0.51 [0.020] MIN. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] 0.30 [0.012] 0.20 [0.008] DETAIL DIMENSIONS IN MM [INCHES] 41.30 [1.626] 40.70 [1.602] 0° TO 15° MAXIMUM LIMIT MINIMUM LIMIT 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 32DIP (DIP032-P-0600) 11 6 1732 32DIP 32-pin, 600-mil DIP DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP (SOP032-P-0525) 14.50 [0.571] 13.70 [0.539] 11.50 [0.453] 11.10 [0.437] 12.50 [0.492] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.10 [0.004] 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 32 17 161 1.40 [0.055] 1.40 [0.055] 32SOP 32-pin, 525-mil SOP CMOS 1M Mask-Programmable ROM L H530800A-Y
ORDERING INFORMATION
D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) LH530800A Device Type X Package 530800A-Y-3 Example: LH530800AD-Y (CMOS 1M (128K x 8) Mask-Programmable ROM, Low-Voltage Operation, 32-pin, 600-mil DIP) CMOS 1M (128K x 8) Mask-Programmable ROM Low-Voltage Operation LH530800A-Y CMOS 1M Mask-Programmable ROM