LH52B256 SHARP | Alldatasheet
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Technical content
. ployed to obtain the best performance from this device. Read Cycles sidered when transmission line effects occur. polysilicon load memory cells. to its lowest level if CE is raised to within 0.2 V of Vcc. lines. OE must be brought LOW to enable the outputs. aCe 20H v0. Figure 2. Pin Connections for TSOP Package
NOTE: Pin numbers apply to the 28-pin DIP, SK-DIP, or SOP. Figure 3. LH52B256 Block Diagram
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CMOS 256K (32K x 8) Static RAM LH52B256 TRUTH TABLE CE WE | OF MODE 01-08 SUPPLY CURRENT | NOTE H Standby (Ise) 1 LL X Write | Bw Operating (eo) 1 L H H_ | Output Disable High-Z Operating (Icc) NOTE: 4. X=Horl ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT NOTE Supply Voltage -05 to +7.0 Vv 1 Input Voltage VIN —0.5 to Voc + 0.5 Vv 1,2 Operating Temperature Topr 0 to +70 °c Storage Temperature Tstg —65 to +150 °C NOTES: 1. The maximum applicable voltage on any pin with respect to GND 2. Vin (MIN.) = 3.0 V for pulse width <50 ns. RECOMMENDED OPERATING CONDITIONS (Ta = 0°C to +70°C) PARAMETER SYMBOL | MIN. | TYP. uniT | NOTE Supply Voltage Voc 45 5.0 Vv V . |. Input Voltage 1H 2.2 Voc +0.5 Vv Vit -05 08 Vv 1 NOTE: 1. Vin (MIN) =-8.0 V for pulse width <50 ns. DC CHARACTERISTICS (Vcc = 5 V +10%, Ta = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. | MAX. | UNIT Input Leakage Current lu Vin = 0 to Veo -1 nA CE or OE = Vin, Output Leakage Current lio Vvo = 0 to Veo -1 1 WA Minimum Cycle Vin = Vic or Vins 70 | mA lvo = 0 mA, CE = V Operating Current lec ro=0m te T T tac, twc = 1 ps Vin = Vit or Vin 15 30 mA Ivo = O mA, CE = Vit | CE=Vi Standby Current Set — " 30 mA be | CESVec-02V WA Vi 1OL = 2.1 mA Vv Output Voltage o 04 | Vou 10H = -1.0 mA 24 Vv SHARP 3
LH52B256 CMOS 256K (32K x 8) Static RAM AC CHARACTERISTICS (1) READ CYCLE (Vcc = 5 V +10%, Ta = 0°C to +70°C) DESCRIPTION SYMBOL LH52B256-70 LH52B256-90 LH52B256-10 UNIT NOTE Read Cycle Time (tac 70 | 90 | | 100 | ons | Address Access Time taa 70 90 | 100 ns Chip Enable Access Time | tacE | | 70 | | 90 | 100 ns Output Enable Access Time toe 40 50 50 ns Output Hold Time toH | 10 | 10 | 10 | ns CE Low to Output in Low-Z tz 10 10 10 ns 1 OE Low to Output in Low-Z toLz 5 5 5 ns 1 CE High to Output in High-Z tuz 0 35 0 40 0 40 ns 1 OE High to Output High-Z | toHZz 0 | 35 | 0 | 40 | 0 | 40 | ns | 1 (2) WRITE CYCLE (Vcc = 5 V 10%, Ta = 0°C to +70°C) DESCRIPTION SYMBOL UNIT NOTE Write Cycle Time two 70 90 100 ns CE Low to End of Write tow 60 70 80 ns Address Valid to End of Write taw | 60 | 70 | 80 | ns Address Setup Time ots 0 oF 0” ns Write Pulse Width twp 55 65 75 ns Write Recovery Time twr 0 0 Oo ns Input Data Setup Time | tow | 30 | | 35 | 40 ns Input Data Hold Time toH 0 0 0 ns WE High to Output in High-Z tow 5 5 5 ns 1 WE Low to Output in High-Z twz 0 40 ) 40 0 40 ns 1 OE High to Output in HighZ tonz 0 35 0 40 0 40. ns 1 NOTE: 1 Aatve, ousput to high-impedance and high-impedance to output active tests specttied for a +200 mV transition
CMOS 256K (32K x 8) Static RAM LH52B256 AC TEST CONDITIONS PARAMETER RATING NOTE Input Voltage Amplitude 0.6to24V Input Rise/Fall Time 10ns Timing Reference Level 15V Output Load Conditions 1TTL + CL (100 pF) 1 NOTE: 1. Includes scope and jig capacitance. CAPACITANCE 1 (Ta = 25°C, f = 1 MHz) PARAMETER SYMBOL | CONDITIONS MIN. TYP. MAX. UNIT Input Capacitance Cin VIN=0V 9 pF Input/Output Capacitance Clio V/O=0V 10 pF NOTE: 1. This parameter is sampled and not production tested. DATA RETENTION CHARACTERISTICS (Ta = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. re. MAX. UNIT | NOTE Data Retention Voltage Vocor CE = Vccor-0.2 V 2.0 55 Vv Ta = 25°C 1 _ Vecor=3.0V | Ta=0to Data Retention Current | Iccor OE>Vecor—-0.2V| ‘4g°c HA CE Setup Time tcpr 0 CE Hold Time ta tro 1 NOTE: 1. tro = Read cycle time SHARP 5
Figure 4. Data Retention Characteristics Figure 5. Read Cycle —
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- The writing occurs during an overlapping period of CE = ‘LOW’ and WE = 'LOW' (twp).
- tow is defined as the time from CE LOW transition to the end of writing.
- tas is defined as the time from address change to the start of writing.
- twa is defined as the time from the end of writing to the address change.
- When I/O pins are in the output state, input signals with the opposite logic
- If CE LOW transition occurs at the same time or after WE LOW transition,
Figure 6. Write Cycle 1 (OE Controlled)
- The writing occurs during an overlapping period of CE = 'LOW' and WE = 'LOW' (tye).
- tow is defined as the time from CE LOW transition to the end of writing
- tas is defined as the time from address change to the start of writing
- twa is defined as the time from the end of writing to address change.
- When I/O pins are in the output state, input signals with the opposite logic level must not be applied.
- If CE LOW transition occurs at the same time or after WE LOW transition, the output will remain high-impedance.
- If CE HIGH transition occurs at the same time or before WE HIGH transition, the output will remain high-impedance. sosose
Figure 7. Write Cycle No. 2 (OE Low Fixed)
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CMOS 256K (32K x 8) Static RAM Lusomose PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] oon _ 0° TO 15° 0.30 [0.012] 36.30 [1.429] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] TYP 0.40 [0.016] DIMENSIONS IN MM [INCHES] wa MT 2a0'P-2 28-pin, 600-mil DIP 28SK-DIP (DIP028-P-0300) sera 28 15 7.05 [0.278] 6.65 [0.262] ‘ "| 0° TO 15° 0.35 [0.014] 35.00 [1.378] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] TP. 0.36 [0.014] DIMENSIONS IN MM INCHES} MAXOMLAM LIMIT 2001P-1 28-pin, 300-mil DIP
LH52B256 CMOS 256K (32K x 8) Static RAM 28SOP (SOP028-P-0450) 1.27 [0.050] 0.50 [0.020] TYP. “a l 1.70 [0.067] 28] IIIT UL TTT mi 1 14 1.70 [0.067] | 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] va 28S0P 28-pin, 450-mil SOP
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CMOS 256K (32K x 8) Static RAM LH52B256 28TSOP (TSOP028-P-0813) 0.12 [0.005] TYP. eee | a fot | = | TOTO 1 14 " 8.20 [0.323] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] DETAIL 0.90 [0.035] MAX. 0.20 [0.008] DIMENSIONS IN MM [INCHES] eT 0.00 [0.000] 2eTsoP| 28-pin, 8 x 13 mm? TSOP (Type |)
ORDERING INFORMATION
LH52B256 x - ## LL Device Type Package Speed Power LL Low-Low-power standby
90 Access Time (ns)
Blank 28-pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (DIP028-P-0300) N_ 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type |) (TSOP028-P-0813) TR 28-pin, 8 x 13 mm? TSOP (Type |) (TSOP028-P-0813) Reverse bend pin CMOS 32K x 8 Static RAM Example: LH52B256D-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 300-mil DIP) 528256-8 SHARP "1