LH52B256LL SHARP | Alldatasheet

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Technical content

@ Automatic Power Down During Long performed by simply changing the address. An Automatic. ployed to obtain the best performance from this device. @ 2V Data Retention sidered when transmission line effects occur. control (G) can prevent bus contention. Figure 1. Pin Connections for DIP and

CMOS 32K x 8 Static RAM PRELIMINARY LHS2B256LL SHARP CORP b1E D M®@ 8180798 0009758 729 MESRPU (28-PIN TSOP (I) (NORMAL BEND) 28-PIN TSOP (I) (REVERSE BEND) OED 160 28D Ay cnn C14 15F] vo, Av 2 27D ce, vo; 13 16) v0, Ads 26, vo, 12 17D wy Ad 4 2s] v0, wo, 181 wo, ces 24 Wo, 4oCh10 19 Pw, wee 23 vo, a9 20D CE, Voc C] 7 220, as 21D Aro ne] 8 21 cn a7 22) 0E Ay] 9 2000, ade 2A, A, C10 190, ads 24D Ag ad 18) v0, AeC] 4 25 Ag As C12 17D A a3 26 ce, aA O13 16D A, Aw 2 27 We Ay 14 a NCL] 1° 287 Veo 2576.1 2 Figure 2, Pin Connections for TSOP Packages SHARP —CNSCSC“‘CS‘CSSS

Figure 3. LH52B256LL Block Diagram

CMOS 32K x 8 Static RAM PRELIMINARY LH52B256LL SHARP CORP MAXIMUM RATINGS * bE D MM 6180798 0009760 387 MESRPU [_raraweren =| anc i NOTES: * Gnatrt Soetana ony Functonaleporavon ofthe davies meee or iy ots onaone sve Woee eo oe ae ing or of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may attect reliability. 2. Outputs should notbe shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGES. [smoot | eanaweren [ww | vee [wax | owr | [ta | tempore roan | 0 |p| wo | [vec | Sapbvetwe | as [so | ss | v | [ves | sap vetie [0 | o Jo | v | in| teoe oma vos [-es || os | v_| [vn [tesehpavetepe | 22 | [vee+08 | v | DC ELECTRICAL CHARACTERISTICS [swwwou | ranweren | vesvconomons | wm | re | wax | war | Pes eerenenes [esc TT Fa] [eer omeing cure [es one [ise | Suntiycoren [Ev] | fm rtvediageorert | vn=aVieves | 1 [| + | an WOlesageCuren | vn-=aViovec | 1 || + | an [von | ommatin vote —[in--10m | aa} |_| v | [ve | Owpntow erage | ix-20ma |_| oa |v | [von | DataRaeninotage | E2Veo-o2v |e | | ss] v | [ion | OasRaenon Coren [voc-avEsvec-oav] | @ | = | wa | SHARP 3-95,

  1. Capagitances are maximum values at 25°C measured at 1.0MHz

with Vaiss = 0 V and Voc = 5.0 V. Figure 5. Data Retention Timing

CMOS 32K x 8 Static RAM PRELIMINARY LHS2B256LL SHARP CORP BIE D MM 8180798 0009762 st MESRPy AC ELECTRICAL CHARACTERISTICS ' (Over Operating Range) ele te po cavern [wc | Readcyetine mT Tt] oe | [um | Adtesssecesstie ——SSSSSCSC~SC‘idtS Yo | | [ton | Outputtoidtrom Address Change | 10 || to || ns | [tex | Etowiovaidnaia To | G00 | res | [iz | ElowtoOuputacive*® To | ts | ns | [tere | EvightoOuparignz?? fo [as | 0 | as | ns | a [oz | Gtowtooupmaave?® ts Ts | [os | [to | Grightooumatignz?® To [as [0 [as | os | Po wrrgevous [we | witecycetime Tm TT too Ts | [tw _[Etowoensorwie | oo | es [| | | uw | Adsress valdtoendotwite | wo | || os | [us| Adiressseup fo To TT os | [twa | AddrossHoidtomendorwie | | fo | | ns | [we | Weuise wey ss Tes Tos | Input Data Setup Time (fa || ns | Fe [eset fo [tw | Wow te utputtign 228 To Tao | 0 | as | ns | ] Lz | Wrigntoouutacive?® Ts | Ts Tf ne |

1 A Ect Chaat speed a AG Test Conon wot

  1. Active output to High-Z and High-Z to output active tests specified for a +200 mV transition from steady state levels into the test load, 3. Sample tested only, SHARP 397

High-Z state. Although these oxareles illustrate timing _be met. thereby reducing system noise. edge of W occurs atter the falling edge of E. Figure 8. Write Cycle No. 1

00 LINES

Figure 9. Write Cycle No. 2

LH52B256LL PRELIMINARY CMOS 32K x 8 Static RAM SHARP CORP S1E D M®@ 8140798 0009765 969 MSRP

ORDERING INFORMATION

LH52B256LL_ x -#t tL Device Type Package Speed Power L_ Low-Low-power standby

400 Access Time (ns)

D 28-pin, 300-mil DIP (DIP28-P-300) Blank 28-pin, 600-mil DIP (DIP28-P-600) N_ 28-pin, 450-mil SOP (SOP28-P-450) T 28-pin, 8 x 13 mm? TSOP Type | (TSOP28-P-0813) TR 28-pin, 8 x 13 mm? TSOP Type | (TSOP28-P-0813) Reverse bend pin CMOS 32K x 8 Static RAM Example: LH52B256LLD-70LL (CMOS 32K x 8 Static RAM, Low-Low-power standby, 70 ns, 28-pin, 300-mil DIP) 2256-10 a 3-100 SHARP